GTS Status

M. Bellato

Electronics Meeting – LNL 22-23 Sep 2005

Topics

• Actual GTS Mezzanine• New GTS Mezzanine• GTS system for the Demonstrator• Alignment• GTS Mezzanine VHDL model• Central Trigger Processor

GTS Hierarchy

GTS Components – Mezzanine

GTS Mezzanine – actual version

• Tested in all its functionalities– MGT’s– Clock distribution and filtering– 10Gb/s switches– Microprocessor + Ethernet + external

SDRAM– Boot flash + user flash– Mictors

GTS Mezzanine – performance• Works fine in all tested

conditions– With 4 MGT’s must be

cooled• Power consumption ~ 4A with

4 MGT’s working• GTS Clock jitter at the

Mictor pins < 10ps rms– Care must be taken for

power supply delivery• BER = 0 after 8 days test with

4 MGT’s looped

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

Thermographic pictures

New GTS Mezzanine

• Motivation– Want to squeeze even more

functionalities– Lower cost and power consumption– Add a TDC– Use as a central trigger root node– Basic building block for GTS mini-trees

GTS System for the Demonstrator

New GTS Mezzanine Schedule

• Schematic ready• Submission for layout middle of Oct 05• PCB ready in Dec 05• First prototype populated and ready to be

tested in Jan 06• If no major problems, a pre-production run

can start in March/April 06

Alignment

• LLP community agreed on a layered scheme for GTS clock phase equalization– 1st: GTS clock phase alignment at LLP’s– 2nd: GTS clock phase alignment at

Digitizers• GTS system in charge of both

Alignment Algorithm

• Two models– Phase equalization by consecutive MGT

resets– Phase equalization by direct

measurements

Alignment: Global view

Alignment: Root Mezzanine

MGT Opt Fiber

Mezzanine

Tx

Rx

Select

Alignment: Mezzanine Digitizers

DIGITISER.

CORE Mezz.

CLK aligned

To segment mezzanines

GTS Mezz.

TDC

DESKEW

Delay adj. cmd

Round trip time≃1µs

0.5µs nominal(Vp≃5ns/m)

= CLK path (copper)

= CLK path (fiber)

= SYNC RTN pulse

= SYNC pulse

Alignment Core

Vhdl Development

• Standalone GTS Mezzanine– Needed for LLP testing– Needed for Ancillary I/F testing– Functionalities

• Global clock and timestamp• GTS I/F protocol compliant• Validates all trigger requests

Deliverables

• Hierarchical html model of GTS Mezzanine firmware (datapath only)

• Corresponding vhdl + testbench for simulation

• Update of the GTS system document with a description of the firmware.

Preview

GTS_top

trigger_rejection

tstamp_err

trigger_validation

local_trigger

lreset

trigger_requestbcast_out

msg_inval_rej_tag

local_tag

bcast_strobemsg_strobe

backpressuretag_strobe

lt_strobe

gts_clk

reject_window

refclksel

fiber_in_n

fiber_in_p

fiber_out_n

fiber_out_p

lclk

C4

"0000000100000000"C7

ROOT

idle_tag

trg_tag

fiber_out_n

fiber_out_p

trg_request

idle

fiber_in_n

fiber_in_p

enable

event_num

lreset

val_tag

ocxo_clk

backpressure_in

send_commacmd_ack

cmd_strobe

command

C8

tstamp_errtstamp_err

trigger_validationtrigger_validation

trigger_rejectiontrigger_rejection

val_rej_tag (7:0)val_rej_tag (7:0)

local_tag (7:0)local_tag (7:0)

lt_strobelt_strobe

tag_strobetag_strobe

trigger_request (1:0)trigger_request (1:0)

local_trigger (1:0)local_trigger (1:0)

msg_in (7:0)msg_in (7:0)

msg_strobe (1:0)msg_strobe (1:0) bcast_strobebcast_strobe

gts_clkgts_clk

RED SIGNALS <=> MICTOR CONNECTORS

bcast_out (7:0)bcast_out (7:0)

S28 (15:0)S28 (15:0)

reject_window = 256 clock cycles

fiber_in_pfiber_in_p

fiber_in_nfiber_in_n

refclkselrefclksel

fiber_out_nfiber_out_n

fiber_out_pfiber_out_p

idle_tag (15:0)idle_tag (15:0)

trg_tag (15:0)trg_tag (15:0)

trg_requesttrg_request

backpressure_inbackpressure_in

idleidle

enableenable

event_num (23:0)event_num (23:0)

val_tag (15:0)val_tag (15:0)

backpressurebackpressure

send_commasend_comma

ocxo_clk

ocxo_clk

ocxo_clk

ocxo_clk

lreset

lreset

lreset

lreset

cmd_ackcmd_ack

command (3:0)command (3:0)

cmd_strobecmd_strobe

Trigger Processor Highlights

• Fully based on timestamps associated with trigger requests coming from each GTS mezzanine– Timing constraint between channels is relaxed– GTS uplinks don’t need equalization

• A high performance sorting network builds a time-ordered stream of trigger requests before processing– Eight stages pipeline– Can be distributed– Works at 100MHz with no deadtime

• Multiplicity computation is done by counting– Based on a custom fifo implementation

Trigger Processor Highlights

• Trigger validation is done by returning the timestamp associated to trigger request– Latency can be different among channels– Strict order of requests is not guaranteed

• A full SystemC model exists– Both behavioural and RTL

• Plan to test it with a GTS mini-tree

Time plan

• New GTS mezzanine built and tested in Q1-06– A prototype GTS mini-tree follows

• VHDL model of GTS mezzanine in Q4-05• Prototype system integration in Q3-06