Agata Week – LNL 14 November 2007 LLP ATCA Carrier Status M. Bellato on behalf of the LLP Carrier Working Group

Agata Week – LNL 14 November 2007

LLP ATCA Carrier Status

M. Bellato

on behalf of the LLP Carrier Working Group


Agata Front-end Model



Clock Distribution

From GTS Tree


MGT Clocking Layout

RocketIO101M

UX

MU

X

RocketIO102M

UX

MU

X

RocketIO103M

UX

MU

X

RocketIO105M

UX

MU

X

MGTclkM34/N34

MGTclkAP28/AP29

RocketIO106M

UX

MU

X

RocketIO109M

UX

MU

X

RocketIO110M

UX

MU

XRocketIO

112MU

XM

UX

RocketIO113M

UX

MU

X

MGTclkAP3/AP4

MGTclkJ1/K1

RocketIO114M

UX

MU

X

ATCA FABRIC CH1-CH2ATCA FABRIC CH1-CH2






USER SFP TRANSCEIVERUSER SFP TRANSCEIVER

RTM PCI EXPRESS LANE0RTM PCI EXPRESS LANE0




100250MHzPCI Express

JITTERATTENUATOR

200MHzGTS Clock

(**) The ATCA FABRIC channelsare routed from CHANNEL1 to CHANNEL12by switches

(***) User SFP could be used as 1GEnet or PCIExpressDAQ without FABRIC



AB

AB

AB

AB

AB

AB

AB

AB

AB

AB

INSPECTIONPADS

100MHzGTS Clock

OPTICALSFP

INSPECTIONPADS

LOCAL100MHz

(EPSON)

PHASE LOCKED

MGT clocking layout


-48V

DC

ENABLE

P3V3-5A 16.5W MEZZANINE 1

MEZZANINE 2

MEZZANINE 3

MEZZANINE 4

MAIN BOARDP3V3-7A 23.1W

MAIN BOARDP2V5-7A 17.5W

FPGAs CORE

P1V2-7A 8.4W

FPGA MGTP1V2-4A 4.8W

P2V5-1.5A

P2V5-1.5A

P1V8-0.5APROMS

VCCAUX Fpga 1

VCCAUX MGT

P2V5-1.5A VCCAUX Fpga 2

P1V2-0.5AVTTTXs

P1V2-0.5A VTTRXs

MGT BUFFERS P1V8-6A 10.8W

P12V-14.7A 176.7(160.6)W

P3V3-5A 16.5W

P3V3-5A 16.5W

P3V3-5A 16.5W

M48V-4.0A 194.4(176.7)W

DC-DC Efficency is estimated at least 90%

ATC210 (210W)

P3V3_BOOT

4x LTM4600 55W

6x LTM4600 55W

P5V0-6A 30W

Carrier Power Supply


• 1M x 18 true dual port RAM @ 100/200 MHZ• 800Mb/s LVDS streaming on data channels• Equalized and filtered distribution of 200MHZ

GTS clock• 1 PCI Express/ GE optical link• 15 x Full mesh connectivity on the backplane• Pervasive I2C bus for slow controls• 200W power supply• Multiple options for data readout

Carrier main features


Pre

-pla

cem

ent A

ttem

pt (

as o

f nov

. 06)


Pre

-pla

cem

ent A

ttem

pt (

as o

f nov

. 06)


Fin

al P

lace

men

t


Fin

al R

outin

g (a

s of

apr

il 07

)


Power and Signal Integrity Simulations


Example Resonant mode between L6pwr/L11gnd


Pro

toty

pe (

as o

f jul

y 07

)



• Started in august • still going on

• >18 different tests

•Jtag chains• FPGAs configurations• Power distribution• I2C control chains• 200 MHz Clock distribution • Microprocessor• Sdram mems• Flash mem• Dual port ram

• PLL • PCI Express optical link• Fast Ethernet switch + PHY’s• MII connections• Backplane 2.5 Gb/s serial links• Mezzanine connections• 800 Mb/s LVDS lanes• Trigger distribution• Master/slave functionality

Tests Campaign



CH-15 Eye Diagram with Equalization



Via hole should be symmetric wrt solder balls


ChipSync™ChipSync™

FPGA FabricFPGA FabricFPGA FabricFPGA Fabric

1 00101010101 10

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

Data width of of 2, 3, 4, 5, 6, 7, 8, 10

BUFIOBUFIO

CLK CLKDIV

ISERDESISERDES

BUFRBUFRClk

Div

Clk

Div

Serdes Advantage


ChipSync™ChipSync™


ISERDESISERDES

CLK

DATAINC/DEC

IDELAYIDELAY

State Machin

e

State Machin

e

IDELAY CNTRLIDELAY CNTRL

190-210 MHz(calibration clk)

• 64 delay elements of ~ 70 to 89 ps each• Calibration clock can be internal or external

Bit Alignment


INCINC DECDEC

StateMachine

StateMachine

Clock Sampling Phase Adjust


ChipSyncChipSync


ISERDESISERDES

BITSLIPState

MachineState

Machine

CLK

DATA

Up to 10-bit bitslip pattern for any length training patternsUp to 10-bit bitslip pattern for any length training patterns

Word Alignment


1 1 1 1 0 0 0 0 1 1 1 1 00 0 0 0 0 0 0

0 0 0 1 1 1 1 0 0 0 0 1 11 1 1 0 1 1 0

0 0 1 1 1 1 0 0 0 0 1 1 11 1 0 0 1 0 0

StateMachine

StateMachine

Bitslip 1Bitslip 1

Bitslip 2Bitslip 2

Bitslip 3Bitslip 3

DATA1

DATA2

DATA3

Word Alignment Animation



Eye Diagram of LVDS pins


• S-parameters of a lvds pair from Mictor conns to main FPGA through full wave EM solver

• Encrypted Hspice model of lvds25ext pad from Xilinx

• Hspice simulation

Spice Verification


Hspice result


Int *ATCA0 = 0xfe001000; // DPRAM on board 0

Int *ATCA1 = 0xfe002000; // DPRAM on board 1

….

Fragment0 = memcpy(buffer0, ATCA0);

Fragment1= memcpy(buffer1, ATCA1);

PCI Express Readout Test


• Tests ongoing– Excessive noise on DC/DC converters - not suitable for

high speed operation– Central reset manager missing– Some errors on components footprints– 90% completed

• Modifications already ongoing at CERN– The layout will be frozen until the end of tests

• Procurement of components for 2 pre-production boards ongoing

Status


• Expected layout completion : end of Dec 07• Signal integrity analysis end of Jan 08• 2 x PCB manufacturing : Feb 08• 2 x PCB assembly : Mar 08• 2 x Board tests Apr 08

Schedule

Documents

Agata Week – LNL 14 November 2007 LLP ATCA Carrier Status M. Bellato on behalf of the LLP Carrier Working Group