GTS Issues & Status

M. Bellato

AGATA Week – GSI 21-24 Feb 2005

GTS Hierarchy

GTS Functionality - Downlink

GTS Functionality - Uplink

GTS Components – ATCA crate

GTS Components – Fanin Fanout board

GTS Components – Mezzanine

Work in Progress on:

• GTS mezzanine

• Phase equalization algorithm

• Atca fanout board

• Vhdl development

• SystemC simulation

GTS Mezzanine

• Pcb layout entirely redone at Cern– Fixes manufacturing problems– Signal integrity analysis on critical nets– New functionalities added

GTS Mezzanine layout

Alignment Algorithm

• Two models– Phase equalization by consecutive MGT

resets– Phase equalization by direct

measurements

Consecutive MGT resetsRoot node

MGT Opt Fiber

Mezzanine

Tx

Rx

Root tx

Root rx

GTS clock

• Mgt wakes up with arbitrary phase• Almost uniformly distributed in one clk cycle• At the root node the phase of RXUSRCLK is

the sum of downstream and upstream MGT pairs clk phases

• Idea : minimize or maximize this sum– The contribution of each pair almost equal– By halving the measure we obtain the latency of

each pair

Consecutive MGT resets

TEST CONDITIONS

TX1

RX1

RX2

TX2SHIFTER / FILTER

RECOV. CLOCK

DATA

100m FIBRE

100 MHz OSC

DATA PATTERN

DATA OUT

RDOUT CLK

RDOUT CLK

TD

P1

P3oscilloscope

RocketIO MGT

“ROOT”

TU

TL

P2

RocketIO MGT

“NODE”

NUMBER OF MEASURES = 11481

ASYMMETRY = |TD-TU| / 10 [ns]

DOWN-LINK LATENCY DISTRIBUTIONS (TD)

0

200

400

600

800

1000

1200

1400

160083

5

837

838

840

841

843

844

846

847

849

850

852

853

855

latency [ns]

freq

. [#]

UP-LINK LATENCY DISTRIBUTION (TU)

0

100

200

300

400

500

600

70083

5

836

837

838

839

840

841

842

843

844

845

846

847

848

849

850

851

latency [ns]

freq

. [#]

LOOP LATENCY DISTRIBUTION (TL)

0

200

400

600

800

1000

120016

73

1675

1677

1679

1681

1683

1685

1687

1689

1691

1693

1695

1697

1699

1701

1703

latency [ns]

freq

. [#]

ASYMMETRY vs LOOP LATENCY

0,0%

50,0%

100,0%

150,0%

200,0%

250,0%

300,0%

350,0%16

7016

7116

7216

7316

7416

7516

7616

7716

7816

7916

8016

8116

8216

8316

8416

8516

8616

8716

8816

8916

9016

9116

9216

9316

9416

9516

9616

9716

9816

9917

0017

0117

0217

0317

0417

05

latency [ns]

asym

met

ry

Direct Measurements

MGT Opt Fiber

Mezzanine

Tx

Rx

Select

Atca Fanout Board

1. Rapid testbed for VHDL development

2. Used as fanin-fanout & root node

3. Programmable4. Customizable area 5. Provided by Xilinx &

Avnet

Vhdl Development

• Standalone GTS Mezzanine– Needed for LLP testing– Needed for Ancillary I/F testing– Functionalities

• Global clock and timestamp• GTS I/F protocol compliant• Validates all trigger requests

Simulation

• SystemC environment

• Behavioural model of different parts of LLP system, included the GTS mezzanine

• It’s very first use will be as reference for Vhdl coding.

• Ongoing development at Strasbourg, Orsay and Padova

Time plan

• GTS mezzanine tested & (hopefully) delivered in the next two months

• Fanout board adaptation in Q2-05

• Prototype system integration in Q1-06