Shiv Bhudia1, Ana Beaumont1, Xiang Chen2, Pedro Barquinha1, Arokia Nathan2

1I3N|CENIMAT, Department of Materials Science, Faculty of Science and Technology, Universidade NOVA de Lisboa and

CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica, Portugal2Engineering Department, University of Cambridge, Cambridge, CB3 0FA, United Kingdom

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This work is funded by FEDER funds through the COMPETE 2020 Programme and National Funds throught FCT - Portuguese Foundation for Science and Technology under the project number POCI-01-0145-FEDER-007688, Reference UID/CTM/50025. The work has also received funding from the European Communities H2020 program, under GA 692373 (BET-EU) and GA 685758 (1D-Neon).

Transistor models are of utmost importance for device behaviour prediction

and circuit design. Physical modelling has the advantage of being based on

parameters directly related with device physics. This allows to gain insight on

the underlying mechanisms during the analysis and parameter extraction

phase. However, the extraction methods may not consider possible non-

idealities of the devices, which can lead to modelling issues when working with

new materials, novel thin-film transistor (TFTs) structures or low-temperature

processed devices.

In this work a compact model was developed and applied to indium-gallium-

zinc oxide (IGZO) and zinc-tin oxide (ZTO) TFTs using a multilayer high-κ

dielectric based on Ta2O5 and SiO2, with annealing temperature of only 180 °C.

Devices were fabricated at I3N|CENIMAT (Portugal) and

characterization/modelling was carried out at Electrical Engineering Division of

University of Cambridge, within the BET-EU project (GA 692373).

Two DC models were developed, the main difference being the contact

resistance extraction using the classic transmission-line method or a more

effective procedure based on MOSFETs with non-ideal behaviour that considers

the possible bias dependency of the parameter.

A dynamic small signal model was also developed, based on conventional FET

models and its validity was studied with the help of S-Parameters and

capacitance-voltage characteristics (C-V) characteristics.

• Static model with good fitting even for low-T anneal devices: requires minimal number of I-V characteristics and only 5 parameters to be extracted

• ZTO required more detailed contact resistance assessment for good fitting (non-negligble, VGS-dependent parameter)

• Application of MOSFET-based model enables good fitting of S11, S21 and H21 parameters. • The compact models developed can be extended to a broad range of other device

families and can empower users to carry out analysis of device behaviour and circuit design for system realization, after implementation in Verilog-A or SPICE.

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or ZTO

All layers by r.f. magnetron sputtering; Photolithography patterning; Channel length (L): 20 to 160 µm; Annealing @ 180 °C in air.

fabrication @ i3N|CENIMAT (Portugal)

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𝑉′𝐺𝑆 = 𝑉𝐺𝑆 − 𝐼𝐷𝑆𝑅𝑆 = 𝑉𝐺𝑆 − 𝐼𝐷𝑆𝑅𝐷𝑆2

𝑉′𝐷𝑆 = 𝑉𝐷𝑆 − 𝐼𝐷𝑆𝑅𝐷𝑆

Assuming device symmetry, i.e., RS=RD=RDS/2

Threshold voltage, 2nd derivative

method

-20 0 20 40 60 80 100 120 140 160 180 200 220 240

0

2

4

0 2 4 6 8 10 12 14 16 180.0

0.2

VGS

- VT [V]

.

:

15 V

7 V

6 V

5 V

RT [

M]

L [m]

4 V

L [m]

Parameter extraction from measurements (some examples)

0 2 4 6 8 10 12 14 160

2

4

6

8

10

12

14

I DS/g

m

VGS

- VT [V]

𝐼𝐷𝑆,𝑙𝑖𝑛𝑔𝑚,𝑙𝑖𝑛

=𝑉𝐺𝑆 − 𝑉𝑇 − 0.5𝑉𝐷𝑆

𝛼 − 1≈

1

𝛼 − 1(𝑉𝐺𝑆 − 𝑉𝑇)

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VG

S[5

:15

] V

wit

h 1

V in

crem

en

t

RDSW (Ω.cm) α ΔL (µm) K (1/Ω)

A – IGZO 5.8 2.2 -0.54 5.2×10-7

B – ZTO 120 2.26 1.47 1.0×10-7

C – ZTO, RSD(VGS) 35-120 2.55 -0.56 to 2.42 4.5×10-8

• ZTO model refinement required mostly due to large contact resistance and VGS dependence

• Negligible for IGZO

Selection of extracted parameters

A - IGZOW/L=20/160 (µm/µm) W/L=20/20 (µm/µm)

B - ZTO C – ZTO, RDS(VGS)

Current gain (Ai) and unity current gain frequency (fT)

Required experimental determination of CD, CS+ch and gm

S11 results (IGZO) H21 results (IGZO and ZTO)

Magnitude

Phase

fT measured (MHz) fT calculated (MHz)

IGZO 4.41 4.11

ZTO 1.02 0.70

Similar to previously reported fT for oxide TFT with L=20 µm [2]

[2] P. G. Bahubalindruni et al., "Influence of Channel Length Scaling on InGaZnO TFTs Characteristics: Unity Current-gain Cutoff Frequency, Intrinsic Voltage-gain and On-resistance," Journal of Display Technology, vol. 12, pp. 515-518, 2016

[1] P. Servati et al., “Above-threshold parameter extraction and modeling for amorphous silicon thin-film transistors,”Electron Devices, IEEE Transactions on, vol. 50, no. 11, pp. 2227–2235, 2003.

VDS=5 mV

VDS=5 mVVDS=100 mV

𝐼𝐷𝑆,𝑙𝑖𝑛 = 𝐾𝑊

𝐿𝑒𝑓𝑓𝑉𝐺𝑆 − 𝑉𝑇 − 0.5𝑉𝐷𝑆

∗ 𝛼−1 𝑉𝐷𝑆∗ − 𝑅𝐷𝑆𝐼𝐷𝑆

𝑉𝐷𝑆∗ = 𝑉𝐷𝑆

−𝑚 + 𝑉𝐺𝑆 − 𝑉𝑇−𝑚 −1 𝑚

For linear region the model can be described by [1]:

Harmonic averaging is introduced for saturation:

m – empirical constant for

correct fitting

Contact resistance, Transmission line

method (TLM)

Power parameter