ECE 545

Digital System Design with VHDL

Fall 2015

Kris Gaj

Office hours: Thursday, 6:00-7:00 PM, Tuesday, 6:00-7:00 PM, and by appointment

Research and teaching interests:• reconfigurable computing• computer arithmetic• cryptography• network security

Contact:The Engineering Building, room 3225

kgaj@gmu.edu

Course Web Page

ECE web page Courses

Digital System Design with VHDL

(or Google “Kris Gaj”)

ECE 545

Part of:

MS in Electrical Engineering

MS in Computer Engineering

Digital Systems DesignDigital Signal Processing

Fundamental course for the specialization areas:

Elective

Elective course in the remaining specialization areas

One of five core courses (must be passed with B or better)

ECE 545

Part of:

PhD in Electrical and Computer Engineering

Knowledge tested at the Technical Qualifying Exam (TQE)Topic 2: Digital Design and Computer Organization

I am interested in…

I want to specializeprimarily in…

VLSI

Digital Systems Design

ASICs & FPGAs

VHDL/Verilog

CAD Tools

Reconfigurable Computing

Microelectronics

VLSI Fabrication

Nanoelectronics

CAD tools & Design Automation

Hardware Description Languages

FPGAs & Reconfigurable computing

Computer Arithmetic

Front-end ASIC Design (algorithmic downto gate level)

Back-end ASIC Design (circuit and mask layout levels)

Analog & Digital Circuit Design

VLSI Fabrication

Microelectronics

Nanoelectronics

Semiconductor Devices

MS CpEDigital Systems Design

MS EEMicroelectronics/Nanoelectronics

Recommendedprogram &

specialization

algorithmic

Design level

register-transfer

gate

transistor

layout

devices

CoursesComputerArithmetic

Digital SystemDesign with VHDL

DigitalIntegratedCircuitsPhysical

VLSI Design

VLSI Test Concepts

ECE545

ECE645

ECE 586

ECE 680

ECE682

ECE684 MOS Device Electronics

ECE 584 SemiconductorDevice Fundamentals

ECE681

VLSI Design for ASICs

ECE699

SW/HWCodesign

CpE

Digital Systems Design

Pre-ApprovedElectives

SuggestedElectives

ECE 545 Digital System Design with VHDLECE 586 Digital Integrated CircuitsECE 645 Computer ArithmeticECE 681 VLSI Design for ASICsECE 682 VLSI Test ConceptsECE 699 SW/HW CodesignECE 740 DSP HW Architectures

ECE 584, 684, … (technology)ECE 511, 611, … (microprocessors)ECE 535, 537, 646, …(applications:DSP, image processing, crypto, etc.)

K. Gaj, H. Homayoun, J-P. KapsT. Storey, A. Cohen

CpEMicroprocessors and Embedded Systems

ECE 510 Real-Time ConceptsECE 511 MicroprocessorsECE 611 Advanced MicroprocessorsECE 612 Real-Time Emb. SystemsECE 641 Computer System Arch.ECE 699 SW/HW CodesignECE 699 Green Computing and Heterogeneous Architectures

ECE 545, 645, 681 (digital design)CS 571 (operating systems)CS 540, 583 (languages, algorithms)CS 580 (artificial intelligence)ECE 542, 642, 742 (networks)ECE 548 (sequential mach. theory)

H. Homayoun, J. Kaps, P. Pachowicz, C. SabzevariProfessors

DIGITAL SYSTEMS DESIGN

1. ECE 545 Digital System Design with VHDL– K. Gaj, project, FPGA design with VHDL

2. ECE 699 Software/Hardware Codesign – K. Gaj, homework, SoC design with VHDL and C

3. ECE 645 Computer Arithmetic– K. Gaj, project, FPGA design with VHDL or Verilog

4. ECE 681 VLSI Design for ASICs– H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools

5. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri, homework

6a. ECE 682 VLSI Test Concepts – T. Storey, homework6b. ECE 740 Digital Signals Processing Hardware Architectures

– A. Cohen, project, FPGA design with VHDL and Matlab/Simulink

MICROPROCESSOR AND EMBEDDED SYSTEMS

1. ECE 510 Real-Time Concepts– P. Pachowicz, project, design of real-time systems

2. ECE 511 Microprocessors – J.P. Kaps, project, system based on MSP430 microcontroller

3. ECE 611 Advanced Microprocessors – H. Homayoun, project, computer architecture simulation tools

4. ECE 612 Real-Time Embedded System – C. Sabzevari, project, programming distributed real-time systems

5. ECE 641 Computer System Architecture – H. Homayoun, project, computer architecture simulation tools

• ECE 699 Software/Hardware Codesign – K. Gaj, homework, SoC design with VHDL and C

7. ECE 699 Heterogeneous Architectures and Green Computing – H. Homayoun, project, computer architecture simulation tools

TA

Sanjay Deshpande

MS Thesis Student in the Cryptographic Engineering

Research Group (CERG)

• help with the installation and configuration of CAD tools

• help with understanding of tutorials and the operation of tools

• help with VHDL and tool-oriented homework assignments

• limited help with debugging your project codes

Getting Help Outside of Office Hours

• System for asking questions 24/7

• Answers can be given by students and instructors

• Student answers endorsed (or corrected) by instructors

• Average response time in Fall 2014 = 1.5 hour

• You can submit your questions anonymously

• You can ask private questions visible only to

the instructors

Grading Scheme

• Homework - 15%

• Project - 35%

• Midterm Exam - 20%

• Final Exam - 30%

• Class Activity - Bonus 5%

Bonus Points for Class Activity

• Based on class exercises during lecture

• “Small” points earned each week posted on BlackBoard

• Up to 5 “big” bonus points

• Scaled based on the performance of the best student

For example:

1. Alice 40 5 2.Bob 36 4.5 … … …28. Charlie 8 1

Small points Big points

Midterm exam 1

2 hours 40 minutes

in class

design-oriented

open-books, cheat sheet

practice exams available on the web

Last week of October

Tentative date:

Final exam

2 hours 45 minutes

in class

design-oriented

open-books, cheat sheet

practice exams available on the web

Thursday, December 17, 7:30-10:15pm

Date:

17

TextbooksTextbooks

Required TextbookPong P. Chu, RTL Hardware Design Using VHDL,Wiley-Interscience, 2006.

Supplementary Textbook – Basics Refresher

Stephen Brown and Zvonko Vranesic,Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition

Supplementary Textbook – Advanced

Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

21

Technology&

Tools

Technology&

Tools

Block R

AM

s

Block R

AM

s

ConfigurableLogic Blocks (CLB) /Adaptive Logic Modules (ALM)

I/OBlocks

What is an FPGA?

BlockRAMs

23

Modern FPGARAM blocks

Multipliers

Logic blocks

Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Multipliers/DSP units

RAM blocks

Logic resources(CLBs or ALMs)

(#Logic resources, #Multipliers/DSP units, #RAM_blocks)

24ECE 448 – FPGA and ASIC Design with VHDL

Programmableinterconnect

Programmablelogic blocks

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

General structure of an FPGA

25

4-input LUT (Look-Up Table) (used in earlier families of FPGAs)

• Look-Up tables are primary elements for logic implementation

• Each LUT can implement any function of 4 inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

26ECE 448 – FPGA and ASIC Design with VHDL

6-Input LUT of Spartan-6

• designs must be sent for expensive and time consuming fabrication in semiconductor foundry

• bought off the shelf and reconfigured by designers themselves

Two competing implementation approaches

ASICApplication Specific

Integrated Circuit

FPGAField Programmable

Gate Array

• designed all the way from behavioral description to physical layout

• no physical layout design; design ends with a bitstream used to configure a device

FPGAs vs. ASICs

ASICs FPGAs

High performanceOff-the-shelf

Short time to the market

Low development costs

Reconfigurability

Low power

Low cost (but only in high volumes)

29

Major FPGA Vendors

SRAM-based FPGAs• Xilinx, Inc.• Altera Corp.• Lattice Semiconductor• Atmel• Achronix

Flash & antifuse FPGAs• Microsemi SoC Products Group (formerly Actel Corp.)• Quick Logic Corp.

~ 51% of the market

~ 34% of the market~ 85%

Technology Low-cost High-performance

220 nm Virtex180 nm Spartan-II, Spartan-IIE

120/150 nm Virtex-II, Virtex-II Pro

90 nm Spartan-3 Virtex-465 nm Virtex-545 nm Spartan-640 nm Virtex-628 nm Artix-7 Virtex-720 nm Virtex UltraSCALE16 nm Virtex UltraSCALE+

Xilinx FPGA Families

Altera FPGA Devices

Technology Low-cost Mid-range High-performance

130 nm Cyclone Stratix

90 nm Cyclone II Stratix II

65 nm Cyclone III Arria I Stratix III

40 nm Cyclone IV Arria II Stratix IV

28 nm Cyclone V Arria V Stratix V

20 / 14 nm Arria 10 Stratix 10

32

FPGA Family

33

Spartan-6 FPGA Family

FPGA Design process (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;

Specification / Pseudocode

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulationSynthesis

On-paper hardware design (Block diagram & ASM chart)

FPGA Design process (2)

Implementation

Configuration

Timing simulation

On chip testing

Results

Levels of design description

Algorithmic level

Register Transfer Level

Logic (gate) level

Circuit (transistor) level

Physical (layout) level

Level of description most suitable for synthesis

Levels supported by HDL

37

Register Transfer Level (RTL) Design Description

Combinational Logic

Combinational Logic

Registers

George Mason University

Synthesis

39

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

beginA1<=A when (NEG_A='0') else

not A;B1<=B when (NEG_B='0') else

not B;Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;

with (L1 & L0) selectY1<=MUX_0 when "00",

MUX_1 when "01",MUX_2 when "10",MUX_3 when others;

end MLU_DATAFLOW;

VHDL description Circuit netlist

Logic Synthesis

40

Circuit netlist (RTL view)

George Mason University

Implementation

42

Mapping

LUT2

LUT1

FF1

FF2

LUT0

43

PlacingCLB SLICES

FPGA

44

Routing

Programmable Connections

FPGA

45

Configuration

• Once a design is implemented, you must create a file that the FPGA can understand• This file is called a bitstream: a BIT file (.bit extension)

• The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

Simulation Tools

FPGA Synthesis Tools

XST

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

beginA1<=A when (NEG_A='0') else

not A;B1<=B when (NEG_B='0') else

not B;Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;

with (L1 & L0) selectY1<=MUX_0 when "00",

MUX_1 when "01",MUX_2 when "10",MUX_3 when others;

end MLU_DATAFLOW;

VHDL description Circuit netlist

Logic Synthesis

FPGA Implementation

• After synthesis the entire implementation process is performed by FPGA vendor tools

Design Process control from Active-HDL

Xilinx FPGA Tools

Aldec Active-HDL (IDE)

Xilinx XSTorSynopsys Synplify Premier

Xilinx ISE Design Suite

ECE Labs

ISim or ModelSim

Xilinx XSTorSynopsys Synplify Premier

Xilinx ISE Design Suite (IDE)

Aldec Active-HDLDesign Flow

Xilinx ISE Design Flow

simulationsynthesisimplementation

Xilinx FPGA Tools

Aldec Active-HDLStudent Edition (IDE)

Xilinx XST (restricted)

Home

Aldec Active-HDL Design Flow

Xilinx ISE Design Flow

simulationsynthesisimplementation

Xilinx ISE WebPACK(restricted)

ISim

Xilinx XST (restricted)

Xilinx ISE WebPACK (IDE)(restricted)

Altera FPGA Tools

ECE Labs

Mentor Graphics ModelSim-Altera

Altera Quartus II Subscription Edition

AlteraDesign Flow

simulationsynthesis & implementation

Altera FPGA Tools

Home

Mentor Graphics ModelSim-Altera Starter(restricted)

Altera Quartus II Web Edition(restricted)

AlteraDesign Flow

simulationsynthesis & implementation

Lab Access Rules and Behavior Code

Please refer to

ECE Labs website

and in particular to

Access rules & behavior code

58

ATHENa – Automated Tool for Hardware EvaluatioN

Supported in part by the National Institute of Standards & Technology (NIST)

GMU ATHENa Team

Venkata“Vinny”MS CpEstudent

Ekawat“Ice”

PhD CpEstudent

Marcin

PhD ECEstudent

Rajesh

PhD ECEstudent

MichalPhD exchangestudent from

Slovakia

John

MS CpEstudent

ATHENa – Automated Tool for Hardware EvaluatioN

60

Benchmarking open-source tool,written in Perl, aimed at an

AUTOMATED generation of OPTIMIZED results for MULTIPLE hardware platforms

Currently under development at George Mason University.

http://cryptography.gmu.edu/athena

Why Athena?

61

"The Greek goddess Athena was frequently called upon to settle disputes between the gods or various mortals. Athena Goddess of Wisdom was known for her superb logic and intellect. Her decisions were usually well-considered, highly ethical, and seldom motivated by self-interest.”

from "Athena, Greek Goddess of Wisdom and Craftsmanship"

ATHENaServer

FPGA Synthesis and Implementation

Result Summary+ Database Entries

2 3

HDL + scripts + configuration files

1

Database Entries

Download scripts and

configuration files8

Designer

4

HDL + FPGA Tools

User

Databasequery

Ranking of designs

5

6

Basic Dataflow of ATHENa

0

Interfaces+ Testbenches 62

63

synthesizable source files

synthesizable source files

configuration files configuration files

testbenchtestbench

constraint files constraint files

result summary (user-friendly)

result summary (user-friendly)

database entries (machine- friendly)database entries

(machine- friendly)

ATHENa Major Features (1)• synthesis, implementation, and timing analysis in batch mode

• support for devices and tools of multiple FPGA vendors:

• generation of results for multiple families of FPGAs of a given vendor

• automated choice of a best-matching device within a given family

64

ATHENa Major Features (2)• automated verification of designs through simulation in batch

mode

• support for multi-core processing

• automated extraction and tabulation of results

• several optimization strategies aimed at finding– optimum options of tools

– best target clock frequency

– best starting point of placement

OR

65

66

• batch mode of FPGA tools

• ease of extraction and tabulation of results• Text Reports, Excel, CSV (Comma-Separated Values)

• optimized choice of tool options• GMU_optimization_1 strategy

Generation of Results Facilitated by ATHENa

vs.

67

Relative Improvement of Results from Using ATHENa Virtex 5, 256-bit Variants of Hash Functions

Ratios of results obtained using ATHENa suggested optionsvs. default options of FPGA tools

68

Other (Somewhat) Similar Tools

Vivado

Design Space Explorer (DSE)

Boldport Flow

EDAx10 Cloud Platform

69

Distinguishing Features of ATHENa

• Support for multiple tools from multiple vendors

• Optimization strategies aimed at the best possible

performance rather than design closure

• Extraction and presentation of results

• Seamless integration with the ATHENa database of results

70

Benchmarking Goals Facilitated by ATHENa

1. cryptographic algorithms

2. hardware architectures or implementations of the same cryptographic algorithm

3. hardware platforms from the point of view of their suitability for the implementation of a given algorithm,(e.g., choice of an FPGA device or FPGA board)

4. tools and languages in terms of qualityof results they generate (e.g. Verilog vs. VHDL, Synplicity Synplify Premier vs. Xilinx XST, ISE v. 14.7 vs. ISE v. 14.6)

Comparing multiple:

71

ProjectProject

Cryptography Project

related to the research project conducted by Cryptographic Engineering Research Group (CERG) at GMU

supporting NIST (National Institute of Standards and Technology) and the CAESAR Contest Committee in the evaluation of candidates for a new cryptographic standard

Cryptography Project RTL VHDL implementation of an authenticated

cipher based on the

• algorithm specification• reference implementation in C• Hardware API specification.

a different cipher for each student

two students working on the similar ciphers can work closely together, and exchange the source codes

each student graded based on the deliverables for his/her own cipher

Combining Projects from Two Different Courses• ECE 545 & ECE 646• ECE 545 project can be extended into an ECE 646 hardware project by adding additional ciphers, architectures, modes of operation, etc.

• ECE 646 students must write a final report and submit deliverables (one submission per group) ECE 545 submit only deliverables (separate for each member of a group)

• Students forming a two-member group in ECE 646 will receive the same score for the ECE 646 project, but possibly different scores for their respective ECE 545 projects

• ECE 545 & ECE 797/798/799/998• ECE 545 project can be extended into a Scholarly Paper, Research Project, Master’s Thesis, PhD Thesis

Project Organization• Project divided into phases

• Deliverables for each phase submitted using Blackboard at selected checkpoints and evaluated by the instructor and/or TA

• Feedback provided to the students on the best effort basis

• Periodical individual/group meetings devoted to the discussion of each phase deliverables and encountered difficulties

• Final deliverables submitted using Blackboard at the end of the semester

• Final project score based only on the final deliverables

Honor Code Rules

• All students are expected to write and debug their project codes individually or in groups of two

• All homework assignments should be done individually

• Students are encouraged to help and support each other in all problems related to the- operation of the CAD tools- understanding of an investigated algorithm and existing implementations- understanding of the project tasks

ECE 545 Questionnaire