GeNoLator – Generic Network Simulator Final Presentation

GeNoLator – Generic Network GeNoLator – Generic Network Simulator Simulator

Final PresentationFinal Presentation

Students: Gal Ben-Haim, Dan Blechner

Supervisor: Isask'har Walter

Winter 08/09

18/08/2009

GeNolator - QNoC Simulator 2

AgendaAgenda

BackgroundProject GoalsProject OverviewNetwork ArchitectureSW ArchitectureConclusion


Key DefinitionsKey Definitions

QoS – Quality of Service.Network Object – any network

component (router, node, link).Packet – data/control message from

one network object to another.Flit – Packet’s building block, smaller

group of bits.S.L – Service Level.


BackgroundBackground

Today - SOC (System On Chip) use BUS for inner chip communication.

Future - QNoC (QoS Network on Chip) - revolutionary communication protocol for SOC.

QNoC - experimental design, depends heavily on simulation for development and methodologies testing.


Background - Background - QNoC diagramQNoC diagram


The NeedThe Need

Current solution - general network simulator, licensed, expensive, slow, many patches.

Our Solution - open source, fast, dedicated QNoC simulator.


Project GoalsProject Goals

Creating an open source generic simulator for QNoC

High ModularityMaximum flexibility (minimum fixed

parameters)Full DocumentationVerification & EvaluationSimulator will be the base for future

QNoC implementations simulations.


Architectural DesignArchitectural Design

Event-driven. All events implemented using messages Built from QNoC’s basic building blocks:

generator, sink, link and router. System definitions read from external file. Packets randomly generated in generator

with random sink destinations. Message sending is based on credits. Every generation, transmission and reception

of packets is documented in output file.


Network ArchitectureNetwork Architecture

IN OUT

OUT

IN

IN

IN

OUT

OUT

ROUTERROUTER

GENERATORGENERATOR SINKSINK

IN OUT

OUT

IN

IN

IN

OUT

OUT

ROUTERROUTER

SINKSINK

GENERATORGENERATORLINKLINK

LINKLINK

MSG

MSGMSG


Software ArchitectureSoftware Architecture

User input (ini file)

OutputFile

Init (building database)

NetworkSimulation


SW Arch. – Network SimulationSW Arch. – Network Simulation

generatorSink Router Link

Event Queue

EVTtime:xx

EVTtime:xx EVT

time:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

LOG (output

file)


Class DiagramClass DiagramNode

Virtual Init ( );

Virtual handle_msg ( );

Get_id ( );

Get_xy ( );

……

RouterInit ( );

handle_msg ( );

Routing_func ( );

Check_route ( );

……

SinkInit ( );

handle_msg ( );

Receive_msg ( );

LinkInit ( );

handle_msg ( );

Get_latency ( );

Get_bw ( );

……

GeneratorInit ( );

handle_msg ( );

Generate_pkt ( );

Inc_credits ( );

……


Event listInsert_event ( );

Delete_event ( );

static list <pEvent> ev_list;

……

PacketGet_type ( );

Get_sl ( );

List <pFlit> flits_;

……

Class DiagramClass Diagram

EventGet_type ( );

Ger_sndr ( );

……

FlitGet_type ( );

Get_sl ( );

……


Event Queue Event Queue (Event Driven Simulation Engine)(Event Driven Simulation Engine)

control and advance trough simulation.

Store all Events: flit arrived, try to send flit, credits messages and more.

Events ordered by future execution time.

EVTtime:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

EVTtime:xx

EventGet_type ( );

Ger_sndr ( );

……

Event listInsert_event ( );

Delete_event ( );

……


GeneratorGenerator

Generates packets - length, destination, sending time.

statistical function (uniformly distributed) calculates length and send time.

Control (generate packet, send flit) by events.

GeneratorInit ( );

handle_msg ( );

Generate_pkt ( );

Inc_credits ( );

……


SinkSink

Receives flits, assembles it to packets and writes to log.

SinkInit ( );

handle_msg ( );

Receive_msg ( );

FlitGet_type ( );

Get_sl ( );

……

PacketGet_type ( );

Get_sl ( );

……


LinkLink

Connects between any 2 other network objects (generator, sink, router).

Link simulation based on user input of BW, latency, basic time unit (for link busy calculation).

LinkInit ( );

handle_msg ( );

Get_latency ( );

Get_bw ( );

……


RouterRouter

4 inputs, 4 outputs. Routes flits according to XY routing function, S.L priority, and round robin to prevent starvation.

Load balance of link partner is based on credits.

Enables QoS by giving routing priority to high S.L flits above low S.L flits.

RouterInit ( );

handle_msg ( );

Routing_func ( );

Check_route ( );

……


Simulator Modularity Simulator Modularity

Adding functionality to simulated hardware is very easy.

Example1: changing routing algorithm– Replace ‘routing_func’ method in router.cpp

with new implementation Example2: add more S.L:

– Change defined SL_num parameter in global.h Example3: change link modulation:

– Replace ‘get_delay’ method implementation in link.cpp


Coding ProceduresCoding Procedures

VIRTUAL functions in parent classes - enforce rules on future code additions

Using standard STL library Event Driven, no polling Emphasis on faster run time:

– Not using managed code (simple C++)– Simple hierarchies– Using initializer list feature– Return Value Optimization (RVO) – Inlining (more memory, less run rime)


Output log example Output log example Simple Network setup:

Part of the log (all events shown) [time] [node_id] [action performed] 488.943 - node_2: routing FLIT from node:4 to node:5 488.943 - node_5: passing FLIT from node:2 to node:3 488.944 - node_1: sent flt type=2 of pkt 31 to link node_id=4 488.944 - node_3: received flit type=1 488.944 - node_1: increasing credits by 5 488.944 - node_4: passing FLIT from node:1 to node:2 488.945 - node_2: routing FLIT from node:4 to node:5 488.945 - node_5: passing FLIT from node:2 to node:3 492.791 - node_1: generated pkt node_id=1 sl=1 length=4 dst=3 492.791 - node_1: sent flt type=0 of pkt 32 to link node_id=4 492.791 - node_4: passing FLIT from node:1 to node:2 498.943 - node_3: received flit type=1

ROUTERROUTERGENERATORGENERATOR

SINKSINK

14

2

53


Work LeftWork Left

Testing & verificationSeparating log messages to layers

by importanceWriting project book


ConclusionsConclusions

The most complicated module is the router – should be built at the beginning.

Starting from a simple simulator helps to better understand the system.

Writing your own simulator allows for fast/easy feature addition and maintains structural hierarchy.


Points For Future ExpansionPoints For Future Expansion

Generator - Add different statistic generation models

Router – Support more S.L, add different routing function, links load balancing.

Multithreading ?Log – interactive display to support

our logging layers


Gratitude'sGratitude's

Thanks to Zigi for helping and mentoring us through the different stages of the project.

Thanks to SW lab for the facilities.Thanks to Ilana.

Project is based on the article: “QNoC: QoS architecture and design process for Network on Chip” by Evgeny Bolotin, Israel Cidon, Ran Ginosar and Avinoam Kolodny.

Diagrams are borrowed from QNoC2003 article link to article: http://webee.technion.ac.il/matrics/papers/QNoC-Dec2003.pdf


Backup1 – Router ArchitectureBackup1 – Router Architecture


Backup2 – Router Data FlowBackup2 – Router Data Flow

Documents

GeNoLator – Generic Network Simulator Final Presentation