Logic Gate Delay Modeling -1Bishnu Prasad DasResearch Scholar CEDT, IISc, Bangalorebpdas@cedt.iisc.ernet.in

OUTLINEMotivationDelay Model HistoryDelay DefinitionTypes of Models-RC delay Models-Logical EffortLimitation of Logical EffortSummary

Motivation

Why Model is required?For fast simulationSolving differential equation is difficultFor creating optimal designReal design will be always more costly and time consuming.So model is used to simulate the system before actual implementation.

Types of ModelsPhysical ModelsBased on Physical phenomena of deviceEmpirical ModelsBased on curve fitting ( i.e. Quadratic,Cubic etc.)No physical significance.Table ModelsStoring the data in a Lookup TableDo interpolation between stored data

Delay Model HistoryCourtesy : Synopsys

Delay Definitionstpdr: rising propagation delayFrom input to rising output crossing VDD/2tpdf: falling propagation delayFrom input to falling output crossing VDD/2tpd: average propagation delaytpd = (tpdr + tpdf)/2tr: rise slewFrom output crossing 0.2 VDD to 0.8 VDDtf: fall slewFrom output crossing 0.8 VDD to 0.2 VDD

Delay Definitionstcdr: rising contamination delayFrom input to rising output crossing VDD/2tcdf: falling contamination delayFrom input to falling output crossing VDD/2tcd: average contamination delaytpd = (tcdr + tcdf)/2

Delay Definitionstpdr: rising propagation delayFrom input to rising output crossing VDD/2tpdf: falling propagation delayFrom input to falling output crossing VDD/2tpd: average propagation delaytpd = (tpdr + tpdf)/2tr: rise timeFrom output crossing 0.2 VDD to 0.8 VDDtf: fall timeFrom output crossing 0.8 VDD to 0.2 VDD

Delay Definitionstcdr: rising contamination delayFrom input to rising output crossing VDD/2tcdf: falling contamination delayFrom input to falling output crossing VDD/2tcd: average contamination delaytpd = (tcdr + tcdf)/2

RC Delay ModelsUse equivalent circuits for MOS transistorsIdeal switch + capacitance and ON resistanceUnit nMOS has resistance R, capacitance CUnit pMOS has resistance 2R, capacitance CCapacitance proportional to widthResistance inversely proportional to width

Example: 3-input NANDSketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

Example: 3-input NANDSketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

Example: 3-input NANDSketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

3-input NAND CapsAnnotate the 3-input NAND gate with gate and diffusion capacitance.

3-input NAND CapsAnnotate the 3-input NAND gate with gate and diffusion capacitance.

3-input NAND CapsAnnotate the 3-input NAND gate with gate and diffusion capacitance.

Elmore DelayON transistors look like resistorsPullup or pulldown network modeled as RC ladderElmore delay of RC ladder

Example: 2-input NANDEstimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

Example: 2-input NANDEstimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

Example: 2-input NANDEstimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Example: 2-input NANDEstimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Example: 2-input NANDEstimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Example: 2-input NANDEstimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Delay ComponentsDelay has two partsParasitic delay6 or 7 RCIndependent of load Effort delay4h RCProportional to load capacitance

Contamination DelayBest-case (contamination) delay can be substantially less than propagation delay.Ex: If both inputs fall simultaneously

Layout ComparisonWhich layout is better?

Delay in a Logic GateExpress delays in process-independent unit

Delay has two components

f is due to external loadingp is due to self loading = 3RC = FO1 delay without parasitic delay

Delay in a Logic GateExpress delays in process-independent unit

Delay has two components

Effort delay f = gh (a.k.a. stage effort)Again has two components = 3RC = FO1 delay without parasitic delay

Delay in a Logic GateExpress delays in process-independent unit

Delay has two components

Effort delay f = gh (a.k.a. stage effort)Again has two componentsg: logical effortMeasures relative ability of gate to deliver currentg 1 for inverter = 3RC = FO1 delay without parasitic delay

Delay in a Logic GateExpress delays in process-independent unit

Delay has two components

Effort delay f = gh (a.k.a. stage effort)Again has two componentsh: electrical effort = Cout / CinRatio of output to input capacitanceSometimes called fanout = 3RC = FO1 delay without parasitic delay

Delay in a Logic GateExpress delays in process-independent unit

Delay has two components

Parasitic delay pRepresents delay of gate driving no loadSet by internal parasitic capacitance = 3RC = FO1 delay without parasitic delay

Effort Delay Logical Effort g = Cingate/Cin_unit_inv

Electrical Effort h= Cout / Cingate

f = g*h = (Cingate/Cin_unit_inv)*(Cout / Cingate) = (Cout / Cin_unit_inv)

(Dactual)ext = g*h * = (Cout / Cin_unit_inv)*3*R*C = (Cout / Cin_unit_inv)*R*Cin_unit_inv = Cout*R

Computing Logical EffortDEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.Measure from delay vs. fanout plotsOr estimate by counting transistor widths

Catalog of GatesLogical effort of common gates

Gate typeNumber of inputs1234nInverter1NAND4/35/36/3(n+2)/3NOR5/37/39/3(2n+1)/3Tristate / mux22222XOR, XNOR4, 46, 12, 68, 16, 16, 8

Catalog of GatesParasitic delay of common gatesIn multiples of pinv (1)

Gate typeNumber of inputs1234nInverter1NAND234nNOR234nTristate / mux24682nXOR, XNOR468

Delay Plotsd = f + p = gh + p

Delay Plotsd = f + p = gh + p

What about NOR2?

Example: Ring OscillatorEstimate the frequency of an N-stage ring oscillator

Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay:d =Frequency:fosc =

Example: Ring OscillatorEstimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay:d = 2Frequency:fosc = 1/(2*N*d) = 1/4N

Example: FO4 InverterEstimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = Electrical Effort:h =Parasitic Delay: p =Stage Delay:d =

Example: FO4 InverterEstimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay:d = 5The FO4 delay is about 200 ps in 0.6 mm process 60 ps in a 180 nm process f/3 ns in an f mm process

Multistage Logic Networks

Limits of Logical EffortChicken and egg problemNeed path to compute GBut dont know number of stages without GSimplistic delay modelNeglects input rise time effectsInterconnectIteration required in designs with wireMaximum speed onlyNot minimum area/power for constrained delay

SummaryRC Delay ModelDelay measurement using Logical Effort MethodGate sizing using Logical Effort for minimum delayLimitations of Logical Effort

ReferenceN. H. E. Weste and D. Harris, CMOS VLSI Design, A circuits and Systems Perspective 3rd edition Pearson Addison WesleyRabaey, Chandrakasan and Nikolic, Digital Integrated Circuits, a Design Perspective, Pearson Education