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GATE-LEVEL MODELING. (Source: a Verilog HDL Primer by J. Bhasker). Different Levels of Abstraction. Architectural / Algorithmic Level Implement a design algorithm in high-level language constructs. Register Transfer Level - PowerPoint PPT Presentation
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GATE-LEVEL MODELING(Source: a Verilog HDL Primer by J. Bhasker)
DIFFERENT LEVELS OF ABSTRACTION
Architectural / Algorithmic Level Implement a design algorithm in
high-level language constructs. Register Transfer Level
Describes the flow of databetween registers and how a design processthese data.
System
Algorithm
Architecture
Register Transfer Level
Gate Level
Transistor Level
DIFFERENT LEVELS OF ABSTRACTION
Gate LevelDescribe the logic gates and the
interconnections between them. Switch (Transistor) Level
Describe the transistors andthe interconnectionsbetween them.
System
Algorithm
Architecture
Register Transfer Level
Gate Level
Transistor Level
GATE-LEVEL MODELING
The gate-level modeling describes the available built-in primitive gates and how these can be used to describe hardware.
MULTIPLE-INPUT GATES
and, nand, or, nor. xor, xnor
These logic gates have only one output and one or more inputs.
MULTIPLE-INPUT GATES
Syntax:multiple_input_gate_type[instance_name]
(OutputA,Input1,Input2,….,Input1);
Note: A value z at an input is handled like an x and the output can never be a z.
Multiple-input gateOutput A
Input1
Input2
Input3
MULTIPLE-INPUT GATES
nand 0 1 x z
0 1 1 1 1
1 1 0 x x
x 1 x x x
z 1 x x x
and 0 1 x z
0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
or 0 1 x z
0 0 1 x x
1 1 1 1 1
x x 1 x x
z x 1 x x
xnor 0 1 x z
0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
nor 0 1 x z
0 1 0 x x
1 0 0 0 0
x x 0 x x
z x 0 x x
xor 0 1 x z
0 0 1 x x
1 1 0 x x
x x x x x
z x x x x
EXAMPLES:
and A1 (Out1, In1, In2) ;and RBX (Sty, Rib, Bro, Qit, Fix) ;xor (Bar, Bud[0], Bud[1], Bud[2] ) , (Car, Cut[0], Cut[1] ) , (Sar, Sut[2], Sut[1], Sut[0], Sut[3] ) ;
MULTIPLE-OUTPUT GATES:
buf, not
These gates have only one input and one or more outputs
MULTIPLE-OUTPUT GATES:
Syntax:multiple_output_gate_type[instance_name]
(Out1,Out2,…..,OutN, InputA);
InputA
Out1
Out2
OutN
Out1
Out2
OutN
InputA
EXAMPLES:BUF B1 ( FAN[0], FAN[1], FAN[2], FAN[3], CLK ) ;NOT N1 (PHA, PHB, READY) ;
buf 0 1 x z
output 0 1 x x
buf 0 1 x z
output 0 1 x x
TRISTATE GATES:
bufif0 , bufif1, notif0, notif1
These gates model three state drivers and have one output, one data input and one control input.
Note: For a bufif0 gate, the output is z if control is 1,
else data is transferred to output. For a bufif1 gate, the output is z if control is 0. For a notif0 gate, the output is z if control is 1,
else output is the invert of the input data value.
For a notif1 gate, the output is z if control is 0.
TRISTATE GATES:
Syntax:tristate_gate [instance_name] (OutA, InputB,
ControlC); InputAOutputAControlCnotif1
InputA OutputA
ControlC
notif1
InputA OutputA
ControlC
notif0
InputA OutputA
ControlC
bufif1
InputA OutputA
ControlC
bufif0
EXAMPLES:BUFIF BF1 ( DBUS, MEMDATA, STROBE ) ;NOTIF0 NT2 (ADDR, ABUS, PROBE) ;
Bufif0 Control
0 1 x z
Data 0 0 z 0/z 0/z
1 1 z 1/z 1/z
x x z x x
z x z x x
Bufif1 Control
0 1 x z
Data 0 z 0 0/z 0/z
1 z 1 1/z 1/z
x z x x x
z z x x x
Notif0 Control
0 1 x z
Data 0 1 z 1/z 1/z
1 0 z 0/z 0/z
x x z x x
z x z x x
Notif1 Control
0 1 x z
Data 0 z 1 1/z 1/z
1 z 0 0/z 0/z
x z x x x
z z x x x
PULL GATES:
pullup , pulldown
These gates have only one output with no inputs.
Note: A pullup gate places a 1 on its output. A pulldown gate places a 0 on its output.
Syntax:
pull_gate_type[instance_name](OutA);
Examples:Pullup PUP(Pwr) ;
MOS SWITCHES:cmos, pmos, nmos, rcmos, rpmos, rnmos
These gates model unidirectional switches, that is, data flows from input to output and the data flow can be turned off by appropriately setting the control input(s).
Note:The pmos( p-type MOS transistor), nmos(n-type MOS transistor), rnmos( r stands for resistive) and rpmos switches have one output, one input, and one control input. If control is 0 for nmos and rnmos switches and 1 for pmos and rpmos switches, the switch is turned off, that is, output has a value z; if control is 1, data at input passes to output.
MOS SWITCHES:
Syntax:gate_type[instance_name](OutputA, InputB,
ControlC);
InputB Output A
ControlC
nmos switch nmos switch
ControlC
OutputAInputB
MOS SWITCHES:
pmosrpmos
Control
0 1 x z
Data 0 0 z 0/z 0/z
1 1 z 1/z 1/z
x x z x x
z z z x x
nmosrnmos
Control
0 1 x z
Data 0 z 0 0/z 0/z
1 z 1 1/z 1/z
x z x x x
z z z x x
EXAMPLES:PMOS P1( BIGBUS, SMALLBUS, GATECONTROL) ;RNMOS RN1(CONTROLBIT,READYBIT,HOLD) ;
Pcontrol
OutputA
Ncontrol
InputB
( r ) cmos switch
BIDIRECTIONAL SWITCHES:
tran, rtran, tranif0, rtranif0, tranif1, rtranif1 These switches are bidirectional, that is, data
flows both ways and there is no delay when data propagates through the switches. The last four switches can be turned off by setting a control signal appropriately. The tran and rtran switches cannot be turned off. If control is 1 for tranif0 and rtranif0, and 0 for tranif1 and rtranif1, the bidirectional data flow is disabled.
Syntax : gate_type[instance_name](SignalA, SignalB, SignalC);
GATE DELAYS
The signal propagation delay from any gate input to the gate output can be specified using a gate delay using the syntax:
gate_type [delay] [ instance_name] ( terminal list );
Example: and #3 g (a, b, c);
WHEN NO GATE DELAY IS SPECIFIED, THE DEFAULT DELAY IS ZERO. A gate delay can be comprised of up to
three values: Rise delay Fall delay Turn-off delay
EXAMPLE: 1-BIT MULTIPLEXER
in1
in2
out0
1
sel sel in1 in2 out
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
to “select” output
GATE LEVEL DESCRIPTION
Gate Level: you see only netlist (gates and wires) in the code.
a1
a2
in1
in2
sel
outo1
iv_sel a1_o
a2_on1
iv_sel
GATE-LEVEL MODELING
StepsDevelop the Boolean function of outputDraw the circuit with logic gates/primitivesConnect gates/primitives with net (usually
wire) HDL: Hardware Description Language
Figure out architecture first, then write code.
TEST METHODOLOGY
Systematically verify the functionality of a model.
Procedure of simulationDetect syntax violations in source code Simulate behavior Monitor results
TEST METHODOLOGY
TestbenchHardware Design
(Design Under Test)
Stimulus
Response
VERILOG SIMULATORVERILOG SIMULATOR
CASE STUDY: FULL ADDERCASE STUDY: FULL ADDER
A B
CiCo
S
Full Adder
Ci A B SCo
0 0 0 00
0 0 1 10
0 1 0 10
0 1 1 01
1 0 0 10
1 0 1 01
1 1 0 01
1 1 1 11
30
CASE STUDY: FULL ADDERCASE STUDY: FULL ADDER
31
Co = AB + BCi + CiA
ABBCi
Ci
A
Co
CASE STUDY: FULL ADDERCASE STUDY: FULL ADDER
sum = a b ci
32
abc
sum
ab
c sum
CASE STUDY: FULL ADDERCASE STUDY: FULL ADDER
Full Adder ConnectionInstance ins_c
from FA_coInstance ins_s
from FA_sum
33
abc
sum
abbcca
co
carry out connection
sum connection
full adder
TESTBENCH FOR FULL TESTBENCH FOR FULL ADDERADDER
module TestBench;reg a,b,ci;wire sum,cout;initialbegin$display(“a b ci sum cout");a = 1'b0; b = 1'b0;ci = 1'b0; #8 $finish;endalways #4 b = ~b;always #2 a = ~a;always #1 ci = ~ci;FA_sum U1(sum,a,b,ci,cout);initial$monitor("%b %b %b %b %b“,
a, b, ci, sum, cout);endmodule