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From Technologies to Market
Intégration 3D pour les
datacenters haute performance
IRT Nanoelec– 05/04/17
Emilie Jolivet
Eric Mounier
© 2015© 2016Chanel fashion runway at Paris’ Grand Palais – October 2016
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DATA TRAFFIC & HYPERSCALE DATACENTER
Data trafficexpected to triple between 2015 and 2020!
©2015 | www.yole.fr | Name of the event
Hyperscale datacenter Microsoft, San Antonio TX
5th biggest hyperscale datacenter
477 000 sq ft ~ 44 314 m² ~ 4 hectares
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WHERE ARE THE TECHNICAL CHALLENGES?
• For the next generation of data centers, three main technical aspects are targeted:
• Storage capacity
• Power consumption
• Data flow
• On the storage side, higher density capacity and higher speed are sought
• Related to power consumption, more efficient systems and less loss sources are needed
• For data flow, faster data transmission and less-consuming solutions are required
Equipment manufacturers are constantly
pursuing technical
breakthroughs
Data centerStorage
capacity
Power
consumption Data flow
Technical
breakthroughs
IT equipmentPower
equipment
Cooling
systems
©2016 | www.yole.fr | Silicon Photonics for Data Centers and Other Applications 2016 report
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INTRA-DATA CENTER CONNECTIVITY WILL HAVE THE HIGHEST CAGR (SOURCE: INTEL)
In 2016, 40% of data trafficwas withindatacenters. In 2020, it will be80%
©2016 | www.yole.fr | Silicon Photonics for Data Centers and Other Applications 2016 report
2016 2018 2020
Data center 40G+ TAM
Between DC
Across DC
Accross row
In rack
$1.2B
$2.1B
$5.1B
The graph below shows that the largest market value growth for 40G+ data rate in data centers will be
IN the data center (either across the data center, across the rows, or in the racks)
Across row
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3DIC MARKET DRIVERS
3DIC drivers unchanged!!
“More than Moore”
Heterogeneous integration
Co-integration of
RF+logic+memory +
sensors in a reduced space
Density
Achieving the highest
capacity / volume ratio
Form factor-
driven
Performance-
driven
3D ICOptimum Market Access
Conditions
Wide IO
memory
CIS
DRAM
RF-SiP
Electrical performance
Interconnect speed, bandwidth and
reduced power consumption
3D vs. “More Moore”
Can 3D be cheaper
than going to the next
lithography node?
Flash
Cost-driven
PartitioningSensors
CPU
GPU
Power.
Analog.
FPGA
©2016 | www.yole.fr | 3DASIP 2016
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3D IN A DATA CENTRE
©2016 | www.yole.fr | Silicon Photonics for Data Centers and Other Applications 2016 report
Top-of-rack
Interconnection (spine) switch
Server cabinets
Access (leaf)
switches
Server connections are typically copperSwitch-to-switch connections are
optical fibers
• Copper is still used for top-of-rack server switches because distance is short. When distance increases, optical links are used since they do not suffer frombandwidth limitation. Most bandwidth is INSIDE DC.
• For 1 “web search” up to 1,000+ servers can be addressed
• One data center: 50k - 200k servers
Between DCs (10 - 500km): 100Gb
Across DCs (100m-2km): 25-40Gb
In-rack (3m):
100Gb
Across row (10 -
100m): 40 - 100Gb
Long-reach optics: 25Gb
25Gb
Core switches
7©2016 | www.yole.fr | 3D TSV & 2.5D Interconnect - Business Update Report 2016
ADVANCED PACKAGING PLATFORMS
AREA OF
INTEREST FOR
TODAY
PRESENTATION
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3D TECHNOLOGIES DEFINITION
3D technology: stacking layers on layers
• It can be Memory on Memory or Logic on Memory
• Large die partitioned
2.5D technology: assembly of chips on interposer
• Several types of chips can be assembled on an interposer (GPU,CPU, memory, NPU,….)
• Interposer can be made out silicon, glass or laminate. In thecase of laminate, we can sometimes find the term 2.1Dtechnology.
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COMPONENTS AVAILABLE ON A 2.5D INTERPOSER
Logic and Memory are the main components integrated on an interposer
Field Programmable
Gate ArraysMemory Cube
Central Process
Unit
Graphic
Process Unit
SERializer-DESerializerNetwork
Process Unit
System On Chip
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3D STACKED MEMORY CUBE
Memory type available
3DS HBM
HMC DiRAM
Source: SK Hynix
11©2016 | www.yole.fr | Status of the CMOS image sensor industry
3DS MEMORY
Three-dimensional stacked memory
• 3DS is a TSV-based DDR4 DRAM, validated by JEDEC standard
• The product is available in 64 and 128 GB, manufactured bySamsung and SK Hynix only
3DS memory is sold as
stand-aloneproductaimed at server market
Courtesy of SK Hynix
Top slave
Slave 2
Slave 1
Master die
PCB
Courtesy of System Plus Consulting, 3DS 64 Gbits from Samsung
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ON-BOARD OPTICAL MODULES• Mid-board and panel optics will integrate with the rack to minimize the distance between FPGA and optical modules, for best-possible
signal
• Broadcom and Samtec are proposing optical modules:
• To minimize the distance between the FPGA and the optical module, and to reduce the power and build-of-materials of the entire chip-to-module link,Altera Corporation and Avago Technologies Inc. (Broadcom) have jointly developed a solution that combines the FPGA and optical transmitter andreceiver modules into a single integrated package that can replace multiple external card-edge optical transceivers
• Samtec has developed Firefly mid-board optics systems up to 28Gbps
©2016 | www.yole.fr | Silicon Photonics for Data Centers and Other Applications 2016 report
MicroPOD optical modules mount to the FPGA
package
FireFly from Samtec.
source: Samtec
SiPh mid-board optics (> 2020)
SiPh pluggable transceivers (> 2016)
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FORECAST FOR HIGH PERFORMANCE 3D-BASED PRODUCTS
By revenue ($M)
Total revenue of high
performanceTSV based products to
reach ~$1.1B by 2021 at a
CAGR of 46%
• The high performance TSV application market by revenue is expected to reach ~$1.1B by 2021
• This chart represents revenues made out of 3D stacked memory and interposer
0
200
400
600
800
1000
1200
2015 2016 2017 2018 2019 2020 2021
Reven
ues
(M$)
Year
2015-2020 Revenue forecast for 3D TSV high performance
products
(in $M )
Yole Développement October 2016
* stacked memory + silicon interposer revenues
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CONCLUSIONS
New commercial products based on 3D were recently launched and will be launched to consolidate the technology portfoliofor datacenters and HPC
3DS and HBM memories now available in volume, a supply chain of stacked memory and interposer is built. Samsung recentlyannounced its interposer platform.
High-performance products based on TSV technology will generate revenues of 1 billion $ by 2021
Bluechip companies orientate their strategy towards datacenters (Intel, Nvidia,…)
Silicon photonics is also moving progressively towards interposer solution
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Biography & contact
CONTACT & SOURCES
Emilie JOLIVET – [email protected]
Eric MOUNIER – [email protected]
Emilie Jolivet is a Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at YoleDéveloppement the "More than Moore" market research and strategy consulting company. She holds a master’s degree Applied Physics specialized in Microelectronics from INSA Toulouse. After an internship in failure analysis in Freescale, she took the position of R&D engineer for 7 years in photovoltaic business and co-authored several scientific articles. Strong for this experience, she graduated from a master in Business Administration at IAE Lyon and then joined EV Group as a business development manager in 3D & Advanced Packaging before joining Yole Développement in 2016.
©2016 | www.yole.fr | Name of the event
Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. He previously worked at CEA LETI R&D lab in Grenoble, France in marketing dept. Since 1998 he is a cofounder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Eric Mounier is in charge of market analysis for MEMS & Sensors, visible and IR imagers (CIS,microbolometers), semiconductors, printed electronics and photonics (e.g. Silicon photonics). He has contributed to more than200 marketing & technological analysis and 100 reports. Eric is also an expert at the OMNT ("Observatoire des Micro & Nanotechnologies") for Optics.
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DATA SOURCES
Related reports
• Information in this presentation is extracted from the following reports:
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MEMS &
Sensors
LED
Compound
Semi.
Imaging Photonics
MedTech
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Advanced Packaging
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Management
Power
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