From boxes to synapstors - leti.congres-scientifique.comleti.congres-scientifique.com/workshopmemories/documents/11-LETI... · Computing with (resistive)memories From boxes to synapstors

Computing with (resistive)memories From boxes to synapstors Christian Gamrat Embedded Computing Laboratory CEA LIST, Saclay, France [email protected]

© CEA. All rights reserved

Computing with memories | Memory workshop, 29 June 2011, Grenoble

Outline

Introduction, Computing with memory The legacy « box » memory style

The LUT and Switch styles: Reconfigurable logic

Neuromorphic approach the old way

Neuromorphic the STDP way

Learning with STDP and memristive devices

Intriducing the Synapstor

Potential applications and demonstrators

Perspective, memory based computing



Computing basics: Von Neumann Architecture

Simply put the VN architecture is a practical implementation of the conceptual Turing machine

Together with the idea of stored program, it allows to mechanize the algorithmic execution of a program

In VN Architecture, Memory is « just » a storage element

Memory Read / Write paths

VN bootleneck

Logic and memory

elements are separated

Why did they

name this

after me?



The Box Memory style

• Data is computed in some places outside of the box

• Data is stored in a box as a result of a write operation

• Data is used externally through a read operation

• Storing a value in a box does not imply any semantics other than that given by the box label

Labelled Box

Read / Write

‘M’

2 ways bootleneck

Out of the box computation &

exploitation of the data



Computing with memory: look-up table

• The look-up table structure (LUT) is one basic building block to design Field Programmable Gate Arrays

• In a LUT the content of the memory directly implements the truth table of a boolean function

0

0 0

1 0

01 0

1 1 1

0

A B S

S=A.B (ET)

0

0

0

1

SA

B

Adresse (AB) = x

Contenumémoire

f()

Sortie = f( x)



Reconfigurable Switch Memory Style

• Data is computed in some places outside of the box

• Data is stored in a box as a result of a write operation

• Data is used locally to turn a switch on & off

• Storing a value in a box imply a simple semantics given by the circuit location of the attached switch element

M

‘M’

Write

1 way bootleneck

Out of the box computation of the data

A B



logiccell

Switch Matrix

Input / Output

Local Interconnects

Global Interconnects

Logic Array Architecture: LUT and Switches • A Regular logic matrix made of

Programmable logic blocks based on Look-up table structures

Routing done with Reconfigurable Switch elements

Lots of long and short wiring

• Field Programmable Gate Array



Field Programmable Nanowire Interconnects with TiO2 Memory cells

Proposed by HP-Labs’ s Snider & Williams(1) with inspiration by Likharev’s CMOL(2)

Experimental demonstration(3)

CMOS Logic gates

Routing with Ti02 memristors

Co-integration above CMOS

Memristors

1. G.S. Snider and R.S. Williams, “Nano/CMOS architectures

using a field-programmable nanowire interconnect,”

Nanotechnology, vol. 18, 2007.

2. K.K. Likharev, “CMOL: A New Concept for Nanoelectronics,”

12th International Symposium on Nanostructures: Physics

and Technology, St Petersburg, Russia: Ioffe Institute, 2004.

3. Xia, Q. et al. Memristor−CMOS Hybrid Integrated Circuits for

Reconfigurable Logic. Nano Letters 9, 3640-3645 (2009).



ni

i

ii xw1

signy

0 1

1

0

X1

X2

)2211( WXWXy

W1

W2

Wn

x1

x2

xn

y

-θ Threshold Weights

1

0

OR

AND

Good Old Neuromorphic Circuit: the perceptron



Experimental circuit with logic function learning capabilities

-3 -2 -1 0 1 2 3

10-9

10-8

10-7

10-6

I D(A

)

VGS

(V)

X1+

X2+ X3+ Bias+

VG

X1- X2- X3-

Bias-

Function outputW21

(a) (b)

(a)8 OG-CNTFETs sharing the same

gate and output electrodes.

(b)Id(Vgs) transfer characteristics

showing large variability in the ON-

state but still leading to efficient

learning of functions.

Efficient learning even with

large device variability

0 0 0 1

0 0 1 0

Epoch 1 2 3 4 5 6 7 8

Before

After

Inpu

ts A

B

EXPECTED OUTPUT

MEASUREDOUTPUT

LEARNING COMPLETED

(a)Exemple of Supervised learning

of a 2-input boolean function

Nanotube devices based crossbar architecture: toward

neuromorphic computing, W. Zhao et al. Nanotechnology

21, 175202 (2010).

Coll. Jacques-Olivier Klein group, IEF, Paris

XI University, Orsay, France

Vincent Derycke group, CEA Saclay, France



Memristive Devices Principle

Important steps First theoretical study1

First link between a physical device and the theory2

STDP learning (next slide)

1 L. Chua and S. Kang, Proceedings of the IEEE, 1976 2 D. Strukov et al., Nature, 2008

Metal (Mx+1 layer)

Metal (Mx layer)

Insulator • Oxide • Solid electrolytic • Organic material

Electrodes MIM

V

V

dR dt

R

Vth

-Vth’

Nonlinear characteristic required for STDP!

iixRv ).,( ),( ixfdt

dx

Crossbar (University of Michigan)

11



Memristive device and STDP: paving the way to unsupervised learning First Proposed by Snider(1)

Vpost Vpre

tpre

t

Vpre

tpost

t Vpost

t

Vpre

-Vpost

R decreases

-Vth’

tpre

t

tpost

t

t

R increases

Vth

tpre < tpost tpre > tpost

Simulation with AMS Designer (Cadence) Functional models in VHDL-AMS

Neurons

Synaptic weight update through STDP

Pre-synaptic spike

Post-synaptic spike (feedback)

1. G. Snider, Nanoscale Architectures, 2008

2. B. Linares-Barranco and T. Serrano-Gotarredona,

Nature Precedings, 2009



U. Michigan, Lu group demonstration1

Recent demonstration on PC memory by Wong group, Stanford

STDP experimental demonstration

1 Jo, S.H. et al. Nanoscale Memristor Device as Synapse in Neuromorphic Systems. Nano Letters (2010).



Influence of pulse shape on STDP

Illustration of influence

of action potential shape

on the resulting STDP

resistance update

function x(DT).X1 is

spike waveform and X2

is resulting STDP

learning function, where

X goes from (A-H

Bernabe Linares Barranco group, IMSE,

CSIS, Sevilla, Spain

(a)Triangle-shaped pulse used to

characterize STDP.

(b)STDP function obtained on

NOMFET with a triangle shaped

function (red dots are

experimental measurements, blue

dots are the model calculations)

Dominique Vuillaume group, IEMN, CNRS, Lille, France



Hybrid NOMFET / CMOS STDP characterization

(a) (b)

(c)

(a) Photography of the

NOMFETs in a TO case (arrow)

plugged on the electronic-board.

(b) Typical spike signals

applied at the input (pre-

synaptic spikes) and at the

output (pots-synaptic spike)

of the NOMFET.

(c) STDP learning function

acquired with the electronic-

board for two NOMFETs (blue

and red dots) measured

simultaneously.

Although the memory devices parameters are very variables among devices The STDP dynamic characteristics are fairly well matched

C. Gamrat group, CEA, LIST, Saclay, France

D. Vuillaume group, IEMN, CNRS, Lille, France



Association is

made Food

Bell

Salivation

A basic simple application: Associative Memory

1 Pershin, Y.V. & Di Ventra, M. Experimental demonstration of associative memory with

memristive neural networks. Arxiv 0905.2935 (2009).

Experimental setup for a Pavlovian

associative memory based on memristive

devices as proposed by Di Ventra et col.1



Synapstor

Introducing the Synapstor

Modelling the behavior of a biological synapse from an EE perspective

A memory device that stores a transmittance value

Integrating a self-updating mechanism capable of using local information to update its transmittance

The synapstor gathers a memory effect + a self-updating behaviour into one single device

It is an adaptive memory that stores and continuously updates contextual information

B=W*A

W+dW (update)

W (storage)

dW = f(A, B)

A

B

W = Stored quantity (memory)

Self-updating scheme dW



A Real life Vision Application using memristive devices as synapstors Architecture Simulation

~ 2,000,000 synapstors

Fully connected Layer planes

Unsupervised learning (STDP)

Competitive learning with lateral inhibition

Results 98% cars detection rate

High noise tolerance: same detection rate with 50% added noise

Very High variability immunity: good performances with 20% synaptic variability (> 95% on learned traffic lanes)

1st lane 2nd lane 3rd lane 4th lane 5th lane 6th lane

O. Bichler, D. Querlioz, S. J. Thorpe, J.-P. Bourgoin and C. Gamrat,

“Unsupervised Features Extraction from Asynchronous Silicon

Retina through Spike-Timing-Dependent Plasticity”, International

Joint Conference on Neural Networks (IJCNN) 2011 (submitted)

Second layer weight reconstruction

Second layer activity



Real Life Application of STDP with memristive synapstors

128

128 AER Sensor

16,384 spiking pixels

1st layer

2nd layer

Lateral

inhibition

Lateral

inhibition

……

…

Elementary patterns

…

Shapes

…

Objects

Two-layers system

~ 2 million devices with STDP

Using the XNET event based

simulator

Hierarchical Architecture

Proposal



Other Applications : Random pattern matching Unsupervised pattern matching in random data

From S. Thorpe1

1 Masquelier T, Guyonneau R, Thorpe SJ. 2008. « Spike timing

dependent plasticity finds the start of repeating patterns in continuous

spike trains”. PLoS ONE 3:e1377 2O. Bichler, “Learning with Memristive Devices”, 2010 Workshop on

Innovative Memory Technologies, Grenoble, June 21, 2010

Hierarchical architecture based

on memristive devices for

unsupervised pattern matching in

image sensors. From O. Bichler1

STDP



SUMMARY

There are ways to computing with memory beyond Boxes

There are even ways beyond LUT and Switch styles

STDP shows that coding schemes beyond booleans (pulse based) shall be explored and developed

The Synapstor is an adaptive contextual memory It models the « synaptic-like » function with an EE perspective

Synapstor + STDP: a paradigm shift in memory usage departing from traditional « box-type » memories

Resistive and Memristive technologies enable the transition between Logic & Neuromorphic architecture



Thank You all PhD Students: Olivier Bichler, Manan Suri, Christophe Novembre

Post Docs: Yves l’Huillier, Damien Querlioz, Weisheng Zhao, Fabien Allibart

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From boxes to synapstors - leti.congres-scientifique.comleti.congres-scientifique.com/workshopmemories/documents/11-LETI... · Computing with (resistive)memories From boxes to synapstors