Frank Vahid, Univ. of California, Riverside 1/17 Highly-Cited Ideas in System Codesign and Synthesis Frank Vahid Dept. of Computer Science and Engineering

1/17Frank Vahid, Univ. of California, Riverside

Highly-Cited Ideas in System Codesign and Synthesis

Frank VahidDept. of Computer Science and

EngineeringUniv. of California, Riverside, USA

*Also with the Center for Embedded Computer Systems, UC Irvine

http://www.cs.ucr.edu/~vahid

Tony GivargisCenter for Embedded Computer

SystemsUniv. of California, Irvine, USAhttp://www.ics.ucr.edu/~givargis

This research was supported in part by the National Science Foundation (CNS-0614957).


CODES/ISSS in Atlanta

#1 spectator sport in U.S. #2 sport on television in U.S.

2nd to football

American football, that is


Introduction

• CODES/ISSS in 2nd decade– Pause to reflect on high-impact ideas

• Citations are one measure of impact– B references A; A has 3 citations (and 2 refs)

• Total citations are of interest– Especially with rise of "h-index" (Hirsch) in academics

• Person with h-index of 25 has 25 papers cited at least 25 times

• Intra-community citations also of interest– Measure of community building on each other’s work

• Citations are clearly an imperfect measure– E.g., paper with no citations that leads to a company

• May still yield insights

Merged 2003

CODES/ISSS papers

reference

cited

A

B

B references AA is cited by B


Method

• Table of contents from ACM online for CODES, ISSS, and CODES/ISSS proceedings

• Entered titles into Google Scholar– Returns paper, and list of citing

papers– We removed self-citations (10%-

25%)– Result is “non-self-citations”– Done in early 2008 (“snapshot”)

• Inexact process (like all)– Not all papers are known to Google,

title mismatches, authors with same names, journal paper with same name

• Process mostly automated, some manual steps, manual spot checks


Top Four Each Year 1996-2006

• Table appears in paper

• Examined top six overall (no adjustment for year published)...

Year IDTitle All Comm1996 a Bus-Based Communication Synthesis on System-Level 98 13

bC Process Partitioning for Distributed Embedded Systems 78 17

c PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning 54 17d Grammar-based Hardware Synthesis of Data Communication Protocols 45 5

1997 a Architectural Exploration and Optimization of Local Memory in Embedded Systems 40 7b Critical Path Driven Cosynthesis for Heterogeneous Target Architectures 37 3c An Evolutionary Approach to System-Level Synthesis 36 3d Embedded System Synthesis by Timing Constraints Solving 35 3

1998 a TGFF Task Graphs for Free 194 7b Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign 93 3c Software Timing Analysis Using HW/SW Cosimulation and Instruction Set Simulator 56 4

d A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools 49 3

1999 a Real-Time Task Scheduling for a Variable Voltage Processor 64 10b Automatic Architectural Synthesis of VLIW and EPIC Processors 55 9c Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessors 53 1d Compiling Esterel into Sequential Code 45 4

2000 a Compiler Optimization on Instruction Scheduling for Low Power 50 10b Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures 44 3c Low-Power Task Scheduling for Multiple Devices 42 0d Heterogeneous Modeling and Simulation of Embedded Systems in El Greco 40 7

2001 a Designing Domain-Specific Processors 70 5b SystemC: A Modeling Platform Supporting Multiple Design Abstractions 58 0c Embedded UML: a Merger of Real-Time UML and Co-Design 49 7d Hardware / Software Partitioning of Embedded System in OCAPI-xl 45 0

2002 a Scratchpad Memory : A Design Alternative for Cache On-chip Memory in Embedded Systems 108 0b Holistic Scheduling and Analysis of Mixed Time/Event-Triggered Distributed Embedded Systems 54 8c An Adaptive Low-Power Transmission Scheme for On-Chip Networks 52 5d Multi-Objective Design Space Exploration Using Genetic Algorithms 45 5

2003 a Pareto Optimization Based Run-time Task Scheduling for Embedded Systems 29 0b Hardware Support for Real-time Operating Systems 28 1c Accurate Estimation of Cache-Related Preemption Delay 24 2d A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks 19 1

2004 a Dynamic Overlay of Scratchpad Memory for Energy Minimization 35 5b Design and Programming of Embedded Multiprocessors: An Interface-Centric Approach 20 1c Transaction Level Modeling: Flows and Use Models 20 1

d Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management 18 1

2005 a A unified approach to constrained mapping and routing on network-on-chip architectures 26 3b Key research problems in NoC design: a holistic perspective 22 5c An automated exploration framework for FPGA-based soft multiprocessor systems 21 0d An integer linear programming approach for identifying instruction-set extensions 12 1

2006 a Multi-processor system design with ESPAM 10 0b A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control 7 0c Challenges in exploitation of loop parallelism in embedded applications 6 0d Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure 6 0


Top 6 Cited Overall Since 1996

M. Arnold , H. Corporaal. Designing domain-specific processors. Int. Symp. on Hardware/Software Co-Design (CODES), 2001, pp. 61-66.

• 70 citations• Semi-automated method for detection

and exploitation of application domain specific instruction set extensions for embedded (VLIW) processors– 1. detects frequent operation patterns

– 2. patterns are grouped & implemented in a number of Special Function Units.

– 3. incorporates the custom operations into the code generation process.



• 78 citations• Technique for partitioning processes

in distributed embedded systems. • Minimizes both context switch and

communication overhead under real-time deadline and process size constraints, while allocating functions to processors suited to those functions.

J. Hou and W. Wolf. Process partitioning for distributed embedded systems. Int. Workshop on Hardware/Software Co-Design (CODES/CASHE), 1996, pp. 70-76.



P.V. Knudsen and J. Madsen. Integrating communication protocol selection with partitioning in Hardware/Software Co-Design. Int. Symp. on System Synthesis (ISSS), 1998, pp. 111-116.

• 93 citations, • Incorporates communication protocol

selection as a design parameter within hw/sw partitioning.

• Considers data transfer rates depending on communication protocol types and configurations, and different operating frequencies of system components, e.g., CPUs, ASICs, and buses.

• Considers timing and area influences of drivers and driver calls needed to perform the communication.



• 98 citations, – Also one of the top-three most cited

by the CODES/ISSS community with 13 citations.

• Algorithm for generation of low cost communication topologies for statically scheduled systems. – Given a set of processes

communicating via abstract send and receive methods and detailed information on communication requirements of each process, performs a clustering of data transfers and, for each cluster, the approach executes a bus generation algorithm that schedules bus accesses while minimizing total communication cost.

M. Gasteier and M. Glesner. Bus-based communication synthesis on system-level. Int. Symp. on System Synthesis (ISSS), 1996, pp. 65-70.



• 108 citations. • Especially interesting due to the paper

being recent (2002)• Scratchpad memory as a means of

reducing energy. • By using a compiler to insert

instructions that move data to and from an on-chip SRAM, rather than relying solely on cache, the simpler memory design and control yields reduced energy

• Of note is that all 108 citations appear to come from outside CODES/ISSS.

R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, P. Marwedel. Scratchpad memory: design alternative for cache on-chip memory in embedded systems. Int. Symp. on Hardware/Software Co-Design (CODES), 2002, pp. 73-78.



• 194 citations.

• Generates synthetic task graphs that can model applications being input to a system synthesis or scheduling tool.

• The tool’s synthetic task graphs have been used by numerous subsequent synthesis and scheduling approaches, accounting for many of the citations.

R.P. Dick and W. Wolf. TGFF: Task graphs for free. Int.. Workshop on Hardware/Software Codesign (CODES/CASHE), 1998, pp. 97-101.



• New general problems (bus/communication synthesis, multi-processor process partitioning)

• New solutions (scratchpad mem, ASIP design/compilation)• Framework

Compared top-3 per year with bottom-3 per year

Top 3 tended to be big ideas, bottom 3 very specific solutions (still useful!)

Predictable from the titles alone


Citation Patterns (All, and Intra-Community)

0

10

20

30

40

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1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93

Paper rank by citations for given year

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2001All

2001Comm

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1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31


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2003Comm

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1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79


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2002All

2002Comm

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1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41


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2004All

2004Comm


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1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61


Num

ber o

f cita

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2003All

2003Comm

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1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70


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2003Comm

FPGA/FCCM MICRO/ISCA

2000 and 2006 were similar. Of note: A MICRO/ISCA paper from 2000 had 939 citations, with 123 from within their community: “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations.” Like the most highly-cited CODES/ISSS paper, that paper described a framework that enabled extensive subsequent research by others in the community.

Citation Patterns (All, and Intra-Community) for FPGA/FCCM, and

for MICRO/ISCA 2003

0

10

20

30

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1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31


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CODES/ISSS


Percentage of Citations to CODES/ISSS Papers Coming from Within CODES/ISSS

0%

5%

10%

15%

20%

25%

30%

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006

% c

itatio

ns fr

om c

omm

unity


The Other Way – References by a Community’s Papers to Other Papers in the

Same Community

0

5

10

15

20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Paper ranked by references to own community

Refer

ence

s to

own

com

mun

ity

CODES/ISSS'06

FPGA/FCCM'06

MICRO/ISCA'06

For all the papers of each community (not just the top 25), 18% of all MICRO/ISCA references were to papers within the community; the FPGA/FCCM rate was 6%, and the CODES/ISSS rate was 3%.

References

[1] Google Scholar from Wikipedia. http://en.wikipedia.org/wiki/Google_Scholar.

[2] S. Aditya, B. Ramakrishna Rau, V. Kathail. Automatic architectural synthesis of VLIW and EPIC processors. Int. Symp. on System Synthesis (ISSS), 1999, p. 107.

[3] M. Arnold , H. Corporaal. Designing domain-specific processors. Int. Symp. on Hardware/Software Co-Design (CODES), 2001, pp. 61-66.

[4] K. Atasu, G. Dündar, C. Özturan. An integer linear programming approach for identifying instruction-set extensions. Int. Conference on Hardware/Software Co-Design and System Synthesis (CODES/ISSS), 2005, pp. 172-177.

[5] R. Banakar, S. Steinke, B. Lee, M. Balakrishnan, P. Marwedel. Scratchpad memory: design alternative for cache on-chip memory in embedded systems. Int. Symp. on Hardware/Software Co-Design (CODES), 2002, pp. 73-78.

...


Conclusions

• Highly-cited papers– Useful for study, graduate seminars, ...

– Features: New problems, new ideas, or useful framework

– Beware of positive feedback "runaway" phenomena

Tough to catch up

• Questions...– Would more citing (appropriate, of course) benefit the community?

• h-index; also better tracing of research• Are page limits (typically 6; other confs 10-12) a barrier? (No longer page costs)

– Citations differences (vs other communities) due to more quality conferences in our area? Nature of relationship with industry? Multiple tracks?

– Need for focus areas?• "Grand challenges" (akin to sequencing of human genome)? Focus on application areas?

– Need for common benchmarks and frameworks?– Encourage (in CFP) reproduction/comparison of others’ work?– Encourage (in CFP) posting of complete data, examples, even tools?

• (This year, my students are posting data/tools to encourage improvement/comparison)

– ???

Documents

Frank Vahid, Univ. of California, Riverside 1/17 Highly-Cited Ideas in System Codesign and Synthesis Frank Vahid Dept. of Computer Science and Engineering