FPGA Implementation of Simple Microprocessor

Introduction: A microprocessor in a Field-Programmable Gate Array (FPGA) is not world news, but a free 8051 emulated core with a Controller Area Network (CAN) interface in a FPGA is not available at the marked at the moment. The embedded microprocessor core chosen for this project is a free soft core 8-bit RISC processor from Xilinx named PicoBlazeTM, implemented in a XC3S200 Spartan-3 FPGA at the development board “Spartan-3 starter kit board” from Xilinx. The FPGA today is used in a lot of products from Digital Video Technologies, Industrial/Scientific & Medical, Wireless Communications to Satellites project in orbit. Satellites and cars typically uses CAN for communication between Microprocessors.

Benjamin Grydehoej - BEng (Honours) Electronic and Computer Engineering Supervisor: Dr. Thomas David Binnie

NAPIER UNIVERSITY

Emulated 8051 Microprocessor

Special Function Register (SFR):Special Function Register (SFR):Special Function Register (SFR): • The SFR control all the call to Ports,

serial UART, interrupt control, timer etc.

WATCHDOG TIMER (WDT):WATCHDOG TIMER (WDT):WATCHDOG TIMER (WDT): • If the WDT is set and not cleared

before every 65ms will the system auto reset.

• The microprocessor reset is with a HIGH

SYSTEM CLOCK:SYSTEM CLOCK:SYSTEM CLOCK: • Standard option is 50MHz • Run up to 200MHz or 100MIPS in a

Virtex-II Pro FPGA CONTROL:CONTROL:CONTROL: • Control signal for external Rom and

RAM or other peripherals compo-nents

ADDRESS DADDRESS DADDRESS DECODER:ECODER:ECODER: • Address bus expander up to 16 bit

with a latch the 8 bit data bus to the low end of 8 the bit address bus, this function is normally done outside the microcontroller

I/O PORTS:I/O PORTS:I/O PORTS: • Port 4 and 5 is clearly data ports at

8 bit • Port 1 and 3 distribute the external

interrupt, timer, Serial RS232 and CAN

Specification and Block Diagram over the Emulated 8051 Microprocessor with CAN bus interface:

Boot RomInstruction Code

1K x 16

PicoBlazeCore

Serial UART

Timer

Serial Flash Rom Interface

CAN Bus UART

Special Function Register

8051

Em

ulat

ion

Perip

hera

ls

Watchdog Timer

Reset

System Clock

CLK (50MHz)

ControlWRRD

PSEN

EA

Address Decoder

Data[7:0]ADD[15:0]

I/O PORTS

P1[7:0]P3[7:0]P4[7:0]P5[7:0]

Inte

rnal

Add

ress

/Dat

a an

d C

ontr

ol B

us

Serial Flash Rom

FPGA

Platform Flash

JTAG

JTAG

PICROBLAZ core PICROBLAZ core PICROBLAZ core and and and BOOT ROM:BOOT ROM:BOOT ROM: • 16 Byte wide Arithmetic Logic Unit(ALU)

with CARRY and ZERO indicator flag • 64-byte internal scratchpad RAM • 256 input and 256 output ports • Automatic 31-location

CALL/RETURN stack • Predictable performance, always two

clock cycles per instruction • Fast interrupt response; worst-case 5

clock cycles • 1,024-Instruction Program Store

18 bits wide SERIAL UART (RS232):SERIAL UART (RS232):SERIAL UART (RS232): • Standard configuration 1 start bit,

8 data bits, No Parity and 1 stop bit. • Baud rates from 9600 to 115200. CAN BUS UART:CAN BUS UART:CAN BUS UART: • Designed to ISO 11898-1, CAN 2.0 A & B • Supports bit rates up to 1Mbit/s for

CAN 2.0B TIMER:TIMER:TIMER: • Timer 0 and 1 as 8-bit timer • Timer 2 as 16-bit timer SERIAL FLASH ROM INTERFACE:SERIAL FLASH ROM INTERFACE:SERIAL FLASH ROM INTERFACE: • Controller interface of extern serial

program store up to 2Mbit

Controller Area Network Specification 2.0A & 2.0B Introduction to CAN: The CAN Bus interface is a serial asynchronous transmission scheme, that uses a communication protocol which efficiently supports distribution of real time control with a very high level of security. The specification is defined with the ISO 11898 “OSI Model”. The CAN 2.0A is an extended message format defined in CAN 1.2 and CAN 2.0B describing both standard and extended message formats.

Physical Layer: • Balanced differential 2-wire interface bus using either a

shielded Twisted Pair (STP) or Un-shielded (UTP) cable with a male 9-PIN SUB-D connector

• Less than 40 meters-1Mbps, and less at 1km-20Kbps • Non Return to Zero (NRZ) bit encoding

Transfer Layer: Message transfer is manifested and controlled by four different frame types: • The Arbitration field identifier the ID. • The Control field consists of four bits Data length Code that identify

how many Bytes there are in the data packet • The Data field consists of the data to be transferred • The Cyclic Redundancy Code (CRC) sequence is calculate from the

Start Of Frame (SOF) field to and with the Data field, with the polynomial X15+X14+X10+X8+X7+X4+X3+1

• The ACK field acknowledgment a valid message received correctly

Object Layer: There are 5 different error types: • Bit Error, Stuff Error, CRC Error, Form Error and

Acknowledgment Error.

Evolution - Simulation - Test and Result

WWW.BG-ELEKTRONIK.DK/FPGA

Development of a Microprocessor in a FPGA: • VHDL Design in Xilinx ISE Project Navigator • Assembler and ANSI C programming with Picoblaze C Compiler

named PCCOMP by Francesco Poderico for software development • Convert the code to machine code in VHDL format, using the KCPSM3 • Software debugging the Assembler code in Mediatronix pBlazeIDE • Simulation of Software and VHDL Design in ModelSim XE • Download the data to the development board via JTAG interface using

the program named iMPACT • Test of the circuit using a Logic Analyzer

Current Results 22/02/2006: The microprocessor core is running on the board with Serial UART and it is possible to communi-cate (read & write) with the parallel I/O ports. The CAN bus interface is the part of the project that will be worked out over the next weeks before the 8051 emulated peripherals will be designed.

Practical test with Logic Analyzer

Development and Simulation