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Flip Flop Chapter 15 Subject: Digital System Year: 2009

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Page 1: Flip Flop Chapter 15 Subject: Digital System Year: 2009
Page 2: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Flip FlopChapter 15

Subject : Digital SystemYear : 2009

Page 3: Flip Flop Chapter 15 Subject: Digital System Year: 2009

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Overview• Latch and Flip Flop• Propagation Delay, Set-up time, Hold time in the

application of flip flop• Apply flip flop in basic operation

Page 4: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Flip Flop• Flip-flops are synchronous bistable devices, also

known as bistable multivibrators. In this case, the term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK), which is designated as a control input, C; that is, changes in the output occur in synchronization with the clock.

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Page 5: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Edge-triggered Flip-Flop logic Symbol

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Page 6: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered S-R Flip-Flop

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Page 7: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered S-R Flip-Flop

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Page 8: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered S-R Flip-Flop

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Page 9: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered D Flip-Flop

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Page 10: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered J-K Flip-Flop

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Page 11: Flip Flop Chapter 15 Subject: Digital System Year: 2009

The Edge-Triggered J-K Flip-Flop

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Page 12: Flip Flop Chapter 15 Subject: Digital System Year: 2009

FLIP-FLOP OPERATING CHARACTERISTICS

• A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur. Four categories of propagation delay times are important in the operation of a flip-flop: – Propagation delay t PLH as measured from the triggering edge

of the clock pulse to the LOW-to-HIGH transition of the output.

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Page 13: Flip Flop Chapter 15 Subject: Digital System Year: 2009

FLIP-FLOP OPERATING CHARACTERISTICS

– Propagation delay t PHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output.

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Page 14: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Set-up Time

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• The set-up time is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or Sand R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Page 15: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Hold Time • The hold time is the minimum interval required

for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

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Page 16: Flip Flop Chapter 15 Subject: Digital System Year: 2009

Flip Flop Application

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