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Flip-Flop Applications

Registers

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Registers

a register is a collection of flip-flops

basic function is to hold information

a shift register is a register thatmoves information on the clock signal

serial-in/serial-out

serial-in/parallel-out

parallel-in/serial-out

parallel-in/parallel-out

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Serial-in, serial-out unidirectional shift register.

Figure 6.26

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Parallel-in unidirectional shift register.

Figure 6.28

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Universal shift register. (a) Logic diagram. (b) Mode control.(c) Symbol.

Figure 6.29

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Flip-Flop Applications

Counters

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Counters

Also called pattern generators

Function: produce a specified outputpattern sequence

Types of counters Binary ripple counters (asynchronous counters)

Synchronous counters

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State diagram of a counter.

Figure 6.30

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Binary Ripple Counters

also called asynchronous binarycounters

the LSB flip-flop recieves clock input

from a clock source

the ithflip-flop recieves clock inputfrom output of the ith-1 flip-flop

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Four-bit binary ripple counter. (a) Logic diagram. (b) Timingdiagram. (c) Counting sequence.

Figure 6.31

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Synchronous Binary Counters

Solve the settling time problem of theripple counters

Every flip-flop changes on clock input

simultaneously

Large number of flip-flops can causeloading complications

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Four-bit synchronous binary counter.

Figure 6.32

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Four-bit synchronous binary counter variation.

Figure 6.33

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Four-bit synchronous binary counter with parallel loadinputs. (a) Logic diagram. (b) Symbol.

Figure 6.34

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Synchronous mod-10 counter. (a) Connections. (b) Countingsequence.

Figure 6.35

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8-bit synchronous binary counter constructed from two 4-bitsynchronous binary counters.

Figure 6.36

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Counters Based on Shift Registers

Nonbinary counters

a ring counter: a circular shift registerwhere only one flip-flop is in 1-state and

the rest are in 0-state a switch-tail counter (twisted-ring

counter or Johnson counter):complement of the rightmost flip-flopbecomes input of the leftmost flip-flop

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Mod-4 ring counter. (a) Logic diagram. (b) Countingsequence.

Figure 6.37

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Mod-8 twisted-ring counter. (a) Logic diagram. (b) Countingsequence.

Figure 6.38

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Mod-7 twisted-ring counter. (a) Logic diagram. (b) Countingsequence.

Figure 6.39

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Synchronous Counter Design

To design a synchronous counter,perform the following steps

Decide the counting sequence

Draw an excitation table, whichconsists of 3 parts

Present state| Next state| flip-flop inputs

(flip-flop inputs can be obtained from an application

table of the selected flip-flop)

Determine inputs of each flip-flop

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General structure of a synchronous mod-6 counter usingpositive-edge-triggered JK flip-flops.

Figure 6.40

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Determination of the minimal-sum expressions for asynchronous mod-6 counter using clocked JK flip-flops.

Figure 6.41

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Logic diagram of a synchronous mod-6 counter.

Figure 6.42

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Determination of the minimal-sum expressions for asynchronous mod-6 counter using clocked D flip-flops.

Figure 6.43

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Determination of the minimal-sum expressions for asynchronous mod-6 counter using clocked T flip-flops.

Figure 6.44

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Determination of the minimal-sum expressions for asynchronous mod-6 counter using clocked SR flip-flops.

Figure 6.45

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