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Flip-Flops
Basic concepts
1/51 A. Yaicharoen 2
Flip-Flops A flip-flop is a bi-stable device: a circuit
having 2 stable conditions (0 or 1) 3 classes of flip-flops
latches: outputs respond immediately whileenabled (no timing control)
pulse-triggered flip-flops: outputs responseto the triggering pulse
edge-triggered flip-flops: outputs responsesto the control input edge
1/51 A. Yaicharoen 3
Conventions The circuit is set means output = 1 The circuit is reset means output = 0 Flip-flops have two output Q and Q′ or (Q and
Q) Due to time related characteristic of the flip-
flop, Q and Q′ (or Q) are usually representedas followed: Qt or Q: present state Qt+1 or Q+: next state
1/51 A. Yaicharoen 4
4 Types of Flip-FlopsSR flip-flop JK flip-flop
D flip-flop T flip-flop
S R Qt+1 Q’t+1
0 0 Qt Q’t
0 1 0 1
1 0 1 0
1 1 Prohibited
J K Qt+1 Q’t+1
0 0 Qt Q’t
0 1 0 1
1 0 1 0
1 1 Q’t Qt
D Qt+1 Q’t+1
0 0 1
1 1 0
T Qt+1 Q’t+1
0 Qt Q’t
1 Q’t Qt
1/51 A. Yaicharoen 5
SR LatchAn SR (or set-reset) latch consists of
S (set) input: set the circuit R (reset) input: reset the circuit Q and Q’ output: output of the SR latch in normal and
complement form
Application example: a switch debouncer
S R Qt+1 Q’t+1
0 0 Qt Q’t
0 1 0 1
1 0 1 0
1 1 Prohibited
1/51 A. Yaicharoen 6
SR latch
1/51 A. Yaicharoen 7
An application of the SR latch
(a) Effects of contactbounce.
(b) A switchdebouncer.
1/51 A. Yaicharoen 8
latch
!
SR
1/51 A. Yaicharoen 9
Gated SR latch
(c)
1/51 A. Yaicharoen 10
Gated D latch
1/51 A. Yaicharoen 11
Timing ConsiderationWhen using a real flip-flop, the following information
is needed to be considered: propagation delay (tpLH, tpHL) - time needed for an
input signal to produce an output signal minimum pulse width (tw(min)) - minimum amount of
time a signal must be applied setup and hold time (tsu, th) - minimum time the
input signal must be held fixed before and after thelatching action
1/51 A. Yaicharoen 12
Propagation delays in an SR latch
1/51 A. Yaicharoen 13
Timing diagram for an SR latch
1/51 A. Yaicharoen 14
Minimum pulse width constraint
1/51 A. Yaicharoen 15
Timing diagram for a gated D latch
1/51 A. Yaicharoen 16
Unpredictable response in a gated D latch
1/51 A. Yaicharoen 17
Master-slave SR flip-flop
1/51 A. Yaicharoen 18
Timing diagram for a master-slave SR flip-flop
1/51 A. Yaicharoen 19
Master-slave JK flip-flop
1/51 A. Yaicharoen 20
Timing diagram for master-slave JK flip-flop
1/51 A. Yaicharoen 21
Master-slave D flip-flop
1/51 A. Yaicharoen 22
Master-slave T flip-flop
1/51 A. Yaicharoen 23
Positive-edge-triggered D flip-flop
1/51 A. Yaicharoen 24
Timing diagram for a positive-edge-triggered D flip-flop
1/51 A. Yaicharoen 25
Negative-edge-triggered D flip-flop
1/51 A. Yaicharoen 26
Asynchronous Inputs do not require the presence of a control
signal preset (PR) - set the flip-flop clear (CLR) - reset the flip-flop
useful to bring a flip-flop to a desiredinitial state
1/51 A. Yaicharoen 27
Positive-edge-triggered D flip-flop with asynchronous inputs
1/51 A. Yaicharoen 28
Positive-edge-triggered JK flip-flop
1/51 A. Yaicharoen 29
Positive-edge-triggered T flip-flop
1/51 A. Yaicharoen 30
Master-slave JK flip-flop with data lockout
1/51 A. Yaicharoen 31
Characteristic Equations algebraic descriptions of the next-state
table of a flip-flop constructing from the Karnaugh map for
Qt+1 in terms of the present state andinput
1/51 A. Yaicharoen 32
Characteristic equations