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ACKNOWLEDGEMENT

With great pleasure we want to take this opportunity to express our

heartfelt gratitude to all the people who have helped us in making this

project work a grand success.

We are very much thankful to XXXX, Project Guide,

CMC, Hyderabad for giving us this opportunity to do this project. We

express our deep sense of gratitude to XXXX for his constant guidance

throughout our project work. Their timely suggestions and direct

involvement at different stages of the project work helped us in completing

our project successfully on time.

It has been a great pleasure and enlightening

experience to work under them during the course of this project. We are also

thankful to all those who helped us directly or indirectly.


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LIST OF FIGURES


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LIST OF TABLES


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ABSTRACT


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CONTENTS

Introduction to embedded systemsTechnology usedStepper motorP89V51RD2 MicrocontrollerSerial communicationCircuits and their operationprogramming

Applications and advantagesConclusionBibliography


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INTRODUCTION TO EMBEDDED SYSTEMS

1.1.Introduction

Computer systems are found everywhere. It is probably no

surprise that millions of computing systems are built every year, destined

for desktop computers like personal computers, laptops, workstations,

mainframes and servers. What may be surprising is that billions of

computing systems are built every year for a very different purpose. They

are embedded with in larger electronic devices, repeatedly carrying out a

particular function. Often going completely unrecognized by the device's

user. Creating a precise definition of the embedded computing systems or

simply the embedded systems is not an easy task Here we will try to

define embedded systems.

Embedded systems are electronic devices that incorporate

microprocessors with in their implementations. The main purposes of the

microprocessor are to simplify the system design and provide flexibility

Having a microprocessor in the device means that removing the bugs,

making modifications, or adding new features are only matters of rewriting

the software that controls the device. Or in other words Embedded

computer systems are electronic systems that include a microcomputer to

perform a specific dedicated application the computer is hidden inside

these products Embedded systems are ubiquitous. Every week millions of

tiny computer chips come pouring out of factories like Motorola, Intel,

Philips, and Mitsubishi finding their way into our everyday products.

Our global economy, our production of food, our transportation

systems, our military defense organizations, our communication systems,


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and even our quality of life depend on the efficiency and effectiveness of

these embedded systems. Unlike PCs, however embedded systems may

not have a disk drive and so the software is often stored in a read-only

memory (ROM) chip this means that modifying the software requires

either replacing or reprogramming the ROM.

Embedded systems are found in a variety of common electronic

devices, such as consumer electronics (cell phones. pagers, digital

cameras, camcorder, videocassette recorders, portable video games,

calculators and personal digital assistants), home appliances (microwave

ovens, answering machines, thermostats, home security systems,

washing machines and lighting machines). Office automation (fax

machines, copiers, printers and scanners), business equipment (cash

registers, curbside check-in alarm system, card readers, product scanners

and automated teller machines), and automobiles (transmission control,

cruise control, fuel injection, anti lock brakes, active suspension and wheel

alignment) One might say that nearly any device that runs on electricity

either already or soon it will have a computing system embedded within it.

Although embedded computers typically cost far less than desktopcomputers, their quantities are huge. For example in 1999, if a typical

American house have had one desktop computer, but each one had

between 35 and 50 embedded computers .With that number expected to

rise to nearly 300 by 2005.Today's embedded systems are so inexpensive

that they are used in almost all electronics products in our life. In many

cases we are not aware that a computer is present and so don't realize

just how pervasive they have become.

For example, although the typical family may own one or two

personal computers, the number of embedded computers found with in

their home and cars and among their personal belongings is much


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greater.

Embedded application programs present some new challenges

such as reliability, performance and cost.

Reliability expectations will place greater responsibility on

programmers to eliminate bugs and to design our software to tolerate

errors and unexpected simulations Many embedded systems need to run

24 hours a day, seven days a week and 365 days an year. You can't just

"reboot" the system when something goes wrong. For this reason, good

coding practices and thorough testing take on a new level ofimpol1ance in

the realm of embedded processors

Performance goals force us to learn and apply new techniques

such as multitasking and multi-scheduling. The need to communicate

directly with the sensors, actuators, keypads, displays, etc., will require

programmers to have a better understanding of how alternative methods

for performing input and output provide opportunities to trade speed,

complexity and cost. Although we'll usually program in a high level

language for better productivity, use of these alternatives will occasionally

require that we drop to the level of computer and program directly in

assembly language.

Embedded systems have several common characteristics that

distinguish such systems from other computing systems

1. Single-functioned:

An embedded system usually executes a specific programrepeatedly. For example a pager is always a pager In contrast,, a desktop

computer executes a variety of programs, like spread sheets. word

processors and video games with new programs added frequently Of

course there are exceptions. One case is that where an embedded system

s program is updated with a newer program version. For example some


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cell phones can be updated in such a manner. A second case Is where

several programs are swapped In and out of the system due to size

limitations For c\ample, some missiles run one program while in cruise

mode, then load a second program Corm locking on to the target

Nevertheless we can see that c\en these' exceptions represent systems

with a specific function

2. Tightly constrained:

All computing systems have constraints design metrics those on

embedded systems can be especially tight . design metric IS measure of

implementation's features such as cost. SI7C, performance and power.

Embedded system often must cost just a few dollars must he sized to fit in

on a single chip, must perform fast enough to process detail n the recall

time,. And must consume minimum power to extend the battery period or

prevent the necessity of a cooling fan.

3. Reactive and real time:

Many embedded systems must continually react to the changes in

the system's environment and must compute certain results in real time

without delay. For example a car's cruise controller continually monitors

and reacts to speed and break sensors. It must compute the acceleration

or the deceleration amounts repeatedly with in a limited time; a delayed

computation could result in a failure to maintain control of the car.

In contrast a desktop system focuses on the computations with

relatively infrequent (from the computer's perspective) reactions to the

input devices. In additions delay in those computations, while perhaps


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inconvenient to the computer user, but does not result in any system

failure.

1.2. Embedded processors

The embedded systems that found in most of the consumer products

employ a single


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the run-time library.

EC++ (Embedded C++) is a new language that is a proper subset

of C++ that has many of its object oriented facilities but that omits those

non-essential features that increase the code size and impair run-time

performance. EC++ was designed by a group of Japanese

microprocessor manufacturer called EC++ Technical Group. The

language has generated a lot of interest in the embedded community and

will undoubtedly finds its way into the embedded applications as soon as

commercial compilers become widely available for a large number of

target processors

Uniqueness of building an embedded application

To understand this first we have to be familiar with the tools and

software components used to build a desktop application program and

load it into the memory for execution. This process is summarized in the

fig.

Object files executable

Image file

Run-time library

Operating system image

LINKER

Compiler

Assembler Loader

Boot process


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Fig.: The build and load process for desktop application

program

When you want to run a desktop application program, its

executable image is loaded from the disk into the memory by a part of the

operating system known as the loader. The operating system itself there in

the memory put there ,during the boot process

The desktop system is intended to run a number of different

application programs, Thus a read/write main memory is used so that an

entirely different application program can be quickly and easily loaded into

the memory, replacing the previous application whenever necessary,

Unlike general-purpose desktop systems, embedded systems are

designed to serve a single purpose, Once the embedded software is there

in the memory, there is usually no reason to change it. This allows a less-

expensive read-only memory to be used for permanent storage of the

program, Since there is no need to store the program on disk, a significant

amount of software can be eliminated that would otherwise be necessary

to support a file system,


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Executable

object files image file ROM image

Re-entrant library

Real-time Kernel

Fig. The build and load process for embedded applicationprogram

Both the application's software and a reed-lime kernel are stored in

the same read only memory as a single program image, A real-lime kernel

is a one which manages the processor time and memory)' utilization

among a number of concurrent threads With no need for a file system, the

kernel is much smaller than a regular operating system and is easily linked

into the program as yet another object file as shown in the above figure

In general. the same kinds of software-development tools are used

to build both embedded and desktop applications Although tool suites

designed especially for ell1bedded-application development are

commercially available, in many cases it is possible to use the same

compiler, assembler and linker that you use for the desktop applications

There are two important difference, however. First, the run-time library that

comes with the compilers for desktop applications is usually not intended

for multitasking applications and must be replaced by the one that is re-

LINKER LOCATE

R

Compiler

Assembler

ROM burner


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entrant Second, additional software called locator is required to convert

the linker's output to a form suitable for storing in read-only memory.

When a desktop operating system loads an executable program image

produced by a linker in to memory, it has to modify a few bytes whose

values depend on the address where the program is to be loaded. Before

we can use such an executable image to permanently store our

embedded program in a read-only memory, we must perform the same

"fix-ups" using the program called a locator

. 1.4. Size of typical embedded programs

We've grown used to desktop application programs that require

several megabytes of memory and disk space. So it is surprising how little

memory is used in embedded products, especially when you consider that

both the embedded applications and its real-time kernel are stored in

memory. If we consider a real time embedded device the FAX Machine as

an example with a RAM of 2048 bytes and ROM of 32KB and with a 16 bit

microprocessor then the total RAM actually used is 66% and amount used

by kernel is 19%and for ROM the total memory used is 90% and the

amount used by kernel is 8.7%.

1.5. Difference between Embedded Systems (ES) and PC (computer)

Embedded systems differ from a normal PC in several ways. Even

though the ES is capable of computation and other jobs done by PC, it is

not a complete PC It may not have a key board, a monitor or even for that

matter a processor. We do have an ES with all these, but not a must. PCs

are usually applicable to build general purpose software and most of the

applications we build are reusable. In case of ES, most of the

development might start from scratch The ES might he specific to some

application and components used in them might be home made But the


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latest ES technology enables one to use general-purpose hardware

and components, which can re used. The as of the Embedded systems

might not be complete, but only the basic functionalities of OS are taken in

a real time environment.

1.6. Parts of Embedded Systems

An Embedded system is mainly comprised of

a) Hardware

b) Real time Operating system (RTOS) c) Processor

d) Serial port, n/w port. j/o peripheral port

e) Sensors and actuators

f) Mechanical parts

1.7.Characteristics of Embedded Systems

a) Applications using ES must be reliable safe and secure

b) High efficiency

c) Mostly fixed set of application systems

d) Frequently reading, processing and controlling physical quantities

e) Must react after. guaranteed time limit

f) Most of the functionalities of the ES are implemented in software

Common microprocessors used for ES

a) ZilogZ8 family


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b) Intel 8051

c) X86 family

d) Motorola 68k family

e) PowerPC family

1.8.Introduction to applications of embedded system

Embedded controllers may be found in many different kinds of

system and are used for many different applications. The list, whichfollows, is indicative rather than exhaustive. An item in the list may be

relevant to a particular company because either

(a) It is or involves a core process or product,

(b) It is or involves an ancillary function or service performed by the

company

(c) It refers to a product or service provided by a contractor under some

form of agreement and the vulnerability of the supplier may need to be

considered.

Required skill sets to work on ES.

Intel Processors & Controllers Micro controllers

DSP Processors

C++,C

Lab View


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Mat Lab

RTOS (Real Time Operating System)

VX Works

ADA (Aerospace)

Hardware design & testing

VHDL

1.9.List of applications of embedded systems

(a) Manufacturing and process

control

Manufacturing plants

Water and sewage systems

J>power stations


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Power grid systems

Oil refineries and related storage facilities

bottling plants

Automated factories

Simulators

Test equipment for control system development, maintenance and

testing

(b) Construction industry

Surveying and location equipment Construction plant

(c) Transport

Aero planes

Trains

Buses

Marine craft (known cases include radar mapping; ballast

monitoring, cargo loading; ship performance monitoring; engine room

vibration monitor; service aid for ships control; ship main control system)

Automobiles

Fuel services

Air Traffic Control Systems

Signaling systems

Radar systems


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Traffic lights

Ticketing systems/machines

Car parking and other meters

(d) Buildings and premises

Electrical supply -supply, measurement, control, protection Backup

lighting and generators

Fire control systems

Heating and Ventilating systems

Lifts, elevators, escalators

Security systems

Security cameras

Safes and vaults

Door locks

(e) Domestic services

Catering

Cleaning

(f) Communications

Telephone exchange


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Cable systems

Telephone switches

Data switching equipment (X.25, SMDS, Frame Relay, etc.) Satellites

(g) Office systems and mobile equipment

Telephone systems

Faxes

Copier

Time recording systems Mobile telephones Still and video

cameras

(h) Banking, finance and commercial

Automated teller systems

Credit card systems

Point of sale systems including scanner/cash systems

(i) Medical diagnostics, monitoring and life support

Heart defibrillators

Pacemaker monitors

Patient information systems


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Patient monitoring systems

Pharmaceutical control and dispensing systems, e.g. infusion pumps X-

ray equipment

(j) Testing, monitoring and diagnostic systems

Energy metering Environmental-monitoring equipment

(k) Industrial functions of embedded systems

Multi-loop control and monitoring - DCS, SCADA, telemetry

Panel mounted devices - Control, display, recording and operations

Safety and security - Alarm and trip systems, fire and gas systems,

buildings and facilities security

Field devices - measurement, actuation

Analytical systems - Laboratory systems; on-line/ plant systems

Electrical supply - supply, measurement, control, protection

Tools - for design, documentation, testing, maintenance


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MICROCONTROLLER

Introduction to Micro controller:

Why we need a microprocessor/controller:

The microprocessor is the core of computer systems.

Nowadays many communications, digital entertainment, portable devices, are

controlled by them.

A designer should know what types of components he needs, ways to reduce production

costs and product reliable.

Different aspects of a microprocessor/controller:

Hardware: Interface to the real world

Software: order how to deal with inputs

The necessary tools for a microprocessor/controller:

CPU: Central Processing Unit

I/O: Input /Output

Bus: Address bus & Data bus

Memory: RAM &ROM

Timer

Interrupt

Serial Port

Parallel port

MICROPROCESSOR:

General-purpose microprocessor

CPU for Computers


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No RAM, ROM, I/O on CPU chip itself

Example: Intels x86, Motorolas 680x0

General purpose microprocessor system:

MICROCONTROLLER:

A smaller computer On-chip RAM, ROM, I/O ports...

Example: Motorolas 6811, Intels 8051, Zilogs Z8 and PlC 16X

A single chip microcontroller:

MICROPROCESSOR vs. MICROCONTROLLER

MICROPROCESSOR

CPU is stand-alone, RAM, ROM, I/O, timer are separate

CPU RAM ROM

I/O PORT TIMER SERIAL COM PORT

CPU

General

Purpose

Micro-

Processo

r

RAM ROM I/OPORT

Timer

Serial

COM

Port

Data Bus

Address Bus

General ur ose micro rocessor s stem


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Designer can decide on the amount of ROM, RAM and I/O ports.

Expansive

versatility

general-purpose

MICROCONTROLLER

CPU, RAM, ROM, I/O and timer are all on a single chip

fix amount of on-chip ROM, RAM, I/O ports

for applications in which cost, power and space are critical

Single-purpose

EMBEDDED SYSTEM:

Embedded system means the processor is embedded into that application.

An embedded product uses a microprocessor or microcontroller to do one task only.

In an embedded system, there is only one application software that is typically burned

into ROM.

Example: Printer, keyboard, video game player

Three criteria in Choosing a Microcontroller:

1. Meeting the computing needs of the task efficiently and cost effectively

Speed, the amount of ROM and RAM, the number of 1/0 ports and timers, size,

packaging, power consumption

easy to upgrade

cost per unit


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2. Availability of software development tools

assemblers, debuggers, C compilers, emulator, simulator, technical support

3. Wide availability and reliable sources of the microcontrollers.


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Introduction to Stepper Motors

A stepper motor is a permanent magnet or variable reluctance dc motor that has the

following performance characteristics:

1. rotation in both directions,

2. precision angular incremental changes,

3. repetition of accurate motion or velocity profiles,

4. a holding torque at zero speed, and

5. capability for digital control.

A stepper motor can move in accurate angular increments knows as steps in response to

the application of digital pulses to an electric drive circuit from a digital controller. Thenumber and rate of the pulses control the position and speed of the motor shaft.

Generally, stepper motors are manufactured with steps per revolution of 12, 24, 72, 144,

180, and 200, resulting in shaft increments of 30, 15, 5, 2.5, 2, and 1.8 degrees per step.

Stepper motors are eitherbipolar, requiring two power sources or a switchable polarity

power source, orunipolar, requiring only one power source. They are powered by dc

current sources and require digital circuitry to produce the coil energizing sequences for

rotation of the motor. Feedback is not always required for control, but the use of anencoder or other position sensor can ensure accuracy when it is essential. The advantage

of operating without feedback is that a closed loop control system is not required.

Generally, stepper motors produce less than 1 horsepower(746W) and are thereforefrequently used in low-power position control applications.

HOW STEPPER MOTORS WORK

We've all experimented with small "hobby motors", or free-spinning DC motors. Have you evertried to position something accurately with one? It can be pretty difficult. Even if you get the timing

just right for starting and stopping the motor, the armature does not stop immediately. DC motorshave a very gradual acceleration and deceleration curves; stabilization is slow. Adding gearing tothe motor will help to reduce this problem, but overshoot is still present and will throw off theanticipated stop position. The only way to effectively use a DC motor for precise positioning is to

use a servo. Servos usually implement a small DC motor, a feedback mechanism (usually apotentiometer with attached to the shaft by gearing or other means), and a control circuit whichcompares the position of the motor with the desired position, and moves the motor accordingly.This can get fairly complex and expensive for most hobby applications.

Stepper motors, however, behave differently than standard DC motors. First of all, they cannotrun freely by themselves. Stepper motors do as their name suggests -- they "step" a little bit at atime.Stepper motors also differ from DC motors in their torque-speed relationship. DC motorsgenerally are not very good at producing high torque at low speeds, without the aid of a gearingmechanism. Stepper motors, on the other hand, work in the opposite manner. They produce the


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highest torque at lowspeeds. Stepper motors also have another characteristic, holding torque,which is not present in DC motors. Holding torque allows a stepper motor to hold its positionfirmly when not turning. This can be useful for applications where the motor may be starting andstopping, while the force acting against the motor remains present. This eliminates the need for amechanical brake mechanism. Steppers don't simply respond to a clock signal, they have severalwindings which need to be energized in the correct sequence before the motor's shaft will rotate.Reversing the order of the sequence will cause the motor to rotate the other way. If the controlsignals are not sent in the correct order, the motor will not turn properly. It may simply buzz andnot move, or it may actually turn, but in a rough or jerky manner. A circuit which is responsible forconverting step and direction signals into winding energization patterns is called a translator.Most stepper motor control systems include adriverin addition to the translator, to handle thecurrent drawn by the motor's windings.

Figure 1.1 - A typical translator / driver connection

A basic example of the "translator

+ driver" type of configuration.

Notice the separate voltages for

logic and for the stepper motor.

Usually the motor will require a

different voltage than the logic

portion of the system. Typicallylogic voltage is +5 Vdc and the

stepper motor voltage can range

from +5 Vdc up to about +48 Vdc.

The driver is also an "open

collector" driver, wherein it takes

its outputs to GND to activate the

motor's windings. Most

semiconductor circuits are more

capable of sinking(providing a

GND or negative voltage) than

sourcing (outputting a positive

voltage).

COMMON CHARACTERISTICS OF STEPPER MOTORS:Stepper motors are not just rated by voltage. The following elements characterize a givensteppermotor:

VoltageStepper motors usually have a voltage rating. This is either printed directly on the unit, or isspecified in the motor's datasheet. Exceeding the rated voltage is sometimes necessary to obtainthe desired torque from a given motor, but doing so may produce excessive heat and/or shortenthe life of the motor.

ResistanceResistance-per-winding is another characteristic of a stepper motor. This resistance willdetermine current draw of the motor, as well as affect the motor's torque curve and maximumoperating speed.


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Degrees per stepThis is often the most important factor in choosing a stepper motor for a given application. Thisfactor specifies the number of degrees the shaft will rotate for each full step. Half step operationof the motor will double the number of steps/revolution, and cut the degrees-per-step in half. Forunmarked motors, it is often possible to carefully count, by hand, the number of steps perrevolution of the motor. The degrees per step can be calculated by dividing 360 by the number ofsteps in 1 complete revolution Common degree/step numbers include: 0.72, 1.8, 3.6, 7.5, 15, andeven 90. Degrees per step is often referred to as the resolution of the motor. As in the case of anunmarked motor, if a motor has only the number of steps/revolution printed on it, dividing 360 bythis number will yield the degree/step value.

Theory

Unipolar stepper motor

Fig.1 A unipolar stepper motor

Unipolar stepping motors with 5 or 6 wires are usually wired as shown in the schematicin Figure 1, with a center tap on each of two windings. In use, the center taps of the

windings are typically wired to the positive supply, and the two ends of each winding are

alternately grounded to reverse the direction of the field provided by that winding. Ananimated GIF of figure 1.2 is available. The motor cross section shown in Figure 1 is of a

30 degree per step motor -- the difference between these two motor types is not relevant

at this level of abstraction. Motor winding number 1 is distributed between the top and

bottom stator pole, while motor winding number 2 is distributed between the left andright motor poles. The rotor is a permanent magnet with 6 poles, 3 south and 3 north,

arranged around its circumfrence. For higher angular resolutions, the rotor must have

proportionally more poles. The 30 degree per step motor in the figure is one of the mostcommon permanent magnet motor designs, although 15 and 7.5 degree per step motors

are widely available. As shown in the figure, the current flowing from the center tap of

winding 1 to terminal a causes the top stator pole to be a north pole while the bottomstator pole is a south pole. This attracts the rotor into the position shown. If the power to

winding 1 is removed and winding 2 is energised, the rotor will turn 30 degrees, or one

step. To rotate the motor continuously, we just apply power to the two windings in

sequence. Assuming positive logic, where a 1 means turning on the current through amotor winding, the following two control sequences will spin the motor illustrated in

Figure 1 clockwise 24 steps or 4 revolutions:
http://mechatronics.mech.northwestern.edu/design_ref/actuators/uni_anim.gifhttp://mechatronics.mech.northwestern.edu/design_ref/actuators/uni_anim.gif


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Winding 1a 1000100010001000100010001

Winding 1b 0010001000100010001000100

Winding 2a 0100010001000100010001000

Winding 2b 0001000100010001000100010

time --->

Winding 1a 1100110011001100110011001

Winding 1b 0011001100110011001100110

Winding 2a 0110011001100110011001100

Winding 2b 1001100110011001100110011

time --->

Note that the two halves of each winding are never energized at the same time. Both

sequences shown above will rotate a permanent magnet one step at a time. The topsequence only powers one winding at a time, as illustrated in the figure above; thus, it

uses less power. The bottom sequence involves powering two windings at a time and

generally produces a torque about 1.4 times greater than the top sequence while usingtwice as much power.

Bipolar stepper motor

Fig 2. A bipolar stepper motor

Bipolar permanent magnet and hybrid motors are constructed with exactly the same

mechanism as is used on unipolar motors, but the two windings are wired more simply,

with no center taps. Thus, the motor itself is simpler but the drive circuitry needed toreverse the polarity of each pair of motor poles is more complex. The schematic in Figure

2 shows how such a motor is wired, while the motor cross section shown here is exactly

the same as the cross section shown in Figure 1. The drive circuitry for such a motorrequires an H-bridge control circuit for each winding. Briefly, an H-bridge allows the

polarity of the power applied to each end of each winding to be controlled independently.

The control sequences for single stepping such a motor are shown below, using + and -

symbols to indicate the polarity of the power applied to each motor terminal:

Terminal 1a +---+---+---+---

Terminal 1b --+---+---+---+-

Terminal 2a -+---+---+---+--

Terminal 2b ---+---+---+---+

time --->


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Note that these sequences are identical to those for a unipolar permanent magnet motor,

at an abstract level, and that avove the level of the H-bridge power switching electronics,

the control systems for the two types of motor can be identical. Note that many full H-bridge driver chips have one control input to enable the output and another to control the

direction. Given such bridge chips, one for eachwinding, the following control sequences

will spin the motor identically to the control sequences given above:

Enable 1 1111111111111111

Direction 1 1100110011001100

Enable 2 1111111111111111

Direction 2 0110011001100110

time --->

To distinguish a bipolar permanent magnet motor from other 4 wire motors, measure the

resistances between the different terminals. It is worth noting that some permanent

magnet stepping motors have 4 independent windings, organized as two sets of two.Within each set, if the two windings are wired in series, the result can be used as a high

voltage bipolar motor. If they are wired in parallel, the result can be used as a low voltagebipolar motor. If they are wired in series with a center tap, the result can be used as a lowvoltage unipolar motor.

Driving Stepper Motors with the L293D

The L293D contains two H-bridges (for more information on H-bridges, clickhere.) for

driving small DC motors. It can also be used to drive stepper motors because steppermotors are, in fact, two(or more) coils being driven in a sequence, backwards and

forwards. One L293D can, in theory, drive one bi-polar 2 phase stepper motor, if you

supply the correct sequence.

We are going to show how to drive a bipolar and a unipolar stepper motor with theL293D. The bipolar stepper motor and the unipolar stepper motor we used were bought

from Jameco. (part# 105881 and 105890 respectively). Both of the bipolar and unipolar

stepper motors are 3.6 degrees/step motors.

Bipolar Stepper Motor

The L293D chip has 16 pins. Here is how each of the pins should be connected:

Pin 1, 9 Enable pins. Hook them together and you can either keep them high and run themotor all the time, or you can control them with you own controller(e.g. 68HC11).

Pin 3, 6, 11, 14 Here is where you plug in the two coils. To tell which wires correspond

to each coil, you can use a mulitmeter to measure the resistance between the wires. Thewires correspond to the same coil has a much lower resistance than wires correspond to

different coils. (This method only applies to bipolar stepper motors. For unipolar stepper
http://mechatronics.mech.northwestern.edu/design_ref/actuators/hbridge_circuitry.htmlhttp://www.jameco.com/http://mechatronics.mech.northwestern.edu/design_ref/actuators/hbridge_circuitry.htmlhttp://www.jameco.com/


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motors, you have to refer to the spec. sheet to tell which wires correspond to each coil.)

You can then get one coil hooked up to pin 3,6 and another one hooked up to pin 11, 14.

Pin 4, 5, 12, 13 Gets hooked to ground.

Pin 8 Motor voltage, for the motors we are using, it is 12V.

Pin 16 +5V. It is the power supply of the chip and it's a good idea to keep this powersupply separate from your motor power.

Pin 2, 7, 10, 15 Control signals. Here is where you supply the pulse sequence. The

following is how you pulse them for a single-cycle (to move the motor in the oppositedirection, just reverse the steps. i.e. from step 4 to step1):

Coil 1a Coil 2a Coil 1b Coil 2b

Step 1 High High Low Low

Step 2 Low High High Low

Step 3 Low Low High High

Step 4 High Low Low High

In our example, we use the digital outputs of the Handy Board to generate the above

pulse. The SPI pins on the connector on the middle right edge of the Handy Board can beconfigured as digital outputs. Do a poke(0x1009, 0x3c) to make them outputs; then they

are mapped o the middle 4 bits of address 0x1008 (SS= bit 5, SCK=bit 4, MOSI=bit 3,

MISO=bit 2). Poke to that address (0x1008) to set them.

Here is the code fragment to generate the pulses:

int address=0x1008;

float x=0.005;

int i;

int t=100;

poke (0x1009, 0x3c);

for(i=0; i


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bk(1);

sleep(x);

fd(0);

bk(1);

sleep(x);

}

}

Again, the variable x controls how long the processor should wait between each step and

it determines the speed of the stepper motor. In the above example, the motor is set to

rotate forever but you can use a for loop instead to set how much the motor should turn.

Unipolar Stepper Motor

Driving a unipolar stepper motor using the Handy Board directly is the same as driving

the bipolar stepper motor with the Handy Board. You can use the same code fragment to

drive the unipolar stepper motor. The only difference is you have to connect the extracommon wire to the +5V supply.


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P89V51RD2

8-bit 80C51 5 V low power 16/32/64 kB Flash microcontrollerwith 1 kB RAM

General description

The P89V51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB Flash and1024 bytes of data RAM.

A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option. The designengineer can choose to run the application with the conventional 80C51 clock rate(12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) toachieve twice the throughput at the same clock frequency. Another way to benefit

from this feature is to keep the same performance by reducing the clock frequency byhalf, thus dramatically reducing the EMI.

The Flash program memory supports both parallel programming and in serialIn-System Programming (ISP). Parallel programming mode offers gang-programmingat high speed, reducing programming costs and time to market. ISP allows a deviceto be reprogrammed in the end product under software control. The capability tofield/update the application firmware makes a wide range of applications possible.

The P89V51RB2/RC2/RD2 is also In-Application Programmable (IAP), allowing theFlash program memory to be reconfigured even while the application is running.

Features

80C51 Central Processing Unit5 V Operating voltage from 0 MHz to 40 MHz16/32/64 kB of on-chip Flash user code memory with ISP (

Programming) and IAP (In-Application Programming)Supports 12-clock (default) or 6-clock mode selection via softwareSPI (Serial Peripheral Interface) and enhanced UARTPCA (Programmable Counter Array) with PWM and Capture/Four 8-bit I/O ports with three high-current Port 1 pins (16Three 16-bit timers/countersProgrammable watchdog timerEight interrupt sources with four priority levelsSecond DPTR register

Low EMI mode (ALE inhibit)TTL- and CMOS-compatible logic levelsBrown-out detectionLow power modes

-Power-down mode with external interrupt wake-up-Idle mode

DIP40, PLCC44 and TQFP44 packages


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Block diagram

P89V51RB2/RC2/RD2 block diagram.


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Symbol Pin Type Description

P0.0 to P0.7 39-32 I/O Port 0: Port 0 is an 8-bitopen drain bi-directional

I/Oport. Port 0 pins that have1s written to them float,andin this state can be usedas high-impedanceinputs.Port 0 is also themultiplexed low-orderaddress anddata bus during accessesto external code and datamemory. In thisapplication, it uses stronginternal

pull-ups whentransitioning to 1s. Port 0also receivesthe code bytes during theexternal host modeprogramming, andoutputs the code bytesduring theexternal host modeverification. External pull-ups arerequired during programverification or as ageneralpurpose I/O port.

P1.0 to P1.7 1-8 I/O with internal pull-up Port 1: Port 1 is an 8-bitbi-directional I/O port withinternal pull-ups. The Port1 pins are pulled high bytheinternal pull-ups when 1sare written to them andcanbe used as inputs in thisstate. As inputs, Port 1pins thatare externally pulled LOWwill source current (IIL)

because of the internalpull-ups. P1.5, P1.6, P1.7havehigh current drive of 16mA. Port 1 also receivesthelow-order address bytesduring the external hostmodeprogramming andverification.


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P1.0 1 I/O T2: External count inputto Timer/Counter 2 orClock-out fromTimer/Counter 2

P1.1 2 I T2EX: Timer/Counter 2capture/reload trigger anddirection control

P1.2 3 I ECI: External clock input.This signal is the externalclock input for the PCA.

P1.3 4 I/O CEX0: Capture/compareexternal I/O for PCAModule 0.Each capture/comparemodule connects to aPort 1 pin

for external I/O. When notused by the PCA, this pincanhandle standard I/O.

P1.4 5 I/O SS: Slave port selectinput for SPICEX1: Capture/compareexternal I/O for PCAModule 1

P1.5 6 I/O MOSI: Master OutputSlave Input for SPICEX2: Capture/compare

external I/O for PCAModule 2

P1.6 7 I/O MISO: Master Input SlaveOutput for SPICEX3: Capture/compareexternal I/O for PCAModule 3

P1.7 8 I/O SCK: Master OutputSlave Input for SPICEX4: Capture/compareexternal I/O for PCAModule 4

P2.0 toP2.7 21-28 I/Owith internalpull-up

Port 2: Port 2 is an 8-bitbi-directional I/O port withinternal pull-ups. Port 2pins are pulled HIGH bytheinternal pull-ups when 1sare written to them andcanbe used as inputs in thisstate. As inputs, Port 2


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pins thatare externally pulled LOWwill source current (IIL)because of the internalpull-ups. Port 2 sends thehigh-order address byteduring fetches from

externalprogram memory andduring accesses toexternal DataMemory that use 16-bitaddress (MOVX@DPTR).In thisapplication, it uses stronginternal pull-ups whentransitioning to 1s. Port 2also receives somecontrolsignals and a partial ofhigh-order address bitsduring

the external host modeprogramming andverification.

P3.0 toP3.7

10-17 I/Owith internalpull-up

Port 3: Port 3 is an 8-bitbidirectional I/O port withinternal pull-ups. Port 3pins are pulled HIGH bytheinternal pull-ups when 1sare written to them andcanbe used as inputs in thisstate. As inputs, Port 3

pins thatare externally pulled LOWwill source current (IIL)because of the internalpull-ups. Port 3 alsoreceivessome control signals anda partial of high-orderaddressbits during the externalhost mode programmingandverification.

P3.0 10 I RXD: serial input port

P3.1 11 O TXD: serial output port

P3.2 12 I INT0: external interrupt 0input

P3.3 13 I INT1: external interrupt 1input


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P3.4 14 I T0: external count inputto Timer/Counter 0

P3.5 15 I T1: external count inputto Timer/Counter 1

P3.6 16 O WR: external datamemory write strobe

P3.7 17 O RD: external datamemory read strobe

PSEN 29 I/O Program Store Enable:PSEN is the read strobeforexternal programmemory. When thedevice is executingfrom internal programmemory, PSEN is

inactive(HIGH). When the deviceis executing code fromexternal programmemory, PSEN isactivated twice eachmachine cycle, exceptthat two PSEN activationsareskipped during eachaccess to external datamemory. Aforced HIGH-to-LOWinput transition on thePSEN pin

while the RST input iscontinually held HIGH formorethan 10 machine cycleswill cause the device toenterexternal host modeprogramming.

RST 9 I Reset: While theoscillator is running, aHIGH logic stateon this pin for twomachine cycles will resetthe device. Ifthe PSEN pin is driven bya HIGH-to-LOW inputtransition while the RSTinput pin is held HIGH,thedevice will enter theexternal host mode,otherwise thedevice will enter thenormal operation mode.


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EA 31 I External AccessEnable: EA must beconnected to VSSin order to enable thedevice to fetch code fromthe

external programmemory. EA must bestrapped to VDDfor internal programexecution. However,Security locklevel 4 will disable EA,and program execution isonlypossible from internalprogram memory. The EApin cantolerate a high voltage of12 V.

ALE/PROG

30 I/O Address Latch Enable:ALE is the output signalforlatching the low byte ofthe address during anaccess toexternal memory. This pinis also the programmingpulse input (PROG) forflash programming.Normally theALE[1] is emitted at a

constant rate of16 thecrystal

frequency[2] and can beused for external timingandclocking. One ALE pulseis skipped during eachaccessto external data memory.However, if AO is set to1,ALE is disabled.

NCXTAL1

- I/O No Connect

XTAL1 19 I Crystal 1: Input to theinverting oscillatoramplifier andinput to the internal clockgenerator circuits.

XTAL2 18 O Crystal 2: Output fromthe inverting oscillatoramplifier.


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VDD 40 I Power supply

VSS 20 I Ground

[1] ALE loading issue: When ALE pin experiences higher loading (>30 pF) during

the reset, the microcontroller may accidentally enter intomodes other than normal working mode. The solution is to add a pull-up resistor

of 3 k to 50 k to VDD, e.g., for ALE pin.

[2] For 6-clock mode, ALE is emitted at 13 of crystal frequency.

Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in thefollowingways:

User must not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for theSFRs. SFR bits labeled -, 0 or 1 can only be written and read as follows:

- Unless otherwise specified, must be written with 0, but can return any valuewhen read (even if it was written with 0). It is a reserved bit and may be used infuture derivatives.

0 must be written with 0, and will return a 0 when read. 1 must be written with 1, and will return a 1 when read.

Functional description

Memory organization

The device has separate address spaces for program and data memory.

Flash program memory bank selection

There are two internal flash memory blocks in the device. Block 0 has 16/32/64kB and is organized as 128/256/512 sectors, each sector consists of 128 Bytes.


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Block contains the IAP/ISP routines and may be enabled such that it overlays thefirst 8 kB of the user code memory. The overlay function is controlled by thecombination of the Software Reset Bit (SWR) at FCF.1 and the Bank Select Bit(BSEL) at FCF.0. The combination of these bits and the memory source used forinstructions is shown in the below Table.

Table: Code memory bank selection

SWR (FCF.1) BSEL (FCF.0) addresses from 0000hto 1FFFh

addresses above 1FFFh

0 0 Bootcode (in Block 1) User code (in Block 0)

0 1 User code (in Block 0)

1 0

1 1

Access to the IAP routines in Block 1 may be enabled by clearing the BSEL bit(FCF.0), provided that the SWR bit (FCF.1) is cleared. Following a power-onsequence, the bootcode is automatically executed and attempts to autobaud to ahost. If no autobaud occurs within approximately 400 ms and the SoftICE flag isnot set, control will be passed to the user code. A software reset is used toaccomplish this control transfer and as a result the SWR bit will remain set.Therefore the user'scode will need to clear the SWR bit in order to access

the IAP routines in BlockHowever, caution must be taken when dynamically changing the BSEL bit. Since

this will cause different physical memory to be mapped to the logical programaddress space, the user must avoid clearing the BSEL bit when executinguser code within the address range 0000H to 1FFFH.

Power-on reset code execution

At initial power up, the port pins will be in a random state until the oscillator hasstarted and the internal reset algorithm has weakly pulled all pins high. Poweringup the device without a valid reset could cause the MCU to start executinginstructions from an indeterminate location. Such undefined states mayinadvertently corrupt the code in the flash. A system reset will not affect the 1 kBof on-chip RAM while the device is running, however, the contents of the on-chipRAM during power up are indeterminate.


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When power is applied to the device, the RST pin must be held high long enoughfor the oscillator to start up (usually several milliseconds for a low frequencycrystal), in addition to two machine cycles for a valid power-on reset. An exampleof a method to extend the RST signal is to implement a RC circuit by connectingthe RST pin to VDD through a 10 F capacitor and to VSS through an 8.2KW

resistor as shown in the above table.Note that if an RC circuit is being used, provisions should be made toensure the VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds.For a low frequency oscillator with slow start-up time the reset signal must beextended in order to account for the slow start-up time. This method maintainsthe necessary relationship between VDD and RST to avoid programming at anindeterminate location, which may cause corruption in the code of the flash. Thepower-on detection is designed to work during initial power up, before the voltagereaches the brown-out detection level. The POF flag in the PCON register is setto indicate an initial power up condition. The POF flag will remain active until

cleared by software.Following a power-on or external reset the P89V51RB2/RC2/RD2 will force theSWR and BSEL bits (FCF[1:0]) = 00. This causes the bootblock to be mappedinto the lower 8 kB of code memory and the device will execute the ISP code inthe boot block and attempt to autobaud to the host. If the autobaud is successfulthe device will remain in ISP mode. If, after approximately 400 ms, the autobaudis unsuccessful the boot block code will check to see if the SoftICE flag is set(from a previous programming operation). If the SoftICE flag is set the device willenter SoftICE mode. If the SoftICE flag is cleared, the bootcode will execute asoftware reset causing the device to execute the user code from block 0 startingat address 0000h. Note that an external reset applied to the RST pin has the

same effect as a power-on reset.


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Power-on reset circuit.

Software reset

A software reset is executed by changing the SWR bit (FCF.1) from 0 to 1. Asoftware reset will reset the program counter to address 0000H and force boththe SWR and BSEL bits (FCF[1:0]) =10. This will result in the lower 8 kB of theuser code memory being mapped into the user code memory space. Thus theuser's code will be executed starting at address 0000h. A software reset will notchange WDTC.2 or RAM data. Other SFRs will be set to their reset values.

Brown-out detect reset

The device includes a brown-out detection circuit to protect the system fromsevere supply voltage fluctuations. The P89V51RB2/RC2/RD2's brown-outdetection threshold is 2.35 V. When VDD drops below this voltage threshold, thebrown-out detect triggers the circuit to generate a brown-out interrupt but theCPU still runs until the supplied voltage returns to the brown-out detectionvoltage VBOD. The default operation for a brown-out detection is to cause aprocessor reset.


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VDD must stay below VBOD at least four oscillator clock periods before thebrown-out detection circuit will respond.Brown-out interrupt can be enabled by setting the EBO bit (IEA.3). If EBO bit isset and a brown-out condition occurs, a brown-out interrupt will be generated toexecute the program at location 004BH. It is required that the EBO bit be cleared

by software after the brown-out interrupt is serviced. Clearing EBO bit when thebrown-out condition is active will properly reset the device. If brown-out interruptis not enabled, a brown-out condition will reset the program to resume executionat location 0000H.A brown-out detect reset will clear the BSEL bit (FCF.0) but will not change theSWR bit (FCF.1) and therefore will not change the banking of the lower 8 kB ofuser code memory space.

Watchdog reset

Like a brown-out detect reset, the watchdog timer reset will clear the BSEL bit

(FCF.0) but will not change the SWR bit (FCF.1) and therefore will not changethe banking of the lower 8 kB of user code memory space.

The state of the SWR and BSEL bits after different types of resets is shown inBelow table. This results in the code memory bank selections as shown.

Reset source SWR bit result(FCF.1)

BSEL bit result(FCF.0)

addresses from0000h to1FFFh

addresses above1FFFh

External reset 0 0 Bootcode (in Block 1) User code (in Block 0)

Power-on reset

Watchdog reset x 0 Retains state of SWR bit. If SWR,BSEL = 00 then usesBootcode.If SWR, BSEL = 10then usesuser code.

Brown-out detectreset

Retains state ofSWR bit. If SWR,BSEL = 00 then usesBootcode.If SWR, BSEL = 10then usesuser code.


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Software reset 1 0 User code (in Block0)

Data RAM memory

The data RAM has 1024 bytes of internal memory. The device can also addressup to 64 kB for external data memory.

Expanded data RAM addressing

The P89V51RB2/RC2/RD2 has 1 kB of RAM.

The device has four sections of internal data memory:

1. The lower 128 bytes of RAM (00H to 7FH) are directly and indirectly

addressable.

2. The higher 128 bytes of RAM (80H to FFH) are indirectly addressable.3. The special function registers (80H to FFH) are directly addressable only.4. The expanded RAM of 768 bytes (00H to 2FFH) is indirectly addressable bythe move external instruction (MOVX) and clearing the EXTRAM bit.

Since the upper 128 bytes occupy the same addresses as the SFRs, the RAMmust be accessed indirectly. The RAM and SFRs space are physically separateeven though they have the same addresses.

AUXR - Auxiliary register (address 8EH) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - - - - - - EXTRAM AO

AUXR - Auxiliary register (address 8EH) bit description

Bit Symbol Description

7 to 2 - Reserved for future use. Should beset to 0 by user programs.

1 EXTRAM

Internal/External RAM access usingMOVX @Ri/@DPTR.When 0, core attempts to access


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internal XRAM with addressspecified in MOVX instruction. Ifaddress supplied with thisinstruction exceeds on-chipavailable XRAM, off-chip XRAM isgoing to be selected and accessed.When 1, every MOVX

@Ri/@DPTR instruction targetsexternaldata memory by default.

0 AO ALE off: disables/enables ALE. AO= 0 results in ALE emitted at a

constant rate of12 the oscillatorfrequency. In case of AO = 1, ALEis active only during a MOVX orMOVC.

When instructions access addresses in the upper 128 bytes (above 7FH), the

MCU determines whether to access the SFRs or RAM by the type of instructiongiven. If it is indirect, then RAM is accessed. If it is direct, then an SFR isaccessed. See the examples below.Indirect Access:

MOV@R0, #data; R0 contains 90H

Register R0 points to 90H which is located in the upper address range. Data in#data is written to RAM location 90H rather than port 1.Direct Access:

MOV90H, #data; write data to P1Data in #data is written to port 1. Instructions that write directly to the addresswrite to the SFRs.To access the expanded RAM, the EXTRAM bit must be cleared and MOVXinstructions must be used. The extra 768 bytes of memory is physically locatedon the chip and logically occupies the first 768 bytes of external memory(addresses 000H to 2FFH).

When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVXinstruction in combination with any of the registers R0, R1 of the selected bank orDPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7

(RD), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in thefollowing example.

Expanded RAM Access (Indirect Addressing only):

MOVX@DPTR, A DPTR contains 0A0H

DPTR points to 0A0H and data in A is written to address 0A0H of the expanded


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RAM rather than external memory. Access to external memory higher than 2FFHusing the MOVX instruction will access external memory (0300H to FFFFH) andwill perform in the same way as the standard 8051, with P0 and P2 asdata/address bus, and P3.6 and P3.7 as write and read timing signals.

When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to thestandard 8051. Using MOVX @Ri provides an 8-bit address with multiplexeddata on Port 0.

Other output port pins can be used to output higher order address bits. Thisprovides external paging capabilities. Using MOVX @DPTR generates a 16-bitaddress. This allows external addressing up the 64 kB. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low order eightaddress bits (DPL) with data.

Both MOVX @Ri and MOVX @DPTR generates the necessary read and write

signals (P3.6 - WR and P3.7 - RD) for external memory use. Table 9 showsexternal data memory RD, WR operation with EXTRAM bit.

The stack pointer (SP) can be located anywhere within the 256 bytes of internalRAM (lower 128 bytes and upper 128 bytes). The stack pointer may not belocated in any part of the expanded RAM.

External data memory RD, WR with EXTRAM bit

[1] Access limited to ERAM address within 0 to 0FFH; cannot access 100H to

02FFH.


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Internal and external data memory structure.

Dual data pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1determines which of the two data pointers is accessed. When DPS = 0, DPTR0 isselected; when DPS = 1, DPTR1 is selected. Quickly switching between the twodata pointers can be accomplished by a single INC instruction on AUXR1 (seebelow figure)


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Dual data pointer organization.

AUXR1 - Auxiliary register 1 (address A2H) bit allocation

Not bit addressable; Reset value 00H

Flash memory In-Application Programming

Flash organization

The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. AnIn-System Programming (ISP) capability, in a second 8 kB block, is provided toallow the user code to be programmed in-circuit through the serial port. There arethree methods of erasing or programming of the Flash memory that may beused. First, the Flash may be programmed or erased in the end-user application


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by calling low-level routines through a common entry point (IAP). Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. Third, the Flash may be programmed or erased using theparallel method by using a commercially available EPROM programmer which

supports this device.

Boot block (Block 1)

When the microcontroller programs its own Flash memory, all of the low leveldetails are handled by code that is contained in Block 1. A user program calls thecommon entry point in the Block 1 with appropriate parameters to accomplish thedesired operation. Boot block operations include erase user code, program usercode, program security bits, etc.

A Chip-Erase operation can be performed using a commercially available parallel

programer. This operation will erase the contents of this Boot Block and it will benecessary for the user to reprogram this Boot Block (Block 1) with thePhilips-provided ISP/IAP code in order to use the ISP or IAP capabilities of thisdevice.

In-System Programming (ISP)

In-System Programming is performed without removing the microcontroller fromthe system. The In-System Programming facility consists of a series of internalhardware resources coupled with internal firmware to facilitate remoteprogramming of the P89V51RB2/RC2/RD2 through the serial port. This firmware

is provided by Philips and embedded within each P89V51RB2/RC2/RD2 device.The Philips In-System Programming facility has made in-circuit programming inan embedded application possible with a minimum of additional expense incomponents and circuit board area.The ISP function uses five pins (VDD, VSS, TxD, RxD, and RST). Only a smallconnector needs to be available to interface your application to an external circuitin order to use this feature.

Using the In-System Programming

The ISP feature allows for a wide range of baud rates to be used in your application,independent of the oscillator frequency. It is also adaptable to a wide range of

oscillator frequencies. This is accomplished by measuring the bit-time of a single bitin a received character. This information is then used to program the baud rate interms of timer counts based on the oscillator frequency. The ISP feature requires thatan initial character (an uppercase U) be sent to the P89V51RB2/RC2/RD2 toestablish the baud rate. The ISP firmware provides auto-echo of received characters.Once baud rate initialization has been performed, the ISP firmware will only acceptIntel Hex-type records. Intel Hex records consist of ASCII characters used torepresent hexadecimal values and are summarized below::NNAAAARRDD..DDCC


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In the Intel Hex record, the NN represents the number of data bytes in the record.The P89V51RB2/RC2/RD2 will accept up to 32 data bytes. The AAAA stringrepresents the address of the first byte in the record. If there are zero bytes in therecord, this field is often set to 0000. The RR string indicates the record type. Arecord type of 00 is a data record. A record type of 01 indicates the end-of-filemark. In this application, additional record types will be added to indicate eithercommands or data for the ISP facility.The maximum number of data bytes in a record is limited to 32 (decimal). ISPcommands are summarized in Table given below.. As a record is received by theP89V51RB2/RC2/RD2, the information in the record is stored internally and achecksum calculation is performed. The operation indicated by the record type is notperformed until the entire record has been received. Should an error occur in thechecksum, the P89V51RB2/RC2/RD2 will send an X out the serial port indicating achecksum error. If the checksum calculation is found to match the checksum in therecord, then the command will be executed. In most cases, successful reception ofthe record will be indicated by transmitting a . character out the serial port.

In-System Programming (ISP) hex record formats


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In-System Programming (ISP) hex record formats continued


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Using the serial number

This device has the option of storing a 31-byte serial number along with the length ofthe serial number (for a total of 32 bytes) in a non-volatile memory space. When ISPmode is entered, the serial number length is evaluated to determine if the serialnumber is in use. If the length of the serial number is programmed to either 00H or

FFH, the serial number is considered not in use. If the serial number is in use,reading, programming, or erasing of the user code memory or the serial number isblocked until the user transmits a verify serial number record containing a serialnumber and length that matches the serial number and length previously stored in thedevice. The user can reset the serial number to all zeros and set the length to zero bysending the reset serial number' record. In addition, the reset serial number recordwill also erase all user code.

In-Application Programming method

Several In-Application Programming (IAP) calls are available for use by an applicationprogram to permit selective erasing, reading and programming of Flash sectors,security bit, configuration bytes, and device id. All calls are made through a common

interface, PGM_MTP. The programming functions are selected by setting up themicrocontrollers registers before making a call to PGM_MTP at 1FF0H. The IAP callsare shown in Table below.


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IAP function calls


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IAP function calls continued

Timers/counters 0 and 1

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured tooperate either as timers or event counters (see Tables below).In the Timer function, the register is incremented every machine cycle. Thus, onecan think of it as counting machine cycles. Since a machine cycle consists of six

oscillator periods, the count rate is 16 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transitionat its corresponding external input pin, T0 or T1. In this function, the external input issampled once every machine cycle.When the samples show a high in one cycle and a low in the next cycle, the count isincremented. The new count value appears in the register in the machine cyclefollowing the one in which the transition was detected. Since it takes two machinecycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum

count rate is 112 of the oscillator frequency. There are no restrictions on the duty cycleof the external input signal, but to ensure that a given level is sampled at least oncebefore it changes, it should be held for at least one full machine cycle. In addition tothe Timer or Counter selection, Timer 0 and Timer 1 have four operating modesfrom which to select.


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TCON - Timer/Counter control register (address 88H) bit allocation

Bit addressable; Reset value: 00000000B; Reset source(s): any reset

TCON - Timer/Counter control register (address 88H) bit description

TCON - Timer/Counter control register (address 88H) bit description


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Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bitCounter with a fixed divide-by-32 prescaler. Figure below shows Mode 0 operation.

Timer/Counter 0 or 1 in Mode 0 (13-bit counter).

In this mode, the Timer register is configured as a 13-bit register. As the count rollsover from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input isenabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (SettingGATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulsewidth measurements). TRn is a control bit in the Special Function Register TCON(Figure). The GATE bit is in the TMOD register.The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn)does not clear the registers.Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure). There are twodifferent GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn andTLn) are used. See Figure.

Timer/Counter 0 or 1 in Mode 1 (16-bit counter).

Mode 2Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload,


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as shown in Figure . Overflow from TLn not only sets TFn, but also reloads TLnwith the contents of THn, which must be preset by software. The reload leaves THnunchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

Timer/Counter 0 or 1 in Mode 2 (8-bit auto-reload).

Mode 3

When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as

setting TR1 = 0.Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logicfor Mode 3 and Timer 0 is shown in Figure . TL0 uses the Timer 0 control bits:T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (countingmachine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0now controls the Timer 1 interrupt.Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 inMode 3, the P89V51RB2/RC2/RD2 can look like it has an additional Timer.Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching itinto and out of its own Mode 3. It can still be used by the serial port as a baud rategenerator, or in any application not requiring an interrupt.

Timer/Counter 0 Mode 3 (two 8-bit counters).

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an


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event counter, as selected by C/T2 in the special function register T2CON. Timer 2has four operating modes: Capture, Auto-reload (up or down counting), Clock-out,and Baud Rate Generator which are selected according to Table given below using T2CON(Tables below ) and T2MOD (Tables below ).

Timer 2 operating mode

T2CON - Timer/Counter 2 control register (address C8H) bit allocation

Bit addressable; Reset value: 00H


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T2CON - Timer/Counter 2 control register (address C8H) bit description

T2MOD - Timer 2 mode control register (address C9H) bit allocation

Not bit addressable; Reset value: XX000000B

T2MOD - Timer 2 mode control register (address C9H) bit description


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Capture mode

In the Capture Mode there are two options which are selected by bit EXEN2 inT2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 inT2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit.

The capture mode is illustrated in Figure below.

Timer 2 in Capture Mode.

This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit inthe IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with theadded feature that a 1- to -0 transition at external input T2EX causes the currentvalue in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2Land RCAP2H, respectively.

In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like

TF2 can generate an interrupt (which vectors to the same location as Timer 2overflow interrupt). The Timer 2 interrupt service routine can interrogate TF2 andEXF2 to determine which event caused the interrupt.

There is no reload value for TL2 and TH2 in this mode. Even when a capture eventoccurs from T2EX, the counter keeps on counting T2 pin transitions or fosc/6 pulses.Since once loaded contents of RCAP2L and RCAP2H registers are not protected,once Timer2 interrupt is signalled it has to be serviced before new capture event onT2EX pin occurs. Otherwise, the next falling edge on T2EX pin will initiate reload of


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the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequentlycorrupt their content related to previously reported interrupt.

Auto-reload mode (up or down counter)

In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter

(via C/T2 in T2CON), then programmed to count up or down. The counting directionis determined by bit DCEN (Down Counter Enable) which is located in the T2MODregister (see respective tables). When reset is applied, DCEN = 0 and Timer 2will default to counting up. If the DCEN bit is set, Timer 2 can count up or downdepending on the value of the T2EX pin.

Below figure shows Timer 2 counting up automatically (DCEN = 0).

Timer 2 in auto-reload mode (DCEN = 0)

In this mode, there are two options selected by bit EXEN2 in T2CON register. IfEXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bitupon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit valuein RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset bysoftware means.

If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt,if enabled, can be generated when either TF2 or EXF2 is 1.

Microcontrollers hardware will need three consecutive machine cycles in order torecognize falling edge on T2EX and set EXF2 = 1: in the first machine cycle pin T2EXhas to be sampled as 1; in the second machine cycle it has to be sampled as 0, and

in the third machine cycle EXF2 will be set to 1.

In the below Figure , DCEN = 1 and Timer 2 is enabled to count up or down. This modeallows pin T2EX to control the direction of count. When a logic 1 is applied at pinT2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag,which can then generate an interrupt, if the interrupt is enabled. This timer overflowalso causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timerregisters TL2 and TH2.


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When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer

will underflow when TL2 and TH2 become equal to the value stored in RCAP2L andRCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloadedinto the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution ifneeded.

Programmable clock-out

A 50 % duty cycle clock can be programmed to come out on pin T2 (P1.0). This pin,besides being a regular I/O pin, has two additional functions. It can be programmed:1. To input the external clock for Timer/Counter 2, or2. To output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHzoperating frequency.To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must becleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set tostart the timer.

In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similarto when it is used as a baud-rate generator.

Baud rate generator mode

Bits TCLK and/or RCLK in T2CON allow the UART) transmit and receive baud rates

to be derived from either Timer 1 or Timer 2 (See next Section UARTs on ). When TCLK = 0,Timer 1 is used as the UART transmit baud rate generator.

When TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLKhas the same effect for the UART receive baud rate. With these two bits, the serialport can have different receive and transmit baud rates Timer 1 or Timer 2.


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Figure below shows Timer 2 in baud rate generator mode:

Timer 2 in Baud Rate Generator mode.

The baud rate generation mode is like the auto-reload mode, when a rollover in TH2causes the Timer 2 registers to be reloaded with the 16-bit value in registersRCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2s overflow rate givenbelow:

Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate/16The timer can be configured for either timer or counter operation. In manyapplications, it is configured for timer' operation (C/T2 = 0). Timer operation is

different for Timer 2 when it is being used as a baud rate generator.

The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 inT2CON register. Note that a rollover in TH2 does not set TF2, and will not generatean interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 isin the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 externalflag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Thereforewhen Timer 2 is in use as a baud rate generator, T2EX can be used as an additionalexternal interrupt, if needed.

When Timer 2 is in the baud rate generator mode, one should not try to read or writeTH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be

accurate. The RCAP2 registers may be read, but should not be written to, because awrite might overlap a reload and cause write and/or reload errors. The timer shouldbe turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table belowshows commonly used baud rates and how they can be obtained from Timer 2.

Summary of baud rate equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin


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T2(P1.0) the baud rate is:

Baud rate = Timer 2 overflow rate / 16

If Timer 2 is being clocked internally, the baud rate is:

Baud rate = fosc

/ (16

(65536

(RCAP2H, RCAP2L)))

Where fosc = oscillator frequency

To obtain the reload value for RCAP2H and RCAP2L, the above equation can berewritten as:

RCAP2H, RCAP2L = 65536 fosc / (16 baud rate)

Timer 2 generated commonly used baud rates

UARTs

The UART operates in all standard modes. Enhancements over the standard 80C51UART include Framing Error detection, and automatic address recognition.

Mode 0

Serial data enters and exits through RxD and TxD outputs the shift clock. Only 8 bits

are transmitted or received, LSB first. The baud rate is fixed at 16 of the CPU clockfrequency. UART configured to operate in this mode outputs serial clock on TxD lineno matter whether it sends or receives data on RxD line.

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0),8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is


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stored in RB8 in Special Function Register SCON. The baud rate is variable and is

determined by the Timer12 overflow rate.

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8

data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). Whendata is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or(e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received,the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit

is ignored. The baud rate is programmable to either116 or132 of the CPU clockfrequency, as determined by the SMOD1 bit in PCON.

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0),8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact,Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in

Mode 3 is variable and is determined by the Timer12 overflow rate.

SCON - Serial port control register (address 98H) bit allocation

Bit addressable; Reset value: 00H

SCON - Serial port control register (address 98H) bit description


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SCON - Serial port control register (address 98H) SM0/SM1 mode definition

Framing error

Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. IfSMOD0 = 0, SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is setup before SMOD0 is set to 1.

More about UART mode 1

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD issampled at a rate of 16 times whatever baud rate has been established. When atransition is detected, the divide-by-16 counter is immediately reset to align itsrollovers with the boundaries of the incoming bit times.The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9thcounter states of each bit time, the bit detector samples the value of RxD. The valueaccepted is the value that was seen in at least 2 of the 3 samples. This is done fornoise rejection. If the value accepted during the first bit time is not 0, the receivecircuits are reset and the unit goes back to looking for another 1-to-0 transition. Thisis to provide rejection of false start bits. If the start bit proves valid, it is shifted into theinput shift register, and reception of the rest of the frame will proceed.The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, thefollowing conditions are met at the time the final shift pulse is generated: (a) RI = 0,and (b) Either SM2 = 0, or the received stop bit = 1.If either of these two conditions is not met, the received frame is irretrievably lost. Ifboth conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, andRI is activated.


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More about UART modes 2 and 3

Reception is performed in the same manner as in mode 1.The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, thefollowing conditions are met at the time the final shift pulse is generated: (a) RI = 0,and (b) Either SM2 = 0, or the received 9th data bit = 1.If either of these conditions is not met, the received frame is irretrievably lost, and RIis not set. If both conditions are met, the received 9th data bit goes into RB8, and thefirst 8 data bits go into SBUF.

Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. Inthese modes, 9 data bits are received or transmitted. When data is received, the 9thbit is stored in RB8. The UART can be programmed so that when the stop bit isreceived, the serial port interrupt will be activated only if RB8 = 1. This feature isenabled by setting bit SM2 in SCON. One way to use this feature in multiprocessorsystems is as follows:

When the master processor wants to transmit a block of data to one of several slaves,it first sends out an address byte which identifies the target slave. An address bytediffers from a data byte in a way that the 9th bit is 1 in an address byte and 0 in thedata byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received9th bit is 0. However, an address byte having the 9th bit set to 1 will interrupt allslaves, so that each slave can examine the received byte and see if it is beingaddressed or not. The addressed slave will clear its SM2 bit and prepare to receivethe data (still 9 bits long) that follow. The slaves that werent being addressed leavetheir SM2 bits set and go on about their business, ignoring the subsequent databytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of thestop bit, although this is better done with the Framing Error flag. When UART receivesdata in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid

stop bit is received.

Automatic address recognition

Automatic Address Recognition is a feature which allows the UART to recognizecertain addresses in the serial bit stream by using hardware to make thecomparisons. This feature saves a great deal of software overhead by eliminating theneed for the software to examine every serial address which passes by the serialport. This feature is enabled for the UART by setting the SM2 bit in SCON. In the 9 bitUART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will beautomatically set when the received byte contains either the Given address or theBroadcast' address. The 9 bit mode requires that the 9th information bit is a 1 toindicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectivelycommunicate with one or more slaves by invoking the Given slave address oraddresses. All of the slaves may be contacted by using the Broadcast address. TwoSpecial Function Registers are used to define the slaves address, SADDR, and theaddress mask, SADEN. SADEN is used to define which bits in the SADDR are to beused and which bits are dont care. The SADEN mask can be logically ANDed withthe SADDR to create the Given address which the master will use for addressingeach of the slaves. Use of the Given address allows multiple slaves to be recognizedwhile excluding others.This device uses the methods presented in below Figure to determine if a Given or


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Broadcast address has been received or not.

Schemes used by the UART to detect given and broadcast addresses when multiprocessorcommunications is enabled

Serial peripheral interface

SPI features

Master or slave operation 10 MHz bit frequency (max) LSB first or MSB first data transfer Four programmable bit rates End of transmission (SPIF) Write collision flag protection (WCOL) Wake-up from idle mode (slave mode only)

SPI description

The serial peripheral interface (SPI) allows high-speed synchronous data transferbetween the P89V51RB2/RC2/RD2 and peripheral devices or between severalP89V51RB2/RC2/RD2 devices. Figure below shows the correspondence betweenmaster and slave SPI devices. The SCK pin is the clock output and input for themaster and slave modes, respectively. The SPI clock generator will start following awrite to the master devices SPI data register. The written data is then shifted out ofthe MOSI pin on the master device into the MOSI pin of the slave device. Following acomplete transmission of one byte of data, the SPI clock generator is stopped and theSPIF flag is set. An SPI interrupt request will be generated if the SPI Interrupt Enable


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bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both set.An external master drives the Slave Select input pin, SS/P1[4], low to select the SPImodule as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is notactive and the MOSI/P1[5] port can also be used as an input port pin.CPHA and CPOL control the phase and polarity of the SPI clock. Figures below andshow the four possible combinations of these two bits.

SPI master-slave interconnection.

SPCR - SPI control register (address D5H) bit allocation

Bit addressable; Reset source(s): any reset; Reset value: 00000000B

SPCR - SPI control register (address D5H) bit description


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SPSR - SPI status register (address AAH) bit allocation

Bit addressable; Reset source(s): any reset; Reset value: 00000000B


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SPSR - SPI status register (address AAH) bit description

SPI transfer format with CPHA = 0.

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