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Ferroelectric Negative Capacitance MOSFET:
Design Framework based on Capacitance Tuning
Asif I. Khan PI: Prof. Sayeef Salahuddin
Laboratory for Emerging & Exploratory Devices (LEED) Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley, CA-94720, USA
The Team
2
PI: Prof. S. Salahuddin EECS, UC Berkeley
Collaborative PI’s: Prof. R. Ramesh MSE, UC Berkeley
Prof. C. Hu EECS, UC Berkeley
Students: Asif Khan Chun Yueng Asis Sarker EECS, UC Berkeley
MOSFET Scaling: The Negative Capacitance Approach
Negative capacitance can give S < 60 mV/decade
http://www.intel.com/technology/mooreslaw/
Moore’s Law Negative Capacitance FET
Salahuddin et al., Nanoletters 8, 405 (2008).
Experimental Evidence of Negative Capacitance:
A. Khan et al., APL 99, 113501 (2011). A. Rusu et al., IEDM 2010.
3
MOSFET Scaling: The Negative Capacitance Approach
Negative capacitance can give S < 60 mV/decade
http://www.intel.com/technology/mooreslaw/
Moore’s Law Negative Capacitance FET
Salahuddin et al., Nanoletters 8, 405 (2008).
Experimental Evidence of Negative Capacitance:
A. Khan et al., APL 99, 113501 (2011). A. Rusu et al., IEDM 2010.
4
Ferroelectric Negative Capacitance
Positive Capacitance Ferroelectric
Negative Capacitance
V C
Capacitor
According to Landau-Devonshire Theory of Ferroelectrics, Ferroelectric capacitors can give rise to negative capacitance
under certain conditions.
5
Experimental Evidence of Ferroelectric Negative Capacitance
V CDE
CFE
Substrate
Metal
DE STO
FE PZT
Metal
Khan et al. APL 99, (2011)
6
Experimental Evidence of Ferroelectric Negative Capacitance
V CDE
CFE
Negative Capacitance effect @ > 110 oC.
substrate
SrRuO3
Au
. . .
BSTO LAO
BSTO LAO
BSTO LAO
Ba0.8Sr0.2TiO3-LaAlO3 superlattice
Unpublished
LAO (2.5nm)-BSTO(7.5nm) x 10 times superlattice
100 kHz
Negative Cap limit
Superlattice
Sub 60mV/dec Negative Capacitance FET: Capacitance Tuning Perspective
Intrinsic MOSFET VG
Cox
Cs Cdrain
VD
Csource
0 V ᵠ
1||||
1 ox
Drainsources
s
g
C
CCCm
V
Subthreshold Swing, SS = m x 60 mV/dec >60 mV/dec
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Sub 60mV/dec Negative Capacitance FET: Capacitance Tuning Perspective
Ideal Switch: 0mV/decade ⇐ |CFE|=CMOS Is it possible to match CFE and CMOS over a large range of
charge densities and voltages ?
Negative Capacitance FET
VG
VD
Intrinsic MOSFET
CMOS
CFE
Cox
Cs Cdrain Csource
0V ᵠ
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Capacitance Cancellation in an NCFET
-2 -1 0 1 2
0.00
0.04
0.08Accumulation
Depletion
CM
OS (
F/m
2)
VG (V)
Strong Inversion
It may not be possible to match CFE and CMOS within the operational charge densities.
MOS Capacitance changes by almost two orders of magnitude between on and off state.
VG
VD
Intrinsic MOSFET CMOS
CFE
Cox
Cs Cdrain Csource
0V ᵠ
10
Simulation of Negative Capacitance FET Structure
Self-consistent 2D Electrostatics-1D Landau Simulation Intrinsic MOSFET: TCAD Sentaurus Simulation. Ferroelectric: 1-D Landau Simulation. PbZr0.5Ti0.5O3. Anisotropy Constants from Haun et al., Ferroelectrics 99, 63 (1989) Interlayer Metallic Electrode: To screen out non-uniformity in potential profile as well due to domain formation.
11
-2 -1 0 1 2
0.00
0.04
0.08
Case A: -CFE
Case B: -CFE
Cg (
F/m
2)
VG (V)
Case C: -CFE
Capacitance Matching in a NCFET
-4 -2 0 2 4
-0.5
0.0
0.5
Case C
Depletion
Acum
ulat
ion
Strong Inversion
Q (
C/m
2)
VG (V)
12
-2 -1 0 1 2
0.00
0.04
0.08
Case A: -CFE
Case B: -CFE
Cg (
F/m
2)
VG (V)
Case C: -CFE
Capacitance Matching in a NCFET
-4 -2 0 2 4
-0.5
0.0
0.5
Case C
Depletion
Acum
ulat
ion
Strong Inversion
Q (
C/m
2)
VG (V)
13
-2 -1 0 1 2
0.00
0.04
0.08
Case A: -CFE
Case B: -CFE
Cg (
F/m
2)
VG (V)
Case C: -CFE
Capacitance Matching Condition: Antiferroelectric Hysteresis
Antiferroelectric Hysteresis: Nominal hysteresis in exchange for
large increase in the on-current and the on-off ratio.
VDD Swing
14
-2 -1 0 1 2
0.00
0.04
0.08
Case A: -CFE
Case B: -CFE
Cg (
F/m
2)
VG (V)
Case C: -CFE
Capacitance Matching in a NCFET
-4 -2 0 2 4
-0.5
0.0
0.5
Case C
Depletion
Acum
ulat
ion
Strong Inversion
Q (
C/m
2)
VG (V)
Three different classes of FE-MOS Q-V characteristics: 1. Non-hysteretic 2. Antiferroelectic Hysteretic 3. Ferroelectric Hysteretic
15
Antiferroelectric NCFET: Optimization of FE Thickness
15
0n
m
0n
m
23
0 n
m
25
0 n
m
23
0 n
m
25
0 n
m
VDD=0.3 V LG=100nm NA=5x1017cm-3
Significant enhancement of on-current in the presence of hysteresis.
16
Antiferroelectric NC-FET: Optimization of FE Thickness
w/o FE
VDD=0.3 V Ioff = 100 nA/μm LG=100nm
On set of Hysteresis
Hysteresis>VDD
17
Antiferroelectric NC-FET: Optimization of FE Thickness
w/o FE
VDD=0.3 V Ioff = 100 nA/μm LG=100nm
Optimal tFE
18
Antiferroelectric NCFET: Performance Projection
Lg = 100 nm NA = 5x10
17 cm-3
tox = 5 A
Ioff = 100 nA/μm
Significant reduction in Vdd is possible by design optimization.
∆VDD=400 mV
19
Capacitance Tuning by Source Overlap
w/o FE
Lov=0,50nm LG=100nm Lov
CMOS
CFE
Overlap capacitance adds an VG independent capacitance in CMOS resulting in a better matching between CFE and CMOS.
20
w/o FE
Capacitance Tuning by Source Overlap
tFE=210nm LG=100nm Lov
CMOS
CFE
Overlap capacitance adds an VG independent capacitance in CMOS resulting in a better matching between CFE and CMOS.
21
Capacitance Tuning by Source Overlap
w/o FE
tFE=210nm LG=100nm
Overlap capacitance adds an VG independent capacitance in CMOS resulting in a better matching between CFE and CMOS.
Lov CMOS
CFE
22
Negative Capacitance in Scaled Devices
VG
VD
Intrinsic MOSFET
CFE
Cox
Cs Cdrain Csource
0V LG=100nm
Dotted: no FE
tFE=210nm
23
Negative Capacitance in Scaled Devices
VG
VD
Intrinsic MOSFET
CFE
Cox
Cs Cdrain Csource
0V LG=100nm
Dotted: no FE Solid: w/ FE
Matching between CFE and CMOS improves with scaling due to increased Drain coupling to the channel.
tFE=210nm
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Hysteresis Free Operation of NC-FET
25
Hysteresis free operation can be obtained by reducing the difference between on-state and depletion capacitance.
VDS=0.5V LG=100nm tTSOC=5nm
Initial Experimental Work on Negative Capacitance MOSFET
26
Crystalline STO from Prof. Droopad
Process Flow I: Crystalline FE NC MOSFET
Collaboration with C. W. Yeung & C. Hu, UCB and R. Droopad. Texas Tech U
Initial Experimental Work on Negative Capacitance MOSFET
27
SiO2
Process Flow II: Polydomain PZT MOSFET
Collaboration with C. W. Yeung & C. Hu, UCB
Conclusions
• Capacitance tuning a powerful design concept for negative capacitance FETs.
• Design parameters for NCFET optimization: FE thickness, Gate overlap.
• Negative capacitance more dominant in scaled devices.
• Effects of contact resistance, mobility degradation, domain formation etc.
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THANK YOU
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