The simple CMOS negative capacitance with improved frequency response

Boško Mrković*, Martina Ašenbrener** * Tehnoalarm d.o.o. Zagreb, Croatia

** University of Rijeka/Department of Informatics, Rijeka, Croatia E-mail: bosko.mrkovic@kr.t-com.hr, masenbrener@inf.uniri.hr

Abstract - The negative capacitance circuits are very interesting analog building blocks with many possible applications like the compensation of undesired parasitic capacitance, bandwidth enhancement of amplifiers, equalization filters design without passive inductors, etc. This paper presents a method for improving and controlling CMOS floating negative capacitance frequency response. Since the negative capacitance is generated by the simple and known negative impedance converter (NIC), the proposed method is applicable for negative inductance and resistance also.

The proposed method is simulated and verified using standard 0.35µm and 0.18µm CMOS processes.

I. INTRODUCTION

The negative capacitance circuits or negative capacitance generators (NCG) are very useful analogue building blocks, used for numerous different applications enabling:

• The improvement of existing structures, through the compensation of undesired parasitic capacitance, like bandwidth enhancement of various kind of amplifiers [6], [7], speed enhancement of some DAC architectures, improvement of ESD protection circuits [3], improvement of active inductor design [1], [4], etc.

• The design of new circuit architectures like the new compact equalization filters, new RC and LC oscillator structures etc.

There are many different possibilities for grounded or floating negative capacitance generation, mostly known for decays.

Generally, any well known negative impedance converter (NIC), which employs operational amplifiers or current conveyors, can be used. Negative capacitance generated using such an approach is accurate, with a large allowed signal swing. The disadvantages are that such an approach requires a large area and increased power, especially for floating capacitor generation, and mostly performs with poor higher frequency limit.

There are also several known simple structures which can be used as a floating NCG, like a common source amplifier with cross-coupled capacitors and source’s parallel R-C pairs [2]; or a very effective NCG known as

the relaxation generator, with cross-coupled MOSFETs, described in [3].

Although the last structure generates a negative resistance as well as a negative capacitance and performs with an inevitable noise figure and some linearity degradation, it is quite simple, offers great possibilities for improvements and control and was therefore chosen for the presented analysis and design.

II. IMPLEMENTATION

A. A Generalized Negative Capacitance

As it is mentioned previously, a simple way to generate a floating negative capacitor is by using a cross-coupled pair of transistors in order to create a positive feedback.

v1

M1 M2

C

I I

Zeq

i1 i2

v2

Figure 1. The simple negative capacitance generator

The positive feedback loop formed by transistors M1 and M2 makes a difference in the output currents to have an opposite polarity to the differential voltage. Thus, the equivalent output impedance has a negative value.

From the small signal analysis of the proposed circuit, after disregarding the channel length modulation, the equivalent impedance is given by

( )GSm

GSmequ sCg

CCsg

sCZ

−++−= 21 (1)

As long as f << fT, where fT is the unity gain frequency or transition frequency of the used MOSFETs, the equivalent impedance can be approximated by

( )T

m

GSequ ff

Cg

CC

sCZ <<+−−≈ ,

21 (2)

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Equivalent impedance at the output is the complex impedance with reactive and resistive parts, and it is easy to notice that a similar circuit, with a shorted capacitor C, can be used for negative resistance generation. Further modification proposed in [5] enables a negative inductance generation as well.

Figures 2 (a) and (b) show the schematic diagrams of a similar negative resistance circuit and a negative inductance circuit [5], respectively.

v1

v1

M1

M1 C1 C1

M2

M2

I I I

C

Zeq

Zeq

i1

i1

i2

i2v2

v2

(a) (b)

Figure 2. Schematic diagrams of (a) negative resistance and (b) negative inductance generators

B. A Simplified Implementation Model

The previously described NCG is loaded with the rest of the circuits where it acts as a negative capacitor, and all characteristics, including the possible stability issues, hardly depend on the implementation details. For further analysis, such an undefined load will be replaced by a dynamic one, with MOSFETs shown as current sources, for simplicity. A corresponding schematic diagram is shown by Figure 3.

M1 M2

I

I

I

I

C

Zeq

Figure 3. The simple NCG with load

Figure 4. Negative capacitance and complex impedance, the simple NCG model

Assuming that MOSFETs are ideal, without any parasitic capacitance and with a realistic but constant transconductance gm, an equivalent negative capacitance with an equivalent complex impedance are shown in Figure 4. As expected, the capacitance value C defines the value of the equivalent negative capacitance, while the transconductance value defines the negative resistance value.

The capacitor C and the MOSFET’s transconductance define the higher frequency limit for the used NCG as well.

Figure 5 shows the equivalent negative capacitances for different capacitor C values. In the ideal case, only the sign would differ.

Figure 5. Negative capacitance versus input capacitance value, model

The capacitance C also defines the frequency range. To increase the frequency range of the proposed NCG it is necessary to decrease the capacitance C value. Usually this is not acceptable in the real design.

There is another way to enlarge the frequency range. The currents and the dependent transconductance should be increased. For the assumed ideal MOSFETs, replaced by dependent sources with constant transconductance, the current I value changes do not produce any effect. Nevertheless, the transconductance changes perform as expected, as shown by Figure 6.

Figure 6. Negative capacitance versus transconductance, model

The high frequency limit of the proposed NCG depends on the current I value and depending MOSFETs transconductance. This enables an easy control of the high

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frequency limit which allows an easy calibration and frequency control for some RC oscillator classes.

The equivalent complex impedance, with all its parts, is shown in Figure 7.

Figure 7. Negative capacitance and complex impedance versus transconductance, model

III. VERIFICATION

A. General Information

The circuits were designed, simulated and verified using NCSU CDK, which is a collection of MOSIS fabrication processes available for public download, and ngspice v22 simulator. The technologies used were tsmc_02, tsmc_03 and tsmc_04_4m. Simulations were made across all process corners and the temperature range for all cases.

The proposed design can be processed in any available mixed–signal technology with simple re-calculations and optimizations due to the specific characteristics of the technology.

B. Physical Implementation

Figure 8. Negative capacitance generator

Figure 8 shows the real implementation of the proposed NCG with ideal current sources replaced by current source and sink mirrors. The implemented power-down circuitry enables a parallel connection between multiple NCGs. Such parallel connection is actually a transistors W/L ratios multiplication and is equivalent to

the previously described transconductances multiplication. To enable fine control, the proposed NCG is biased by IB current.

Figure 9. Negative capacitance and complex impedance, model and real circuit, comparison

Figure 9 shows the comparison between model’s and the realistic NCG’s behaviors. The main difference is caused by the real transistors parasitics, especially by the CGS. It is inevitable but can be compensated by an increased capacitance C value.

Figure 10. Negative capacitance versus transconductance

Figure 10 shows the high frequency limit characteristics for a different number of parallel NCGs shown by Figure 8. One should notice that a parallel combination of simple NCGs significantly increases the frequency range for almost a decade.

Unlike the previously used NCG model, the real circuit allows a high frequency limit control by current.

Figure 11. Negative capacitance versus current

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Figure 11 shows the high frequency limit characteristics for different currents, controlled by the IB.

Figure 12. Controled NCG, block diagram

Figure 12 shows the final negative capacitance circuit, with high frequency limit controllable by a bias current and transconductances. Control with the bias current is fine and accurate, with a simple IDAC; the transconductance control is coarse, with a controlled number of connected simple NCGs.

Figure 13 shows the frequency characteristic of the proposed NCG, generated with 3 coarse ranges. In order to keep the picture clear only 3 fine values per range are shown.

Figure 13. Negative capacitance versus transcoductance and current

IV. CONLUSION

A simple method for increasing and controlling the high frequency limit for the simple NCG is presented. The significantly increased frequency range and the accurate high frequency limit control allow an efficient design of some RC oscillator classes.

The same method can be used for the value and the frequency limit control of the negative resistance and the frequency range of the negative inductance shown in Figure 2.

REFERENCES

[1] M. M. Reja, K. Moez, I. Filanovsky, “A wide frequency range

CMOS active inductor for UWB bandpass filters”, 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009.

[2] F. Aznar, S. Celma, B. Calvo, D- Digon, “A fully integrated inductorless AGC amplifier for optical gigabit ethernet in 0.18µm CMOS”, IEEE International Symposium on Industrial Electronic, 2008., pp. 1662-1667

[3] S. Gallal, B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18µm CMOS technology”, IEEE J. Solid-State Circuits vol. 39, Dec. 2004., pp. 2389-2396

[4] C. Andriesei, L. Goraş, F. Temcamani, B. Delacressonniere, “Improved RF CMOS Active Inductor With High Self Resonant Frequency”, IEEE International Conference on Electronics, Circuits, and Systems, Athens, 2010.

[5] K. Yoo, M. M. Abdul-Latif, G. Han, E. Sánches-Sinencio, “Negative Impedance Circuit and Its Application to Inductorless Resonant Oscillators”, Proc Int SOC Conference, 2007., pp. 13-16

[6] K. Yoo, D. Lee, G. Han, S. M. Park, W. S. Oh, “A 1.2V 5.2mW 40dB 2.5-Gb/s Limiting Amplifier in 0.18µm CMOS Using Negative-Impedance Compensation,” in Proc. ISSCC, San Francisco, CA, Feb. 2007, pp.56-57.

[7] Jin-Sung Youn, Hyo-Soon Kang, Myung-Jae Lee, Kang-Yeob Park, Woo-Young Choi, “High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector”, IEEE Photonics Technology Letters, VOL. 21, NO. 20, Ooctober 15, 2009., pp.1553-1555

[8] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design”, 2nd Edn., Oxford University Press, 2002.

[9] B. Razavi, “Design of Analog CMOS Integrated Circuits”, International Edition, McGraw-Hill, 2001.

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