FE8113 ”High Speed Data Converters”

Part 2: Digital background calibration

Gain errors and calibration

- Introduction to gain error calibration and test signal injection in pipelined ADCs

Pipelined ADC

backendStage 1

2

Y

Vin

ε1

2

- εbe

1 1( ) 2 2in inV V

12be

1 12 2 2in be in beY V V

Digital error correction

in

out

2

ref2

ref refref

ref

2

ref

2

ref

ref

Stage output:

Backend MSB:

Sum:

0 0 0 1 1

0 1 1 0 1

00 01 01 10 11

offset

in

out

4

ref4

ref2

ref2

ref refref

ref

2

ref

2

ref

ref

Stage output:

Backend MSB:

Sum:

00 00 01 01 10 10

0 1 0 1 0 1

00 01 01 10 10 11

offset

Offset translates directly to distortion at the output

Offset within +/-Vref/4 corrected by redundant bits

1 bit, no error correction: 1.5 bits, error correction:

MDAC gain error

+

+-

-

A

Cr

Cr

inV+

-outV+

-

Cf

Cf

VCM

+

+-

-

A

Cf

Cf

Cr

Crrefd V

+

-outV+

-

xv

xv

Cr Cf in CM r f

Cr Cf in CM r f

Q Q V V C C

Q Q V V C C

ref x r out x f in CM r f

ref x r out x f in CM r f

d V v C V v C V V C C

d V v C V v C V V C C

φ1:

φ2:

MDAC gain error

2 22 2 2out in ref in ref

d A dV V V V V Ge

A

+

+-

-

A

Cf

Cf

Cr

Crrefd V

+

-outV+

-

xv

xv

φ2:

out outref r out f in r f

V Vd V C V C V C C

A A

12 2

2 21out in ref in ref

AV V d V V d V

AA

in

out

4

ref4

ref2

ref2

ref refref

ref

2

ref

2

ref

ref

Pipeline with gain error

backendStage 1 Ge1

2

Y

Vin

Vout_1_idealVin_be

Pipeline with gain error

1 12 2 1in beY V Ge

backendStage 1

Ge1

2

Y

Vin

Vout_1_idealVin_be

ε1

2

- εbe

Calibration of gain error

1 1 1 12 2 1in beY V l Ge l

1 11

12 in bel Y V l

Ge

backendStage 1

Ge1

2

Y

Vin

Vout_1_idealVin_be

ε1

2

- εbe

l1

Calibration of multiple stages

Vin

Y

Calibrated backend

Stage 1 Stage 2 backendGe1 Ge2

l2l1

222

1 2 1 21 2

1 1, 2 in bel l Y V l l

Ge Ge

Calibration, alternative implementation

Vin

Y

Stage 1 Stage 2 backendStage 2

1

1

Ge1 2

1

Ge Ge1

1

1N

i iGe

(Digital scaling factors between the stages are not shown here)

Test signal injection

backendStage 1 Ge1

2

Y

Vin

Vout_1_idealVin_bets

l1

1/4

Stage transfer function (TF)

in

out

4

ref4

ref2

ref2

ref refref

ref

2

ref

2

ref

ref

Stage TF with Vref/4 test signal

in

out

4

ref4

ref2

ref2

ref refref

ref

2

ref

2

ref

ref

Stage TF, modified test signal, tsmod

in

out

4

ref4

ref2

ref2

ref refref

ref

2

ref

2

ref

ref

MDAC, holding phase, test signal injection

+

+-

-

A

Cf

Cf

Cr

Crrefd V

+

-outV+

-

xv

xv

Cts

Cts

ts

ts

mod22out in ref

dV V V ts Ge

Test signal at ADC output

1 1 1 1 mod 1 1

12 2 1 1

4in beY V l Ge l ts Ge l

backendStage 1

Ge1

bes1

s1+be

Y

Vin

ε1

2

- εbe

2

ts

1/4

1/4 -mod

l1

Measuring error energy

backendStage 1 Ge1

2

Y

Vin

Vout_1_idealVin_bets

l1

1/4

Correlator

C

Correlate over a blocklength (BL) of millions of samples

1 1 1 1 mod 1 1

mod 1 1

12 2 1 1

4

11

4

in beBL

BL

C V l Ge l ts Ge l ts

C ts ts Ge l

Error energy at the output, use this to adjust digital coefficient

List of Papers Test signal injection

E.Siragusa, I.Galton: “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC” Skip (& fill)

U-K.Moon, B-S.Song: “Background Digital Calibration Techniques for Pipelined ADC’s” E.B.Blecker et.al: “Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a

Simplified Queue” Slow-but accurate parallel ADC

S.R.Sonkusale et.al: “Background Digital Error Correction Technique for Pipelined Analog-Digital Converters”

X.Wang et.al: ”A 12-bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background Calibration”

J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters”

Reference voltage scaling J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background

Calibration” S.Sonkusale, J.Van der Spiegel: “Mixed-Signal Calibration of Pipelined Analog-Digital Converters”

Comparator Dithering A.Gines et.al: “Full Calibration Digital Techniques for Pipeline ADCs” J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined ADCs” J.Li et.al: “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy”

Others A.Abdelatty, K.Nagaraj: “Background Calibration of Operational Amplifier Gain Error in Pipelined A/D

Converters” K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC” B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification” Y.Chiu et.al: “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital

Converters”