Fault tolerant and online testability

Fault Tolerant and Online Testability in Reversible Logic

Synthesis

Sajib Kumar MitraDepartment of Computer Science and Engineering

University of [email protected]

mailto:[email protected]

Overview

• Background StudyReversible Logic Fault Tolerant MethodOnline Testability

• Online Testable Fault Tolerant Circuit• Full Adder Circuit

Existing DesignProposed Design

• Performance Analysis• About Authors• Conclusion

Reversible Logic

• Unique mapping between input and output vectors which governs to have same number of input-output lines of any reversible circuit

• Recovers heat dissipation unlikely irreversible logic and uses low power CMOS technology

• Feedback and Fan-out are not allowed• Single unit able to compute more than one

operation

Reversible Logic (cont…)

Reversible Circuit

I1

I2

I3

In

O1

O2

O3

On

An (n x n) Reversible Circuit


Reversible Circuit

I1

I2

I3

In

O1

O2

O3

On

Unique mapping of Reversible Circuit

O1

O2

O3

.

.

.On

Output VectorOutput Vector

I1I2I3...In

Input VectorInput

Vector


I1

I2

I3

In

O1

O2

O3

On

Gat

e 1

Gat

e 2

Gat

e 3

.

.

.

Gat

e S

An (n x n) Reversible Circuit Architecture


Reversible EX-OR operation and 2x2 Feynman Gate

FGA

B Q=A B

P=A

OU

TP

UT

VE

CT

OR

(P

, Q

)

3

2

1

0

2

1

INP

UT

VE

CT

OR

(A

, B

)

0

3

(a) Feynman Gate (b) Unique Mapping between Input and Output

Vector


Popular 3x3 Reversible Gates

F2GA

BC

A

A C

A B

(c) Feynman Double Gate

PGA

BC

AA B

AB C

(a) Peres Gate

FRGA

BC

A

A’C AB

A’B AC

(e) Fredkin Gate

TGA

BC

A

AB C

B

(b) Toffoli Gate

NFTA

BC

AC’ B’CAC’ BC

A B

(d) New Fault Tolerant Gate


4x4 Reversible Gates

D

ABC

P = AQ = R = A B CS = (A B)C AB D

MTSG A B

D

ABC

P = AQ = A’C’ B’R = A’C’ B’ DS = ( A’C’ B’)D AB C

ABC

P = A

D

Q = A BR = AB CS = AB’ D

MIG TSG

(a) Modified IG Gate (b) TSG Gate

(c) Modified TSG Gate

Reversibility prevents Bit Loss but not able to detect Bit

Error or Fault in Circuit

Fault Tolerant Method

Bit Error means the alteration of the value of output bits because of internal fault of digital circuit.

Input Output

A B A A B

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

FG0

1

0

(a) Reversible EX-OR Operation

0

What is the meaning of Bit Error?

Bit Error in Reversible Circuit

Fault Tolerant Method (cont…)

Bit Error means the alteration of the value of output bits because of internal fault of digital circuit.

Input Output

A B A A B

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0

FG0

1

0

(a) Reversible EX-OR Operation

0

What is the meaning of Bit Error?

Bit Error in Reversible Circuit


Preserves same parity between Input and Output vectors over one to one mapping of reversible circuit

Reversible Circuit

I1

I2

I3

In

O1

O2

O3

On

EV

EN

Par

ity

EV

EN

Par

ity

Parity Preservation of Reversible Circuit

Reversible Circuit

I1

I2

I3

In

O1

O2

O3

OnO

DD

Par

ity

OD

D P

arit

y


Let, Iv and Ov are input and output vectors of a reversible circuit, so the relation is Iv↔Ov.

But to be a Reversible Fault Tolerant circuit, itself must preserve following equation:

where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}

nn OOOIII 2121

Input Parity = Output Parity


Parity Preservation over reversibility between Input and Output vectors can be realized from the Truth Table of Fredkin Gate as shown below:

Fredkin Gate and Corresponding Truth Table

Input Output

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 0 1

1 1 1 1 1 1

A

BC

P=A

R=A’C AB

Q=A’B ACFRG


Input Output

A B C P Q R

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 0 1

1 1 1 1 1 1

A

BC

P=A

R=A’C AB

Q=A’B ACFRG

Fredkin Gate and Corresponding Truth Table

RQPCBA

Now Verify the following equation:


1

01

1FRG 1

0EV

EN

EV

EN

Fault detection of FRG gate

RQPCBA

Verify the following equation:

1

01

1FRG 1

1EV

EN

OD

D

Fault exist in CircuitNo Fault exist in Circuit


But the minimum dimension of Fault Tolerant gates is 3. Why?

Finally Reversible Gate which preserves same parity between input and output vectors is called Fault Tolerant Gate or Parity Preserving Gate

A A’

Input Output

A A’

0 1

1 0

1x1 Reversible Gate Never be a Fault Tolerant Gate

NOT operation


But the minimum dimension of Fault Tolerant gates is 3. Why?

Input Output

A B P Q

0 0 0 0

0 1 0 1

1 0 1 0

1 1 1 1

2x2 Reversible Gates have no any significance as Fault Tolerant Gate

2x2Reversible

Gate

A

B

A

B

Input Output

A B P Q

0 0 0 0

0 1 1 0

1 0 0 1

1 1 1 1

Input Output

A B P Q

0 0 1 1

0 1 1 0

1 0 0 1

1 1 0 0

Input Output

A B P Q

0 0 1 1

0 1 0 1

1 0 1 0

1 1 0 0

2x2Reversible

Gate

A

B

B

A

2x2Reversible

Gate

A

B

A’

B’

2x2Reversible

Gate

A

B

B’

A’


A

BC

P=A

R=A’C AB

Q=A’B ACFRG

(b)

F2GA

BC

A

A C

A B

(a)

NFTA

BC

Q=AC’ B’CR=AC’ BC

P=A B

(c)

Existing 3x3 and 4x4 Fault Tolerant Gates

ABC

P = A

D


MIG

(d)

A

B

C

B C D

D

PPHCG B C AB D AC D A

(e)

Online Testability

• Built-In Self Testing method• Detects bit-error at outputs of any circuit in run

time• Reversible gates able to adopt testability feature

by deducing output and corresponding input bits• To be online testable an (n x n) reversible gates

must preserve the following properties:

where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}

121 nnn OOOIO

Online Testability (cont…)

F2GA

BC

U=A

W=A C

V=A B

WO

BCBAAC

VUCO

Let

3

3

,

To be online testable an (n x n) reversible gates must have the following properties:

121 nnn OOOIO

3x3 F2G is not online Testable Gates

But F2G can be Testable by deducing extra an input and corresponding output line.


F2GA

BC

A

A C

A BTestable F2G

A

BC

U=A

P Q=P A B C

V=A BW=A C

QO

CBAPCABAAP

WVUPO

Let

3

3

,

To be online testable an (n x n) reversible gates must have the following properties:

121 nnn OOOIO

Testing OutputTesting Input


Testable F2G

A

BC

U=A

P Q=P A B C

V=A BW=A C

Testable F2G

1

00

U=1

0

V=1W=1Q=1

Verification of Testable F2G at Runtime

QO

WVUPO

Let

3

3

11110

,


Testable F2G

A

BC

U=A

P Q=P A B C

V=A BW=A C

Testable F2G

1

00

U=1

0

V=1W=0Q=1


QO

WVUPO

Let

3

3

00110

,


Testable F2G

A

BC

U=A

P Q=P A B C

V=A BW=A C

Testable F2G

1

00

U=1

0

V=1W=0Q=1


Testable R2

D

EF

X=D

R S=R D E F

Y=E

Z=F

0

:

R

WF

VE

UD

Assignment


Testable F2G

ABC0

Testable R2

Q 0 S

XYZ

UVW

""

""

ErrorBitelse

ErrorBitNOthenSQIf

Testable F2G

A

BC

U=A

P Q=P A B C

V=A BW=A C

Testable R2

D

EF

X=D

R S=R D E F

Y=E

Z=F


Testable Reversible

F2G

ABCPR

Q

XYZ

S

Testable F2G

ABCP

Testable R2

Q R S

XYZ


Testable Reversible

Cell(TRC)

ABCPQ

R

XYZ

S

Operational Outputs

Testing OutputsTesting Inputs

(Constant Value)

Operational Inputs

TRC is a Cascading Block not Gate


Testable Reversible

Cell(TRC)

I1I2I3

In+2

O1O2O3

On+2

Conversion of nxn Reversible Gate into (n+2)x(n+2) reversible Cell

DeducibleTestable

GateDR

I1I2I3

In+1

O1O2O3

On+1

nxn Reversible

GateR

I1I2

In

O1O2

On

Testable R based on following Law:

121 nnn OOOIO

Testable Reversible Cell by using Cascading Attachment

Reversible Fault Tolerant Full Adder Circuit

• Full Adder circuit produces Sum and Cout as following equations respectively:

• Full Adder can be realized by using only one MTSG gate as follows:

ABCBAC

CBASum

inout

in

)(

D

ABC

P = AQ = R = A B CS = (A B)C AB D

MTSG A B

0

ABCin A B Cin

(A B)Cin AB

MTSG

Reversible Fault Tolerant Full Adder Circuit (cont…)

0

ABCin A B Cin

(A B)C AB

MTSG

Pros o Garbage = 2o Gate = 1o Quantum Cost = 6

Cons Neither Fault Tolerant nor Online testable

You have to make Fault Tolerant and Online Testable circuit by using fault Tolerant Gates. So

start now…

Existing Fault Tolerant Fault Tolerant Adder Circuit

By using MIG…

ABC

P = A

D


MIG

ABCD G

MIGSum

MIGCin

CoutG

G

Design is Fault tolerant but uses higher dimensional reversible Gates

To make online testable, circuit has to increase an extra input-output line

Proposed Design of Fault Tolerant Full Adder

Uses 3x3 Fault Tolerant gates Easily adoptable to online testable full adder Minimum number of Garbage, 3 Preferable for Carry Look Ahead adder

CinFRG

F2GF2G

F2G

0

A

B

0

G

G

GA B Cin

AB BCin ACin

Proposed Design of Online Testable Fault Tolerant Full Adder

F2GTRC

PPIRC

FRGTRC

PPIRC

F2GTRC

PPIRC

01

01

01

TESTING INPUT

1 1 1

e

Cout S

a3 a2 a1

BLOCK ERROR TESTING OUTPUT

F2GTRC

PPIRC

01

1

a4

0

A

B0

0

Cin

Performance Analysis

Fault Tolerant

Full Adder

Total Gates Total

Garbage

Quantum Cost

3x3 4x4

Proposed [b]

4 0 3 11

Existing [a] 0 2 3 14Cin

FRG

F2GF2G

F2G

0

A

B

0

G

G

GA B Cin

AB BCin ACin

(b)

ABCD G

MIGSum

MIGCin

CoutG

G

(a)

Table 1: Comparison between proposed and existing design

About Author

Ahsan Raja Chowdhury received his B.Sc .and MS degrees in Computer science and Engineering from the University of Dhaka, Bangladesh, in 2004 and 2006, respectively. He worked with the Department of Computer Science and Engineering, Northern University, Bangladesh, from 2004 to 2007 as faculty member. He is the faculty member of the Department of Computer Science and Engineering,

Sajib Kumar Mitra is an MS student of Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interests include Electronics, Digital Circuit Design, Logic Design, and Reversible Logic Synthesis.

Md. Faisal Hossain has completed his undergraduate from Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interest includes Logic Design, especially Reversible Logic Design.

Thanks To All

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Fault tolerant and online testability