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Title: Fault Characterization, Testability Issue and Design for
Testability of Complementary Pass Transistor Logic
Circuits
Authors: Mohammad Faisal *
Abdul Hasib+
A. B. M. H. Rashid*
*Affiliation: Department of Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology
Dhaka-1000. Bangladesh
E-mail: [email protected], [email protected]
+Affiliation: Institute of Information and Communication Technology,
Bangladesh University of Engineering and Technology, Dhaka-
1000, Bangladesh.
E-mail: [email protected]
Contact: Dr. A.B.M. Harun-ur Rashid
Associate Professor
Department of Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology
Dhaka-1000, Bangladesh
Telephone: 880-2-9355048
Fax: 880-2-8613026
E-mail: [email protected]
2
Fault Characterization, Testability Issue and Design for
Testability of Complementary Pass Transistor Logic Circuits Mohammad Faisal*, Abdul Hasib+, and A.B.M.H. Rashid*
*Department of Electrical and Electronic Engineering, Bangladesh University of
Engineering and Technology, Dhaka-1000, Bangladesh
+Institute of Information and Communication Technology, Bangladesh University of
Engineering and Technology, Dhaka-1000, Bangladesh
Abstract: Testability analysis of basic and complex logic gates employing
complementary pass transistor logic (CPL) under various single stuck faults is
investigated. Results show that all stuck-on faults, bridging faults and more than 90%
stuck-at faults in the basic CPL gates are only detectable by current monitoring
generally known as IDDQ testing. It is also shown that all stuck-open faults in the basic
CPL gates are only detectable by logic monitoring using appropriate two-pattern test.
Testability analysis of CPL full-adder under single stuck-on fault shows that stuck-on
fault on all the MOS transistors of the SUM logic and the CARRY logic circuit can be
detected by signal source current monitoring with appropriate test vectors. Similarly
stuck-at fault on all MOS transistors of full-adder can be detected by current
monitoring only, and stuck-open fault on all MOS transistors of full-adder can be
detected by appropriate two-pattern test. It is concluded that signal source current
monitoring (IDDQ testing) is the best method for fault detection in CPL circuits and
gives more than 94% fault coverage for stuck-at, stuck-on and bridging faults and logic
monitoring gives 100% fault coverage for stuck-open faults. Finally, a current
monitoring circuit in CPL VLSI chip has been proposed.
3
Index Terms: CMOS, CPL circuits, Design for testability, Fault model, Fault
detection, Full-adder, IDDQ testing, Testability analysis, VLSI.
1. INTRODUCTION: Complementary pass transistor logic (CPL) is a new family of
advanced differential CMOS logic that has much higher speed and lower power
consumption compared to conventional static CMOS logic [1]. The main concept
behind the CPL is the use of an nMOS pass transistor network for logic organization
and elimination of the pMOS latch. CPL consists of complementary inputs/outputs, an
nMOS logic network and CMOS output inverters. Other attractive features of this
family are: lower delay, less number of transistors and less silicon area compared to
conventional CMOS circuits for the same functionality. Arbitrary Boolean functions
can be constructed from the pass transistor network by combining the basic circuit
modules: an AND/NAND module, an OR/NOR module, and a XOR/XNOR module.
The powerful logic functionality of CPL due to the multilevel pass transistor network
realizes complex Boolean functions efficiently with a small number of nMOS
transistors, thus further reducing area and delay time. M. Avci et. al. [2] have presented
a general and effective CPL design method for pipeline circuits that have enhanced
performance over conventional CMOS circuits in terms of silicon area, speed and
reduced power dissipation. The group of Yano [1] has fabricated a 3.8 ns CMOS
16×16-b multiplier using CPL, having a speed more than twice as fast as conventional
CMOS due to lower input capacitance and higher logic functionality. Abu-Khater et. al.
[3] have shown that full-adder constructed with CPL provides a power saving of 50%
compared to conventional CMOS full-adder and CPL implementation of a Booth
encoder for multiplier provides 30% power saving and 15% speed improvement
compared to static CMOS implementation. A novel low-power 32-b adder has been
4
designed using conditional sum adder (CSA) architecture and CPL-like logic structure
that outperforms several architectures using CMOS circuit styles in terms of power and
speed [4]. Besides many authors have fabricated CPL circuits and shown the
improvement in both speed and power compared to conventional CMOS [5]-[7].
However, the fault characterization, testability issue and design for testability (DFT) of
CPL circuits have not been presented yet.
The high-performance integrated circuits to day contain millions of transistors on a
single chip [8]. It is essential to adopt a design-for-testability (DFT) approach in
designing such complex integrated circuits in order to facilitate testing and save cost
[9]. In our previous papers, we have reported the preliminary study on testability issue
of basic CPL circuits [10], [11]. This paper reports the rigorous analytic and simulation
results on testability of the basic CPL gates and CPL full-adder circuits for stuck-on,
stuck-open, stuck-at and bridging faults and design for testability of CPL circuits. First
a qualitative analysis of the fault behaviour is performed by fault simulation. The
qualitative analysis and SPICE simulation results show that for CPL circuits steady
state supply current testing (IDDQ testing) gives a very wide range of fault coverage.
Finally, a technique to implement IDDQ testing in CPL circuits is proposed. The paper
illustrates as follows: in section-2, a theoretical study describing the fault behaviour of
the basic CPL circuits is developed. The testability issue of CPL full-adder circuit is
investigated in section-3, and then a technique to implement the IDDQ testing in CPL
circuits is illustrated in section-4.
2. FAULT ANALYSIS OF BASIC CPL CIRCUITS: Fig.1 shows the basic CPL
circuits. The behaviour of these circuits for various single stuck-on, stuck-open, stuck-
5
at and bridging faults have been analyzed in the following section. The fault strength
for all cases was varied from 0 to 20 kΩ. Normal operating current was 5 pA.
2.1: Stuck-on fault: If a transistor is permanently ON irrespective of the input signal
applied at the gate then it is referred to as stuck-on. This fault may occur when the
source and drain terminals of a transistor are short-circuited due to mask misalignment
or excessive source-drain out diffusion. This type of fault can be modeled by placing a
resistance Rf that indicates fault strength in parallel with the transistor between the
respective terminals.
Fig.2 shows the fault simulation circuit of stuck-on fault on MOS M1 in CPL AND gate
with test vector [A=1, B=0]. The tests vectors [A=0, B=0], [A=0, B=1] and [A=1,
B=1] produce correct logic and no significant current flows. However, when vector
[A=1, B=0] is applied, M2 turns ON and a huge current flows through Rf and M2. In
fault-free circuit, the vector [A=1, B=0] would have pulled the output node down to the
ground level i.e. would produce correct logic. In the faulty circuit, the output voltage
becomes,
IHonfonout VRRRV )( += ……………..(1)
where Ron is the ON resistance of M2 and VIH is the input high logic level at A. When
fault strength is maximum i.e. Rf approaches zero, Vout approaches VIH and when Rf is
very large Vout approaches 0 V. Now since Vout can attain any value from 0 to VIH,
hence, the stuck on fault at M1 cannot be detected by logic monitoring. However,
Steady state current is significantly large due to the low resistance path between VIH
and ground. Steady state current is given by,
( )onfIH RRVI += …………..…(2)
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Hence, the fault can be detected by current monitoring i.e. IDDQ testing.
SPICE simulation is done to analyze the effect of stuck-on fault on all transistors of all
the basic CPL gates. Fig.3 shows the variation of the output voltage Vout and signal
current IDDQ as a function of Rf for fault on the transistor M1 of the basic CPL AND
gate with test vector [A=1, B=0]. This is in agreement with the analysis made above.
The simulation also revealed that the current under faulted condition varies from 3 mA
to 0.24 mA, whereas the normal operating current is only 5 pA. Therefore, this fault
can be detected by current monitoring. Similarly it has been found that all single stuck-
on faults in all CPL basic circuits can be detected by current monitoring applying
appropriate test vectors but no logic monitoring is possible. The result is summarized in
Table-1.
2.2: Stuck-at fault: It is assumed that this fault causes a line in the circuit to behave as
if it were permanently at logic ‘0’ or logic ‘1’. If the line is permanently at logic ‘0’ it
said to be stuck-at-0, otherwise if the line is permanently at logic ‘1’ it said to be stuck-
at-1 [12]. We have considered two types of stuck-at fault: (i) stuck-at fault between
gate and source and (ii) stuck-at fault between gate and drain. As in stuck-on fault case,
this fault is modeled by placing a resistor Rf between the gate and the source/drain
terminals of the faulty device as shown in Fig.4. This figure shows the simulation
circuit for gate to source stuck-at fault of MOS M2 of basic CPL AND gate for test
vector [A=1, B=1].
The test vector [A=0, B=1] produce correct output logic and no significant current
flows. However, when vectors [A=0, B=0], [A=1, B=1] and [A=1, B=0] are applied,
7
fault can be detected. When test vector [A=1, B=1] is applied, MOS M1 turns ON and a
short circuit current flows through Rf and M1. In a fault-free circuit this vector would
produce a high level output. In the faulty circuit the output voltage is given by,
IHonffout VRRRV )( += ……………….(3)
When fault strength is maximum i.e. Rf approaches zero, Vout approaches 0 V and
when Rf is very large Vout approaches VIH. Now since Vout can attain any value from 0
to VIH depending on Rf, hence the stuck-at fault at M2 cannot be detected by logic
monitoring. However, Steady state current is significantly large due to the low
resistance path between VIH and ground. Steady state current is
( )onfIH RRVI += ……………….(4)
Hence, the fault can be detected by current monitoring i.e. IDDQ testing.
SPICE simulation has been carried out for single stuck-at faults between gate and
source/drain terminals in all basic gates. Fig.5 shows that output current varies from
3.05 mA to 0.158 mA, whereas the normal operating current is only 5 pA. Hence the
fault is detectable by current monitoring. Similar analysis and SPICE simulations have
been performed for other gates. It is found that all stuck-at faults can be detected by
current monitoring, except for MOS M3 in AND/NAND gate and MOS M2 in
OR/NOR gate in which the gate and drain terminals have the same input variable. The
simulation results are summarized in Table-2.
2.3 Stuck-open fault: Physical defects or electromigration in aluminum conductor
may cause a MOS transistor to become permanently open and insensitive to its input
signal. To model a stuck open fault a large resistance is inserted between the
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source/drain terminal and the circuit node to which the terminal would otherwise be
connected.
Single stuck-open fault can be detected by applying two-pattern test, the first vector to
be applied is called initialization vector and the second vector is called test vector
[13]-[14]. Two vectors are applied to the faulty circuit sequentially. These two vectors
are chosen so that under fault-free conditions, the outputs complements to each other.
The first one initializes the relevant output node to a definite logic state. The second
one sensitizes the fault; it causes the both nMOS devices connected to the same output
node to be OFF. As a result the output node becomes floating and the circuit exhibits
sequential behaviour. The output node retains its previous logic level for some time
before being discharged due to leakage current flowing in the circuit. Reading the
output logic level soon after the application of sensitizing vector would show a faulty
output thereby indicating the presence of a stuck-open fault. In the circuit of Fig.6,
application of vector [A=0, B=0] initializes the output node a logic low level. When
the sensitizing vector [A=1, B=1] is applied, the output node is disconnected from
either of the two input nodes A and B, and is floating thereby retaining the previous
logic low level. This faulty level can be read quickly to manifest the presence of stuck-
open fault on M1. Similar analysis of all the circuits of Fig.1 shows that all single
stuck-open faults result in incorrect output logic and therefore can be detected by logic
monitoring.
SPICE simulations have been carried out for all single stuck-open faults in all the basic
CPL gates. SPICE level-3 parameters were used for the simulations. A 4.7 pf capacitor
was connected to output node. For all SPICE simulations minimum value of fault
9
strength was taken 10 MΩ. In all cases, the sensitizing vector was applied within only
10 ns after application of initialization vector. The output is monitored after a time
delay of 100 ns. This monitoring time is far less than the leakage current time constant.
The result is summarized in Table-3.
2.4: Bridging fault: Bridging fault is generally defined as a short among two or more
signal lines in the circuit as shown in Fig.7. Such a fault may occur due to defective
masking or etching, breakdown of insulator, etc [15].
In case of output bridging, as the output logic levels are complementary, one MOS of
each section of a basic logic module remains ON for any test pattern. Obviously, this
type of fault can not be detected by logic monitoring, however, signal current flowing
through the MOS transistors and the fault resistance Rf is significantly large and is
given by ( )fIH RRonVI += 2 . In case of input bridging, for appropriate test patterns
the steady state current is very large compared to normal operating current and be given
by fIH RVI = .
SPICE simulation is also carried out to analyze the effect of input/output bridging faults
for all the basic CPL circuit modules. Fig. 8 shows the variation of output voltage Vout
and signal source current IDDQ as a function of Rf for AND/NAND module. The current
under faulted condition varies from 1.46 mA to 0.156 mA, whereas the normal
operating current is only 5 pA and hence, this type of fault can be detected by current
monitoring. Similar results have been obtained for other gates.
3 Fault Characterization of CPL Full-adder: Fig.9 shows the CPL Full-
adder SUM and CARRY logic circuits. The behaviour of these circuits under various
10
single stuck-on, stuck-at and stuck-open faults have been analyzed in the following
sections.
3.1 Stuck-on fault: Similar analysis and SPICE simulation as done for basic CPL gates
have been performed for single stuck-on fault on all the transistors of SUM logic and
CARRY logic circuits. It has been found that for SUM logic circuit the single stuck-on
fault on all the eight transistors are detectable by current monitoring using appropriate
test vectors. For some of these test vectors, the fault can be detected by logic
monitoring also but in all cases a large flow of signal current is observed.
Consider a single stuck-on fault on MOS M5 of CPL full-adder SUM logic circuit. The
fault is modeled in Fig.9. The test vectors (000), (010), (100) and (110) produce correct
logic and no significant current flows in the circuit. Hence these vectors are incapable
of detecting the fault. For test vectors (001), (011), (101) and (111), a large signal
source current flows and the fault is detected by current monitoring. In Fig.10, the test
vector (001) is applied, M3, M4, M7 and M8 turn ON and a steady state current IDDQ
flows through M4, M7, Rf and M3 of the circuit. In the faulted circuit, the output voltage
is
( ) ( ) IHonfonfout VRRRRV 3++= . …….………(5)
Above equation shows that when fault strength is maximal i.e. Rf approaches zero, Vout
approaches VIH/3 and when Rf is very large Vout approaches VIH. Now since Vout can
attain any value from VIH/3 to VIH depending on Rf. Hence the stuck on fault at M5
cannot be detected by logic monitoring. However, the steady state current is
significantly large due to the low resistance path between VIH and ground. The steady
state current is given by
11
( )onfIH RRVI 3+= …………………………(6)
Hence, the fault can be detected by current monitoring (IDDQ testing).
The signal source current is approximately 5.4 mA with fault strength of 100 ohms
compared to normal operating current of 5 pA. The result is summarized in Table-4.
Similarly, for the CARRY logic circuit stuck-on fault on all the twelve transistors can
be detected by current monitoring with appropriate test vectors. For some test vectors,
the fault can be detected by logic monitoring, but in all cases, it is also accompanied by
a large flow of signal source current. The result is summarized in Table-4. In case of
CPL full-adder CARRY circuit, M1 and M2; M3 and M4; M5 and M6; M7 and M8; M9
and M10; and M11 and M12 have same results.
3.2 Stuck-at fault: Similar analysis and SPICE simulations have been carried out for
stuck-at fault on all transistors of the SUM logic and the CARRY logic circuits. The
simulation results are summarized in Table-5.
3.3 Stuck-open fault: Similar fault analysis and SPICE simulations are performed for
stuck-open fault on all transistors of the SUM logic and the CARRY logic circuits of
full-adder. The simulation results are summarized in Table-6.
4 Designing CPL circuit for testability: The qualitative analysis and simulation
results presented in section-2 and 3 shows that for CPL basic circuits steady state
supply current (IDDQ) testing gives fault coverage of more than 94% for stuck-on, stuck-
at and bridging faults. For stuck-on and stuck-at fault on CPL full adder circuit, the
IDDQ testing gives fault coverage of 100% for both the SUM logic circuit and the
CARRY logic circuit. This gives us a tremendous opportunity to use IDDQ testing for
fault monitoring in CPL circuits. In fact the above result shows that IDDQ testing based
12
technique is the most natural choice for adopting design for testability approach in
CPL. In this paper we have investigated several techniques to implement IDDQ testing in
CPL circuits.
4.1 Fault detection by current monitoring: For both on-chip and off-chip current
testing, first the upper limit of device complexity for which current testing is applicable
has to be determined. As seen from the results presented in section-2 and 3, the smallest
increase in power supply current occurs for bridging fault between output terminals. In
this case, the minimum output current under faulted condition is 0.156 mA for fault
strength of 20 kΩ, whereas the maximum normal operating current is 100 pA. The ratio
of this fault current to normal operating current is 1.56×106. If we consider a safety
factor of 100, then for every 15600 basic CPL circuits, a current monitoring unit is
required. To facilitate this, the main power supply rail is divided into multiple rail, each
supply current to approximately 15600 basic CPL gates. One current monitoring circuit
will be required for each of the VDD rail.
For off-chip fault detection, we propose the following circuit. A small polysilicon
resistor is inserted into the power supply rail. The resistivity of polysilicon resistor in a
typical 0.25 µm process is 20 Ω/square. Therefore if we insert a polysilicon resistor of
one square then the resistance of the layer is 20 Ω. The maximum normal operating
current flowing through 15600 basic CPL circuit is 1.56 µA. Hence the voltage drop
across the polysilicon resistor under normal operating condition is 31.2 µV, which is
much smaller than VDD. However, for a single stuck-on or stuck-at or bridging fault, the
steady state current due to fault could be from 0.15 mA to 3.0 mA. As a result, the
voltage on the polysilicon resistor could vary from 3 mV to 60 mV. Hence, voltage
13
drop on polysilicon resistor under faulted condition is significantly larger than the
voltage drop under normal operating condition. In off-chip fault detection scheme, the
chip has a test pin on either end of the polysilicon resistor. For polysilicon metal
contact, instead of a big contact, multiple contact cuts should be used to reduce the
effect of the variation of the contact resistance. The effect of process variations on the
polysilicon resistors can be minimized by making the polysilicon squares large in area,
of identical dimensions and by placing them close to each other. The test circuit shown
in Fig. 11 can be built off-chip for online monitoring of fault on the target chip.
The instrumentation amplifier gain is adjusted to about 600 such that a 1 mV
differential voltage at the input is amplified to approximately 0.6 V. A zener diode is
connected at the negative terminal of the op-amp to produce a reference voltage of 0.6
V. Therefore, whenever the voltage drop across the polysilicon resistor exceeds 1 mV,
the output of the op-amp becomes high indicating that stuck-on or stuck-at or bridging
faults have occurred on the chip. For normal operating condition the output is low. Pin
1 and pin 2 of the chip are brought out to facilitate testing. The capacitor C at the output
of instrumentation amplifier is incorporated to protect the system from any transient
variation of input signal.
For fault detection with on-chip current monitoring, we suggest to use Built-in Current
Sensor (BICS). One of the best high-speed BICS design to date has been proposed by
Shen et al. [16]. This design achieves its high performance by using a sense amplifier
structure similar to the bit line sense amplifier employed in dynamic memories.
14
5. CONCLUSION: Theoretical analysis and SPICE simulations of testability of basic
CPL circuits under various single stuck faults are presented. It is found that all stuck-
on faults of all the CPL basic gates can be detected only by current monitoring but no
logic monitoring is possible. Similar results have been obtained for stuck-at faults
between gate and source of the MOS devices of all basic CPL gates. However, for
stuck-at faults between gate and drain, it is found that all stuck-at fault between gate
and drain could be detected by current monitoring except for the following two MOS
devices (i) MOS M3 of the basic AND/NAND gate and (ii) MOS M2 of the basic
OR/NOR gate for which the gate and drain terminals have the same input variable. In
case of stuck-open fault, it has been found that stuck-open faults on all the MOS
transistors of all basic CPL gates can be detected with logic monitoring by applying
appropriate two-pattern test. Stuck-at and stuck-on are the most common faults on
VLSI circuits and for CPL basic gate circuits IDDQ testing gives fault coverage of more
than 94 % for stuck-at, stuck-on and bridging faults. In case of CPL full-adder, we have
found that stuck-on and stuck-at faults on all the transistors of SUM logic and CARRY
logic circuits can be detected by current monitoring, i.e. IDDQ testing provides 100%
fault coverage. Like CPL basic circuits, stuck-open fault on all transistors of CPL full-
adder are detectable by logic monitoring applying appropriate two-pattern test.
Therefore, it can be concluded that signal source current monitoring (IDDQ testing) is the
best method for common fault detection in CPL circuits and gives a very wide range of
fault coverage. Again for detecting stuck-open faults, logic monitoring with two-pattern
test is the only available method so far and for CPL basic circuits it gives fault coverage
of 100%. Therefore, other than low power consumption, higher speed and higher logic
functionality, CPL circuits are also very much promising on the testability point of
view.
15
6. REFERENCES
[1] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi and A. Shimizu,
"A 3.8 ns CMOS 16×16 -b multiplier using Complementary Pass-transistor
Logic", IEEE J. of Solid-state Circuits, 1990, 25, (2), pp. 388-395
[2] M. Avci and T. Yildirim, “General design method for complementary pass
transistor logic circuits”, Electron. Lett., 2003, 39, (1), pp. 46-48
[3] I.S. Abu-Khater, A. Bellaouar and M.I. Elmasry, "Circuit techniques for CMOS
low-power high-performance multipliers", IEEE J. Solid-State circuits, 1996,
31, (10), pp. 1535-1546
[4] I.S. Abu-Khater, A. Bellaouar, M.I. Elmasry, R.H. Yan, “Circuit/architecture
for low-power high-performance 32-bit adder”, IEEE Proc., Fifth Great lakes
Symp., VLSI, 1995, Buffalo, NY, USA, pp. 74-77
[5] A.G.M. Strallo and E. Napoli, " A fast and area efficient complimentary Pass-
transistor Logic carry-skip adder", Proc., 21st Int. conf., Microelectronics,
MIEL, 1997, 2, pp. 701-704
[6] L.K. Wang and H.H. Chen, "A low power high speed error correction code
macro using Complementary Pass-transistor Logic", Proc., 10th Annual IEEE
Int. ASIC Conf. and Exhibition, 1997, pp.17-20
[7] T. Fuse, Y. Oowaki and M. Terauchi, "An ultra low voltage SOI CMOS pass-
gate logic", IEICE Trans. Electronics, E80-C, (3), 1997, pp.472-477
[8] IBM J. Research and development, special issue on IBM S/390 G3 and G4, 41,
Nos. 4/5, July/Sept. 1997
[9] T. Williams and K. Parker, "Design for testability - A survey", IEEE Trans.
comput., 1982, C-31, pp.2-15
16
[10] S.M. Aziz, A.B.M.H. Rashid and M. Karim, "Fault characterization of
complementary pass-transistor logic circuits", Proc., IEEE Int. Conf.,
Semiconductor Electronics, 2000, Malaysia, pp. 80-84
[11] A.B.M.H. Rashid, M. Karim and S.M. Aziz, "Testing complementary pass-
transistor logic circuits", Proc., IEEE Int. Symp., Circuits and System, (ISCAS
2001), 2001, Sydney, Australia, IV, pp. 5-8
[12] N.K. JHA & S. KUNDU, "Testing and Reliable Design of COMS circuits",
Kluwer Academic Publishers, USA, 1990
[13] R. L. Wadsack, "Fault Modeling and logic simulation of COMS and MOS
integrated circuits", Bell Syst. Tech. J., 1978, 57, (5), pp. 1449-1474
[14] W. Maly, P.K. Nag and P. Nigh, “Testing oriented analysis of CMOS ICs with
opens”, Proc. Int. Conf., Computer-Aided Design, Santa Clara, CA, pp. 344-
347.
[15] K.C.Y. Mei, “Bridging and stuck-at faults”, IEEE Trans. Comput., 1974, C-23,
(7), pp. 720-727.
[16] T. Shen, J.C. Daly, and J. Lo, “On-chip current sensing circuit for CMOS
VLSI”, Proc., IEEE VLSI Test. Symp., 1992, pp. 309-314
17
List of Figures
Fig.1 Basic CPL circuits
Fig.2 Simulation circuit for stuck-on fault on MOS M1 of CPL AND gate for test
vector [A=1, B=0]
Fig.3 Variation of output voltage Vout and signal current IDDQ with fault strength Rf for
stuck-on fault on M1 of CPL AND circuit for test vector [A=1, B=0]
Fig.4 Simulation circuit for stuck-at fault between gate and source of MOS M2 of
AND gate for test vector [A=1, B=1]
Fig.5 Variation of output voltage Vout and signal source current IDDQ as a function of
Rf for stuck-at fault between gate to source on MOS M2 of AND gate for test
vector [A=1, B=1]
Fig.6 Stuck-open fault in M1 of CPL AND gate with test vector [A=1, B=1] applied
after initializing vector [A=0, B=0]
Fig.7 Bridging fault between complementary output terminals of OR/NOR gate
Fig.8 Variation of Vout and IDDQ with fault strength Rf for output bridging of
AND/NAND module
Fig.9a CPL full-adder SUM logic circuit
Fig.9b CPL full-adder CARRY logic circuit
Fig.10 Equivalent circuit for stuck-on fault on M5 of CPL full-adder SUM circuit for
test vector [A=0, B=0, C=1]
Fig.11 Fault detection by off-chip steady state current monitoring (IDDQ testing)
18
List of Tables
Table-1: Simulation results for stuck-on faults. In all cases no logic monitoring is
possible, but current monitoring is possible with appropriate test vector
denoting with YES.
Table-2.1: Simulation results for stuck-at fault between gate and source of MOS
transistor. In all cases no logic monitoring is possible, but current
monitoring is possible with appropriate test vector denoting with YES.
Table-2.2: Simulation results for stuck-at fault between gate and drain. In all cases
no logic monitoring is possible, but current monitoring is possible with
appropriate test vector denoting with YES.
Table-3: Simulation results for stuck-open faults. In all cases the fault is
detectable by logic monitoring using appropriate two-pattern test.
Table-4.1: Simulation results for Stuck-on faults in CPL full-adder SUM circuit
Table-4.2: Simulation results for Stuck-on faults in CPL full-adder CARRY circuit
Table-5.1: Simulation results for Stuck-at faults in CPL full-adder SUM circuit.
Table-5.2: Simulation results for Stuck-at faults in CPL full-adder CARRY logic
circuit
Table-6.1: Simulation results for Stuck-open-fault in CPL full-adder SUM circuit
Table-6.2: Simulation results for Stuck-open faults in CPL full-adder CARRY logic
circuit
19
Figure 1
Β
Β
A ΑΒ Β
M2 M3
M4
OR
Q'
M1
Q
NOR
Β
Β
A Α Β Β
M2 M3
M4
AND
Q'
M1
Q
NAND
Β
Β
A Α
M2 M3
M4
EXOR Q'
Α A
M1
Q EXNOR
20
Figure 2
Β
A Β
M2
M1
Rf
VIH
VIH
Vout
B
21
Figure 3
0.0 5.0k 10.0k 15.0k 20.0k
0
1
2
3
4
5
Fault strength (Rf in Ohms)
Out
put V
olta
ge (V
olts
)
Output Voltage (Volts)
-3
-2
-1
0
Cur
rent
(ID
DQ in
mA
)
Current (mA)
22
Figure 4
A Β
M2
M1
Rf
VIH VIH
Vout
B
B
VIH
23
Figure 5
0.0 5.0k 10.0k 15.0k 20.0k
0
1
2
3
4
5
Fault strength (Rf in Ohms)
Out
put v
olta
ge (V
olts
)
Output voltage (Volts)
-3
-2
-1
0
Cur
rent
(ID
DQ in
mA
)
Current (mA)
24
Figure 6
VIH
Vout
A Β
M2
M1
Rf
VIH
B
B
VIH
Cout
25
Figure 7
Β
Β
M2 M3
OR NOR
Rf Q'Q
M1
A ΑΒ Β
M4
26
Figure 8
0 5 10 15 200
1
2
3
4
Out
put v
olta
ge (V
olts
)
Q Q'
0 5 10 15 200.0
0.5
1.0
1.5
Sour
ce c
urre
nt
I DDQ
(mA)
Fault strength (kΩΩΩΩ)
IDDQ
27
Figure 9(a)
Figure 9(b)
28
Figure 10
A
M7
A
VIH
VIH
M4
Rf
Vout
M5
M3
VIH
VIH
C C
29
Figure 11
INSTRUMENTATION AMPLIFIER
Polysilicon
VDD rail
Metal
Pin 1Pin 2
Vo VrefR
C
OP_AMP
30
Table-1
Minimum current, IDDQ = 0.1588 mA
Stuck-on
MOS
Test
Vector(AB)
AND /NAND
gate
OR /NOR gate
XOR/ XNOR
gate
(00) NO NO NO (01) NO YES YES (10) YES NO NO
M1
(11) NO NO YES (00) NO NO YES (01) YES NO NO (10) NO YES YES
M2
(11) NO NO NO (00) NO NO YES (01) YES NO NO (10) NO YES YES
M3
(11) NO NO NO (00) NO NO NO (01) NO YES YES (10) YES NO NO
M4
(11) NO NO YES
31
Table-2.1
Minimum current, IDDQ = 0.1588 mA
Stuck-
at
MOS
Test
Vector
(AB)
AND/
NAND
gate
OR
/NOR
gate
XOR
/XNOR
gate
(00) NO YES YES (01) YES YES YES (10) NO NO NO
M1
(11) NO YES NO (00) YES NO NO (01) NO NO NO (10) YES YES YES
M2
(11) YES NO YES (00) NO YES YES (01) YES YES YES (10) NO NO NO
M3
(11) NO YES NO (00) YES NO NO (01) NO NO NO (10) YES YES YES
M4
(11) YES NO YES
32
Table-2.2
Minimum current, IDDQ = 0.25 mA
Stuck-
at
MOS
Test
Vector
<AB>
AND
/NAND
gate
OR
/NOR
gate
XOR
/XNOR
gate
<00> NO YES YES <01> YES NO NO <10> YES NO NO
M1 <11> NO YES YES <00> YES NO YES <01> YES NO NO <10> YES NO NO
M2 <11> YES NO YES <00> NO YES NO <01> NO YES YES <10> NO YES YES
M3 <11> NO YES NO <00> YES YES YES <01> NO NO NO <10> NO NO NO
M4 <11> YES YES YES
33
Table-3
Maximum current, IDDQ = 132.8 nA
Table-4.1
Minimum current, IDDQ = 0.194mA
Logic monitoring = LM, Current monitoring = CM
Fault Successful Test Vector (ABC)
LM
CM
M1 (000),(001), (010), (011)
No Yes
M2 (000),(001), (010), (011)
No Yes
M3 (100),(101), (110), (111)
No Yes
M4 (100),(101) (110), (111)
No Yes
M5 (001),(011), (101), (111)
No Yes
M6 (001),(011), (101), (111)
No Yes
M7 (000),(010), (100), (110)
No Yes
M8 (000),(010), (100), (110)
No Yes
AND/ NAND
OR/ NOR
XOR/ XNOR
Stuck-open MOS Successful
2-pattern test <AB,AB>
Successful2-pattern test <AB,AB>
Successful2-pattern test <AB,AB>
<00, 11> <01,00> <01,00> M1 <10,11> <11,00> <10,00> <11,00> <00,01> <00,01> M2 <11,10> <00,11> <11,01> <11,00> <00,01> <00,01> M3 <11,10> <00,11> <11,01> <00,11> <01,00> <01,00> M4 <10,11> <11,00> <10,00>
34
Table-4.2
Minimum current, IDDQ = 0.195mA
Logic monitoring = LM, Current monitoring = CM
Fault Successful
Test Vector
(ABC)
LM CM
M1 (001),(100) No YesM3 (011),(110) No YesM5 (011),(110) No YesM7 (001),(100) No YesM9 (001),(011) No YesM11 (100),(110) No Yes
Table-5.1
Minimum current, IDDQ = 0.232 mA
Logic monitoring = LM, Current monitoring = CM
Fault Successful Test Vector
(ABC)
LM CM
M1 (010),(011), (110), (111)
No Yes
M2 (000),(001), (100), (101)
No Yes
M3 (000),(001), (100), (101)
No Yes
M4 (010),(011), (110), (111)
No Yes
M5 (000),(001), (110), (111)
No Yes
M6 (010),(011), (100), (101)
No Yes
M7 (010),(011), (100), (101)
No Yes
M8 (000),(001), (110), (111)
No Yes
35
Table-5.2
Minimum current, IDDQ = 0.2329 mA
Logic monitoring = LM, Current monitoring = CM
Fault Successful
Test Vector
(ABC)
LM CM
M1 (001),(010)
(011),(101)
No Yes
M3 (000),(100)
(110),(111)
No Yes
M5 (000),(001)
(011),(111)
No Yes
M7 (010),(100)
(101),(110)
No Yes
M9 (011), (100) No Yes
M11 (000),(001)
(010),(101)
(110),(111)
No Yes
36
Table-6.1
Maximum current, IDDQ = 16.91nA
Logic Monitoring = LM, Current Monitoring = CM
Fault Successful
Two- Pattern Vectors
O/P Logic Level
Un-faulted
O/P Logic Level
Faulted
LM CM
(000,100) 01 00 Yes No (011,100) 01 00 Yes No (101,100) 01 00 Yes No (110,100) 01 00 Yes No
M1
(001,110) 10 11 Yes No M2 (001,101) 10 11 Yes No
(010,101) 10 11 Yes No (111,101) 10 11 Yes No (101,111) 01 00 Yes No (110,111) 01 00 Yes No
M3 (001,000) 10 11 Yes No (010,000) 10 11 Yes No (011,000) 10 11 Yes No (100,000) 10 11 Yes No (111,000) 10 11 Yes No (000,010) 01 00 Yes No (111,101) 10 11 Yes No
M4 (000,001) 01 00 Yes No (011,001) 01 00 Yes No (101,001) 01 00 Yes No (001,011) 10 11 Yes No (100,011) 10 11 Yes No (111,011) 10 11 Yes No
M5 (001,000) 10 11 Yes No (111,000) 10 11 Yes No (000,110) 01 00 Yes No (110,010) 01 00 Yes No
M6 (001,100) 10 11 Yes No (101,100) 10 11 Yes No (001,110) 01 00 Yes No (111,110) 01 00 Yes No
M7 (000,001) 01 00 Yes No (110,001) 01 00 Yes No (010,011) 10 11 Yes No (100,011) 10 11 Yes No
M8 (000,111) 10 11 Yes No (110,111) 10 11 Yes No (010,101) 01 00 Yes No (100,101) 01 00 Yes No
37
Table-6.2
Maximum current, IDDQ = 56.99nA
Logic Monitoring = LM, Current Monitoring = CM
Fault Successful Two-Pattern
Vectors (ABC)
O/P Logic Level
Un-faulted
O/P Logic Level
Faulted
LM CM
M1 (000,111) 0,1 0,0 Yes No (100,110) 0,1 0,0 Yes No
M3 (011,100) 1,0 1,1 Yes No (101,100) 1,0 1,1 Yes No (110,100) 1,0 1,1 Yes No (111,100) 1,0 1,1 Yes No (100,101) 0,1 0,0 Yes No
M5 (101,000) 1,0 1,1 Yes No (111,000) 1,0 1,1 Yes No (101,001) 1,0 1,1 Yes No (110,001) 1,0 1,1 Yes No (111,001) 1,0 1,1 Yes No
M7 (100,011) 0,1 0,0 Yes No (110,010) 0,1 0,0 Yes No
M9 (011,100) 1,0 1,1 Yes No (000,101) 0,1 0,0 Yes No (001,101) 0,1 0,0 Yes No (010,100) 0,1 0,0 Yes No
M11 (101,010) 1,0 1,1 Yes No (110,010) 1,0 1,1 Yes No (111,010) 1,0 1,1 Yes No
