Experimental investigation of an advanced static VAr compensator

J.B. Ekanayake N. Jenkins C.B. Cooper

Indexing terms: Compensators, Inverters, Power systems

Abstract: An advanced static VAr compensator (ASVC) employing a three-level inverter is pre- sented. The paper describes the operating prin- ciples and construction of a hardware model of this ASVC scheme. The performance of the ASVC is obtained from an experimental study carried out on the laboratory model. The use of the selec- tive harmonic elimination modulation technique (SHEM) to minimise harmonics is explored. Experimental studies have been carried out to determine the effect of the DC-side capacitor on the harmonic performance of the scheme and the open-loop response speed is also evaluated. Finally, the economic feasibility of this scheme is briefly assessed by comparing the ASVC with a conventional thyristor-controlled reactor/fixed- capacitor scheme.

1 Introduction

It is well known that, in an electric power system, the magnitude of the voltage may be controlled by injection or absorption of reactive power. Synchronous com- pensators, mechanically switched capacitors and induc- tors, and saturated reactors have been applied for many years to control the system voltage in this way. More recently, to obtain a smooth variation of the reactive power, thyristor-controlled reactor (TCR) devices together with fixed capacitors (FC) or thyristor-switched capacitors (TSC) have been used. The rating of the induc- tors and the capacitors used in the TCR/FC or TCR/TSC schemes, in most cases, exceeds the reactive power supplied or absorbed by the scheme. This leads to considerable expense and a large requirement for land on which to locate the compensator.

Current advances in power electronic devices now allow the use of voltage-source inverter (VSI) topologies to be considered for reactive power control of electric power systems. These schemes have become known as advanced static VAr compensators (ASVC). In contrast to the TCR/FC or TCR/TSC schemes, the rating of the inductors and capacitors required in an ASVC is only 20-30% of the plant rating. In this way, ASVCs should be more cost effective than conventional schemes. The

0 IEE, 1995 Paper 1710C (PI l), first received 27th April 1994 and in revised form 2nd November 1994 The authors are with the Department of Electrical Engineering and Electronics, UMIST, P.O. Box 88, Manchester, United Kingdom

202

literature includes several publications on ASVCs, and a few prototypes have been reported [l-31. So far, interest has been concentrated on multiphase devices requiring complex transformer connections. This paper describes an experimental investigation of a simple multilevel scheme which has received little attention to date. A single-phase laboratory hardware model of an ASVC employing a three-level VSI topology was constructed and tested. The use of the selective harmonic elimination modulation (SHEM) technique to minimise harmonics is also explored experimentally.

2

The ASVC consists of a voltage-source inverter (VSI) whose DC side is connected to a capacitor. A basic single-phase ASVC circuit is shown in Fig. la. This circuit is inherently two convertors connected in inverse parallel and can be redrawn as Fig. 1 b. Convertor 1 acts as an uncontrolled rectifier, and power flows from the AC side to the DC side through it. Convertor 2 operates in the inverter mode, where the polarity of V,, remains the same but the direction of I , is reversed. Initially, when convertor 2 is not conducting, capacitor C charges up to the peak value of the supply voltage through convertor 1. Providing no real power transfer occurs between the circuit and the supply, the capacitor voltage remains at its initial charged voltage and acts as a constant DC source.

In normal operation, the switching elements of conver- tor 2 are switched so as to develop a voltage in phase with the system voltage. The VSI is coupled to the system via a relatively small reactance which is usually the leakage reactance of the step-up transformer used for connection to the high-voltage network. Owing to this reactive coupling, the line current flowing into or out of the VSI is always at 90" to the network voltage. When the fundamental of the inverter voltage is less than the AC system voltage, reactive power is absorbed by the ASVC. On the other hand, when the ASVC voltage is higher than the system voltage, reactive power flows from the ASVC to the system. This is shown in Fig. 2.

The magnitude of the reactive power absorbed or sup- plied by the ASVC depends on the DC-side capacitor voltage. This voltage can be controlled by adjusting the real power transfer between the ASVC and the system. If the fundamental of the inverter output voltage leads the AC system voltage by a few degrees, convertor 1 con- ducts for a smaller period than convertor 2, causing a net real power flow from the DC side to the AC side, hence decreasing the capacitor voltage. This in turn increases

Operation of the advanced static VAr compensator

I E E Proc.-Gener. Transm. Distrib., Vol. 142, No. 2, Yarch I995

the reactive power absorbed by the ASVC. The converse is true when the ASVC voltage lags the AC system voltage by a few degrees, to give a leading mode of oper- ation. It may be concluded that the reactive power

I I I I I

T2 I I

I I

r---- I I

I I I c T

‘DC I

I

L _ _ _ _ ---_i L _ _ _ _ _ _ _ - _J

converter 2 converter 1

b

Fig. 1 Circuit diagram of rhe ASVC

v1

15 XL + VS Is vs c_

v1

a b

Fig. 2 a Lagging mode of operation b Leading mode of operation V, is the fundamental of the voltage V,

Phasor diagram showing the operation of the ASVC

absorbed or generated by the ASVC can be controlled by one parameter, i.e. the phase angle between the ASVC and the AC system voltage.

I E E Proc.-Gener. Transm. Distrib., Vol. 142, No. 2, March 1995

3 Three-level inverter

The design of the inverter varies in accordance with the rating, the required performance, and with the other desired characteristics for the ASVC application under consideration. At modest power ratings, PWM tech- niques may be used to minimise harmonic distortion [4]. However, in higher power applications, the switching fre- quency must be kept as low as possible to minimise device stresses, switching losses and electromagnetic interference. This can be achieved by using one of a number of configurations. In these configurations, the number of levels refers to the positive voltage levels including zero which appear in the ASVC output voltage (V’) when very large capacitors are used on the DC side. The configurations include:

The simple two-level inverter as shown in Fig. la with the SHEM technique.

The multiphase configuration comprising a number of two-level inverters connected together by complicated transformer arrays.

The multilevel inverter employing more than two levels described by Choi et al. [SI.

For most compensation applications, to obtain high kVAr capability using presently available semicon- ductors, the ASVC must be operated from a relatively high voltage. This becomes difficult when using a two- level inverter, as the semiconductor devices must be con- nected in series to obtain the required high-voltage operation. The second configuration, the multiphase con- vertor configuration, requires more switching devices and very complex transformer arrays to achieve low harmo- nic distortion at the output voltage.

The third approach, a multilevel arrangement, can be used either to eliminate or minimise lower-order harmo- nics while increasing the overall rating of the ASVC. Therefore, a three-level bridge voltage-source inverter, which is shown in Fig. 3a, is proposed in this paper for VAr compensation.

In the three-level arangement, each switching element has to block only half of the DC voltage due to the clamping diodes connected to the midpoint of the DC capacitors. This is a significant advantage of the three- level inverter over the two-level topology. Further, the three-level inverter gives double the power rating of the two-level inverter. Finally, the three-level inverter is very attractive because of the additional features it provides for controlling an ASVC. As shown in Fig. 36, the funda- mental amplitude of the ASVC output voltage depends not only upon the DC capacitor voltage, but also on the angle 8” (see Fig. 3b). These free parameters are available to minimise or eliminate certain harmonics and to allow the dynamic control of the ASVC.

The basic circuit diagram together with the output voltage waveform and switching pattern which can be used to obtain three voltage levels is shown in Fig. 3. The operation of the three-level inverter depends upon the ratio of the voltage across the two capacitors. Fig. 3d shows those switches which have to be ‘ON to obtain the required voltage level in the inverter output voltage (VJ. There are a number of combinations that can be used to obtain some of the voltage levels, and those con- sidered in this study are marked as switching patterns ‘1’ and ‘2’. If the switching pattern marked as ‘1’ in Fig. 3d is used, the lower capacitor can lose charge more rapidly than the upper capacitor, causing a voltage unbalance between the two capacitors. The reverse is true if the switching pattern marked as ‘2’ is used. Various tech-

203

niques, either based on a multilevel PWM method [6] or employing a regulator circuit [SI, are described in the literature to overcome these unbalances. However, these techniques produce higher losses because of the addi- tional chops in the voltage waveforms, or because more resistors and inductors are introduced into the circuit. A new approach for voltage balancing which uses switching patterns '1' and '2' alternatively in each half-cycle is pre- sented in this paper. However, due to the inductive or

capacitive nature of the current in the ASVC circuit, the switching pattern must be changed at current zero, i.e. at voltage peak of the voltage V,, to obtain a smooth tran- sition from one pattern to the other.

3.1 Fundamental frequency switching The output of the ASVC using very large DC-side capa- citors, and fundamental frequency switching is shown in Fig. 36. To obtain this wave shape, the switches in the

vc2 I 2 ' ,I( ID-2

a

I

t"

U

b

I 01 03

' w w'-

Voltage 0 2 Q1 0- 1 0 - 2 02' 01' 0 - 1 ' Q-2 ' Switching level pattern

0 OFF OFF ON ON OFF OFF ON ON 1 OFF ON ON OFF OFF ON ON OFF Not used ON ON OFF OFF ON ON OFF OFF 2

V.,,l2 OFF ON ON OFF OFF OFF ON ON 1 ON ON OFF OFF OFF ON ON OFF 2

V,, ON ON OFF OFF OFF OFF ON ON 1. 2 d

Fig. 3 a Circuit diagram b Waveforms of voltage V, with fundamental frequency switching c Waveforms of voltage V, with two chops per half a cycle d Switchin% pattern

Circuit diagram, corresponding waveforms and switching pattern for the .?-level inverter

204 IEE Proc.-Gener. Transm. Distrib., Vol. 142, No . 2. March 1995

ASVC inverter circuit have to be switched according to Fig. 3d. In this case, all the switches only operate once during a single cycle of the voltage V, and so this tech- nique is referred to as fundamental frequency switching (FFM). From Fourier analysis, optimum values for 81 and 82 can be found to minimise the harmonic content of the voltage waveform. By selecting 81 = 71/12 and 82 = 44 , the triplen harmonics can be eliminated while minimising the Sth, 7th 17th, 19th, 29th and 31st etc. In the case of three-phase applications, the line-to-line voltage is exactly the same shape as the waveform in Fig. 3b and the total harmonic distortion will be reduced by almost 50% compared to that of the two-level voltage waveform [7].

3.2 Selective harmonic elimination modulation

The harmonic content of the inverter output voltage can be further improved by using the SHEM technique. By introducing symmetrical chops in the voltage waveform, as shown in Fig. 3c, certain harmonics can be eliminated in the voltage waveform. The harmonic content of the inverter output voltage for this technique can be obtained from Fourier analysis. Owing to quarter symmetry of the switching pattern, only odd harmonics are present at the output voltage.

(SHEM) technique

The inverter output voltage is given by m

V, = b, cos (nwt) n = 1 , 3 , ...

where

b, = 21.',, [cos nB1 + cos nBz - cos np3 + cos nB4] nn

To eliminate the 3rd, 5th, 7th and 9th harmonics, a set of simultaneous equations given by b, = 0 for n = 3, 5, 7 and 9 can be solved. Multiple solutions are possible for these equations and one solution was examined to demonstrate the ability of the SHEM technique to elimi- nate the harmonics. A Newton Raphson method was used to solve those simultaneous equations and 8" were found as

81 = 14.57", 82 = 45.43", 83 = 57.43" and 84 = 62.57"

Table 1 compares the harmonic content of this technique with 2-level and 3-level waveforms where only fundamen- tal frequency switching is used. Table 1 : Calculated percentage harmonic voltage content with respect t o the R M S fundamental frequency com- Donent of the voltaae V.

~ ~~

Harmonic 2-step with 3-step with 3-step with fundamental fundamental two chops frequency frequency switching switching

3 33.33 0 0 5 20.00 5.359 0 7 14.28 3.828 0 9 11.11 0 0

11 9.09 9.091 4.703 13 7.69 7.692 3.801 15 6.67 0 6.550 17 5.88 1.576 3.528 19 5.26 1.41 0 0.077

4 Experimental study

A small-scale single-phase laboratory model was con- structed to study the characteristics of the ASVC. A

I E E Proc.-Gener. Transm. Distrib., Vol. 142, No. 2, March 1995

three-level inverter topology was employed using GT8QlOl IGBTs which are rated at 8 A with a maximum saturation voltage of 4 V . To maintain the voltages of the two capacitors at the same level, from positive peak to negative peak of the ASVC output voltage, the switching pattern marked as '1' in Fig. 3d was used, and during negative peak to the next positive peak, the switching pattern marked as '2' was used.

A pulse-transformer isolated-gate drive circuit was implemented. During the turn-off transient of the IGBT, a very high overshoot in V,, was observed initially. Therefore, to allow control of the turn-on and turn-off time together with minimum overshoot, the polarised gate drive resistance and a series resistor capacitor feed- back suggested in Reference 8 was used. Overcurrent and overvoltage protection circuits were also included for safe operation of the ASVC.

The operation of the ASVC was studied for the follow- ing two cases.

Case A : Operation of the three-level inverter with funda- mental frequency switching. Case B: Operation of the inverter with the SHEM tech- nique. To keep the switching frequency relatively low, only two chops were introduced. Owing to practical difi- culties in obtaining optimum angles for p, the following values were selected

81 = 15", 82 = 45", 83 = 52.5" and 84 = 60" The errors introduced by these nonoptimum firing angles are tabulated in Table 2. Table 2: Percentage harmonic voltage content for the 3-level voltaae waveform with t w o choos Der half a cvcle _____ ~ ~~ ~ ~~

Harmonic 3 5 7 9 11 13 15 17 19 Theoretial 1.62 2.33 0 39 4.38 2.21 9.67 5.89 7.29 0 27

Experimental 1.25 2.44 1.28 3 50 2 95 8.13 460 6.21 0 61 values

values

As the reactive power output of the ASVC depends upon the phase angle between the ASVC and the supply system, a phase-looked loop (PLL) in conjunction with other logic devices was utilised to generate firing signals for the two cases. The PLL was used together with a divide-by-24 counter as shown in Fig. 4. The phase detec- tor compared the voltage-controlled oscillator (VCO)

vni demand

divide by y dwde by 2 V7H-tLf 4 counter 6 counter

Fig. 4

output divide-by-24 signal with the phase shifted control signal, and produced an error signal. This error signal was added to the VAr demand signal, which was intro- duced manually. This signal was used to control the VCO and so produce firing signals to the IGBTs to obtain the correct phase shift with respect to the system voltage to fulfil the reactive power requirements. The signals at points X, Y and Z were used to obtain the correct firing signals for the two cases.

Tests were carried out for Cases A and B by driving the IGBTs to obtain the output voltage of the ASVC in

Block diagram of the control circuit

205

phase with the system voltage apart from the small phase angle used to control the reactive power exchange. Fig. 5 shows the ASVC output voltage (VJ, ASVC current (is) and DC capacitor voltages for the leading and lagging mode of operation for Case A with C1 = C, = 220 pF.

4.1 Harmonic performance In VAr compensation applications, the current harmo- nics are important as the voltage at the bus to which the compensator is connected is directly affected by them. When the value of the capacitance is high, the output

t

datum

t

I

(1 b

Fig. 5 a Far leading mode of operation

System voltage, ASVC output voltage, ASVC current and capadcitor voltagesfor Case A with C , = C , = 220 p F b Far laggng mode of operation

V, and V, - 10 V/dw Timejdiv - I ms/div yt and V,, - 4 Vidtv: I ms/dw

is ~ 400 mA/div V, and V, - 10 V/div Timeidiv - 1 msjdw V,, and V,, - 4 Vidiv: 1 msjdw

i, ~ 400 rnA/div

Similar waveforms for Case B are shown in Fig. 6. Tests were also carried out with C, = C , = 2200 pF capacitors on the DC side, and the two capacitor voltages with and without voltage balancing are shown in Fig. 7, for Case B. In all tests, a reactor with inductance 50mH and resistance 1.5 C2 was used as the AC side inductance X , .

To examine the dynamic behaviour of the open-loop system, the VAr demand signal was abruptly changed so as to take the ASVC into VAr generation mode and VAr absorption mode. The corresponding response form of the peak value of the ASVC output voltage is shown in Fig. 8. It may be observed that the open-loop response is rather slow due to the time constant of the AC side inductance (X , ) charging the DC side capacitors (Cl, C,). An estimate of this time constant may be obtained by considering a simple series RLC circuit which, with the AC side inductance and its associated resistance, leads to a time contant of 67 ms. This broadly agrees with the experimental data.

voltage waveform of the ASVC follows the theoretically expected wave shape shown in Figs. 3b and c. However, when the value of the capacitance is low, the voltage waveform deviates from that expected due to the ripple on the DC-side capacitors. Therefore, one might expect more current harmonic distortion with smaller values of capacitance. Fig. 9 shows experimental results giving the variation of the 5th, 7th and 9th harmonic component in the ASVC current waveform for Case A with 220 pF and 2200 pF capacitors on the DC side. A similar diagram for Case B is shown in Fig. 10. It is clear from the diagram that the harmonic distortion in the current is only slight- ly dependent on the value of the capacitance used. However, it was noted experimentally that the 3rd- harmonic component increased when the value of the capacitance was reduced.

Theoretically, the three-level VSI with Case A should not produce triplen harmonics. However, owing to unbalances in capacitor voltages and differences in

206 I E E Proc.-Gener. Transm. Distrib., Vol. 142, No. 2, March 1995

voltage drops in the IGBTs and their antiparallel diodes, the third harmonic appears in the current waveform. When considering a full scale application, the system

rather small but allows the design of the ASVC to be based on well established technology. A comparison is carried out between a TCR/FC scheme and the ASVC

t

I datum t I datum

t b

Fig. 6 a For leading mode of operation

ASVC output voltage, ASVC current and capacitor voltages for Case B with C , = C , = 220 p F b For lag& mode of operation

Vx ~ IO Vidiv i, - 200 mA/dtv Time/div - I ms/div V, , and V,, ~ 4 Vidiv: I ms/div

V, - 10 V/dw i, - 200 mA/div Time/div ~ I ms/div V,, and Y 2 - 2 V/div: 1 ms/div

voltage would be much higher than the on-state drop of the switching devices. Hence, the phase shift in the ASVC voltage with respect to the system voltage would be very small and the 3rd-harmonic distortion would be expected to be correspondingly low.

5

It is of interest to compare the merits of emerging tech- nologies such as ASVCs with those of conventional VAr compensators. A technical comparison of the ASVC with TCR and TSC schemes is given in Reference 9 for high- power applications. However, it is also important to assess the economic feasibility of ASVCs. For a compari- son to be made, the voltage and compensating require- ments have been assumed to be identical.

In this brief study, a single-phase compensator with & 350 kVAr, 1200 V rating is considered. This rating is

Economic comparison with the TCR/FC-type compensator

employing a three-level VSI which uses the SHEM tech- nique to eliminate the lower-order harmonics. For the ASVC, IGBT modules having two IGBTs in series can easily be used for an economic and compact design. Further, the leakage reactance of the transformer can be used to support the reactive power flow between the circuit and the system. The rating of the DC capacitors required in this case cannot be calculated easily. Ideally, the ASVC does not require storage of energy for the generation or absorption of reactive power. However, a small capacitor is required to supply the ripple current, and it is suggested in the literature that the rating of the capacitor can be reduced to about 20 to 30% of that required for conventional schemes [9, lo]. To demon- strate the comparison, the ratings of the various com- ponents needed for each case are tabulated in Table 3. From that table it is clear that, in terms of components, the ASVC appears to have a clear advantage over the TCR for single-phase applications.

I E E Proc.-Gener. Transm. Distrib., Vol. 142, No . 2, March I995 207

t

_* -. "; 1

t

L - .A -,--

E - c

datum vc2

datum not shown

1 datum

t

datum

Fig. 7 (1 Far leading mode of operation

V= - IO V/div: I . - 200 mA/div Time/div - I msidiv V,, and V,, ~ 4 V/div: 1 ms/div With voltage balancing V ; > and V:, - 4 V/div: 1 mJdiv Without voltage balancing

b For lagging mode of operation Vx - 10 V/div: I , - 200 mA/dw Time/div - I ms/div V,, and V,, - 1 V/div: I ms/div With voltage balancing V:, and V : , - 1 V/div: 1 ms/div Without voltage balancing

ASVC output voltage, ASVC current and capacitor voltages for Case B with C , = C, = 2200 p F

208 I E E Proc.-Gener. Transm. Distrib., Vol. 142, No. 2, March 1995

Table 3: Comparison of conventional and advanced SVCs for a single-phase application

TCR/FC ~~

Transformer 35WOO kVA Reactor 1200 V. 495 kVAr Capacitor 1200 V, 220 kVAr

Filter 3rd 1200 V, 75 kVAr 5th 1200 V, 25 kVAr 7th 1200 V, 15 kVAr 9th 1200 V, 15 k,VAr high 1200 V, 15 kVAr

components

Semiconductor thyristor 2 nos. elements 1200 V, 450 A

one circuit breaker to switch the caoacitor

ASVC

350-400 kVA

750 V. 70 kVAr 2 nos. high 1200 V, 15 kVAr

IGBT modules 4 nos. (600 V, 300 A) diodes 4 nos. (1200 V. 300 A)

t

t

t

t a

t

1. , , , , , , . , I , , , , . , I , , I , , , I ,

_1_1

L

b

Fig. 8 LI Floating condition lo the leading mode b Floating condition lo the lagging mode Timeidiv - 4 ms/div Datum of the voltage is not shown

Peak value ofthe ASVC output voltage (V,)

V/div - 3 V/dw

6 Conclusions

In the work reported in this paper, a laboratory model of a reactive power compensator employing a three-level voltage-source inverter has been successfully implement- ed and tested. The experimental study carried out on the

I E E Proc.-Gener. Transm. Distrib., Vol. 142, No . 2, March 1995

ASVC has demonstrated the ability of such a device to both absorb and generate reactive power.

Experimental harmonic studies carried out suggest that the performance of the ASVC is only slightly depen- dent on the value of DC-side capacitance. Therefore, rather small values of capacitors can be used on the DC side.

- 0 6 - 0 L - 0 2 0 0 2 0 4 0 6 effective fundamental RMS current ( p U on L A base 1

Fig. 9 Harmonic content in the ASVC current ( iJfor Case A * . 5th - Cl = C2 = 220 pF

. . W . ' 5th-C1 =C2=2200pF - x - 7th-Cl = C 2 = 2 2 0 p F -+- 7th - C1 = CZ = 2200 pF -A- 9th - C1 = C2 = 220 pF -X- 9th-Cl = C 2 = 2 2 0 0 p F

U I

0 6 1

I

0 0 2 0 4 0 6 effective fundamental RMS current ( p U on 4 A base)

Harmonic content in the ASVC current ( iJfor Case B Fig. 10 - * - 5th-C1=C2=220pF

. . W . . 5th-C1 =C2=2200pF -x- 71h-C1=C2=220pF -+- 7th - C1 = C2 = 2200pF -A- 9th - C1 = CZ = 220 pF -X- 9th - C1 = C2 = 2200 pF

A preliminary investigation has shown that the open- loop speed of response of the ASVC is slow for some special industrial applications. This area has to be addressed before such an ASVC is used for a real-scale application and is the subject of continuing research.

209

7 References

1 GYUGYI, L., HINGORANI, N.G., NANNERY, P.R., and TAI, T.: ‘Advanced static VAr compensator using gate turn-off thyristors for utility applications’. Cigre, Paris, 1990, paper 23-203

2 EDWARDS, C.W., and NANNARY, P.R.: ’Advanced static VAr compensator employing GTO thyristors’, IEEE Trans. Power Deliu., 1988, 3, (4), pp. 1622-1627

3 MORI, S., MATSUNO, K., TAKEDA, M., and SETO, M.: ‘Devel- opment of a large static VAr generator using self-commutated inverters for improving power system stability’, IEEE Trans. Power Syst., 1993,8, (1). pp. 371-377

4 SJOERD, W.H., DE HAAN, GERJAN, J.J., and DE LEIJER: ‘A pulsemodulated low volume reactive-power compensator’. Euro- pean Power Electronics Conference, Aschen, 1989, pp. 1175-1 179

5 CHOI, N.S., CHO, J.G., and CHO, G.H.: ‘A general circuit topol- ogy of multilevel inverter’. IEEE 22nd Annual Power Electronic Specialist Conference, USA, 1991, pp. 96-103

6 CHOIS, N.S., CHO, G.C., and CHO, G.H.: ‘Modelling and analysis of a static VAr compensator using multilevel voltage source inverter’. IEEE Industnal Application Society 28th Annual Meeting, Canada, 1993, pp. 901-908

7 BHAGWAT, P.M., and STEFANOVIC, V.R.: ‘Generalized struc- ture of a multilevel PWM inverter’, IEEE Trans. Ind. Appl . , 1993, IA-19, (6), pp. 1057-1062

8 HEFNER, A.R.: ’An investlgation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)’, IEEE Trans. Power Electron., 1991,6, (2), pp. 208-218

9 CHAMIA, M., DAFGARD, A., FRANK, H., and ANGQUIST, C.: ‘Impact of present and future technologies on the design of SVC substations’. Cigre, Paris, 1990, paper 23-201

10 WUEST, D., STEMMLER, H., and SCHEUER, G.: ‘A comparison of different circuit configurations for an advanced static VAr com- pensator (ASVC)’. PESC‘92, 23rd Annual IEEE Power Engineering Specialist Conference, 19 June-2 July 1992, pp. 521-529

210 IEE Proc.-Gener. Transm. Distrih., Vol. 142, No . 2, March 1995