Evaluation of effective throughput rate for certain ATE architectures with data compaction/decompaction

70 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. VOL. 37, NO. I , MARCH 1988

Evaluation of Effective Throughput Rate for Certain ATE Architectures with Data Compaction/

Decompaction

Abstract-Automatic Test Equipment (ATE) architectures are presented for functional digital testing. Formulas for effective throughput rate, refresh rate, burst rate, and compaction ratio are introduced to compare architectures. Methods of horizontal and vertical data compaction are examined to determine the effect of compaction ratio on effective throughput rate.

I. INTRODUCTION TO AUTOMATIC TESTING TECHNIQUES

UTOMATIC TESTING can be divided into three A types [l] . The first type is functional (dc or static) testing, where inputs are applied to a unit under test (UUT) to analyze its steady-state outputs and determine correct functional behavior. The second type is parame- tric (ac or dynamic) testing, which tests the magnitude of certain circuit parameters, such as timing and input, output, and supply voltages and currents. Finally, there is clock rate testing, which is similar to functional testing but performed at near maximum device frequency to speed the testing of complex devices.

One subdivision of functional testing is Algorithmic Pattern Generation (APG). It is used to test random access memories (RAM) by generating simple test patterns algorithmically in real time. Galpat, checkerboard, ping- pong, marching l’s, and walking 1’s are examples of APG tests. Since the patterns needed to test non-memory (combinational and sequential logic) circuits cannot be de- scribed algorithmically, APG is restricted to testing memories. The other major subdivision of functional testing is the pre-test generation of patterns that are stored on auxiliary memory. This paper deals with one of the above- mentioned types of testing, namely functional digital electronic testing based on the pre-test generation of patterns.

Data compaction techniques used in digital testing take advantage of several test pattern characteristics. There is a high probability that only a small percentage of state

Manuscript received November 5, 1986; revised February 23, 1987. S. R. Campbell is a member of the technical staff at RCA, Automated

M. F. Wagdy is with the Department of Electrical Engineering, Uni-

IEEE Log Number 8717641.

Systems Division, Burlington, MA 01803.

versity of Lowell, Lowell, MA 01854.

changes will occur from pattern X, applied to the UUT, to pattern X + 1, the next pattern applied to the UUT. Often a single bit of a pattern will not change state for a sequence of several patterns [2]. Typically, certain groups of I/O pins of a UUT represent given functions of that circuit. Thus, knowledge of the UUT pin function yields information about its state. For example, clock pins will have a specific repeatable sequence of ones and zeros associated with them, and UUT enable lines will remain in a given state for a number of test patterns. These characteristics allow the generation of codes that represent raw (or absolute) data in a compacted format. These codes are based on information theory.

Information theory and source coding provide us with several principles. Shannon’s first theorem states: ‘‘Given a channel and a source which generates information at a rate less than the channel capacity, it is possible to encode the source output in such a manner that it can be trans- mitted through the channel” [3]. His studies lead to many principles pertinent to automatic testing [4]. The most important test pattern characteristic is redundancy. A message has redundancy if there is a certain degree of pre- dictability among the sequences which constitute the message. Information preserving transformations are used for mapping an input set of message sequences into a cor- responding output set that contains fewer binary digits. This mapping is reversible, that is, the input can be ex- actly reconstructed from the coded output. A predictive transformation represents an operation on the input message sequences for the purpose of producing a set of output sequences that exhibit a prescribed structure. Encod- ing of variable-length sequences of source outputs into codewords of constant length is called variable-length-to- block coding [ 5 ] . Digital test patterns are not completely random, and therefore, some redundancy exists. Thus, through the use of coding, redundancy can be removed from patterns so that the refresh channel can be used with maximum efficiency. In Section I1 a basic ATE architecture is presented together with the necessary derivations to create a figure of merit to be called the “Effective Throughput Rate” (ETR). Horizontal and vertical data compaction techniques are considered in Sections I11 and IV, respectively, and their effects on ETR are evaluated.

0018-9456/88/0300-0070$01 .OO 0 1988 IEEE

CAMPBELL AND WAGDY: ATE ARCHITECTURES 71

11. DIGITAL TESTING A. Pattern Memories

Figure 1 shows a digital ATE architecture that uses four pattern storage memories necessary to perform functional digital testing: stimulus (force) patterns, expected response (predicted) patterns, tristate (inhibit or connect) patterns, and mask (“don’t care”) patterns [6] . The stimulus patterns supply input patterns to the UUT. The output patterns of the UUT are compared to the expected response patterns in real time [7]. Tristate patterns inhibit the high-impedance UUT line-driver if a bidirectional UUT pin is used as an output, or enable the driver to ap- ply a stimulus to the UUT. Mask patterns are used to pass or mask the response. A UUT pin’s response is masked when it is a “don’t care.”

The system halts testing or modifies the pattern output sequence in response to the failure of a single bit, or the failure of a combination or sequence of bits. A failure occurs if the actual response does not match the expected response. Ending the test upon a single error represents goho-go device testing. Another test method is to con- tinue testing and log all errors in an error memory as they occur.

Figure 2 identifies an architecture that uses only three pattern memories. This architecture combines stimulus and expected response patterns state patterns. Thus,

red is reduced by 25 percent. in this paper implement this

Figure 3 shows the baseline architecture for a functional digital tiester. Na data coMpaction techniques are implemented in this scheme. An optical disk drive is an example of an auxiliary memory, which is used to store test patterns. Typically, 50 Gbits can be stored on each disk. This is necessary since UUT’s have been identified that require as many as 4 OOO 0o0 patterns to test. Each disk contains 18 data channels, but in this configuration only 16 channels of each disk are used. Data can be accessed randomly or sequentially from the disk. The system has 5 12 test point interfaces with the UUT. The electronics for these test points are provided on 64 test point cards. Each test point card has electmhics for eight test points including local memory used to store the test patterns before they are burst to the UUT. Thus each of four

data for 16 test point cards. s three N X 8 bit memories

mask patterns, where N is the . The system has a totalof 192

N k 8 bit memori’es, that is, 1536 X N bits.

C. Definitions and Formulas

rate, and interburst overhead.

ond, at which ,patterns are

There are three terns related to ETR: refresh rate, burst

Let us &fim pqfmSh,,r8te as ed, in bib per sec- from auxiliary

HIGH IMPEDANCE DRNER

BlDlRECTlONAL UUT PIN

STIMULUS PATTERNS =-?-I-

0-WRRECTORQON‘TCARP 1 =ERROR

Fig. 1 . Four-pattern memory architecture.

HIGH WEQANCE - O A M R STATE b BIDIRECTIONAL I PATTERNS UUT PIN

pq* PATTERNS -

0 = STIMULUS 1 E RECEIVE OR TRISTATE 1 ~ R E c E I V E R

0 = MASK 1 * PASS

0 -CORRECT. ‘DON7 CARE”, TRISTATE Uv7 OR STATE PATTERN WAS STIMULUS

Fig. 2. Thm-pattern memory architecture.

‘PIN.

BURST CHANNEL CHANEL

UUT PINS UL~T mw urn plw W T PINS

Fig. 3. Digital tester baseline architecture

memory to local memory. During refresh time, which occurs between bursts, patterns cannot be transferred from local memory to the UUT since local memory is not dual- port random access memory. Dual-port RAM can be writ- ten to and read f m concurrently, whereas static RAM cannot. The .qa@ ia shown to be a mnliwar tunc- tion of the nun;lbar of patter& ’being transferred, by the

72 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 31, NO, I , MARCH 1988

example of Fig. 4 [8]. We will denote it by: refresh rate (N). Figure 4 shows typical transfer (refresh) rates for mass memory devices. A fixed amount of software overhead is associated with each refresh depending on the size of the transfer. As the block size increases, the percentage of software overhead decreases.

Burst rate can be defined as the speed, in patterns per second, at which patterns are transferred from local memory to the UUT. A burst is the transfer of N patterns from local memory to the UUT, and exhausts local memory. The burst time is the time it takes this transfer to occur.

The setup of clock sources, enable and disable of load logic, and similar overhead associated with each burst is interburst overhead and shall be denoted by K.

ETR would thus be the speed at which patterns are transferred, in patterns per second, from auxiliary memory to the UUT. The ETR is an important measure of automatic test equipment (ATE) performance because it contributes to the total time to test a UUT.

The following definitions and formulas establish a baseline for comparison of compaction schemes.

N = depth of local memory = number of patterns/

B = # of bursts = total # of patterns/N burst

TP = test point-total number of patterns to UUT = ( # of patterndburst ) x ( # of bursts)

total time = refresh time + burst time + interburst overhead time

ETR = total number of patterns to UUT/total time EZR = total number of patterns to UUT/(refresh time

+ burst time + interburst overhead time)

' 8 1 0

0 20 40 60 80 100 120 140 160 180 200

BLoa(sm (KILOBYTES]

Fig. 4. Refresh rate versus block size.

Mpatternslsec 1.0

0.9 "

0.8 '. 0.7

0.6 .. 0.5 .. 0.4 .. 0.3 .. 0.2

0.1

-

.'

.'

.. 0 20 40 BO 80 100 120 140 160 180 200

BUXXWE [KILOBYTES]

Fig. 5. Effective throughput rate (ETR) versus block size.

if the number of bursts is an integer value. Figure 5 is a plot of ETR versus block size using the data from Fig. 4, and shows that an improvement in refresh rate, burst rate, or reduction in overhead will improve the ETR.

( 1 )

(2)

( 3 )

(1 TP card/channel) x (8 TP's/TP card) x ( 3 X N bits/TP/burst) X B refresh rate (N )/channel

refresh time =

N x B burst rate

l x 8 x 3 x N x B

burst time =

N X B ETR =

N x B + K x B ' + refresh rate (N) burst rate

As a numerical example, for a block size of 32 kbytes and a refresh rate of 17.1 Mbits/s, the refresh time is approximately 46 ms; for a burst rate of 50 mpatterns/s, the burst time is 0.65 ms. The interburst overhead time (K x B ) can be assumed negligible, since it is on the order of a few microseconds. Thus the third denominator term can be dropped from (3), and it reduces to

. (4) 1

24 1 ETR =

+ refresh rate (N ) burst rate

These formulas show that the ETR is independent of the number of bursts and dependent only on the burst rate and the refresh rate, which is, in turn, dependent on N (since N X B can be factored out of both the numerator and denominator). It should be noted that (4) is valid only

111. HORIZONTAL COMPACTION

A. State Change Format

The state change format can be used for functional digital testing. State change testing is a form of horizontal compaction in which the patterns are processed into bit state changes which occur between patterns in order to decrease the data storage area required. Horizontal compaction is the compaction of a pattern to be applied to the UUT and not the compaction of a string of bits behind a UUT pin, which is vertical compaction.

Two pieces of information are needed to completely de- fine a pattern's bit changes: l) the number of bit changes per pattern; and 2) a list of the bit positions (UUT interface pins) that will toggle in a pattern. This data is stored in compacted format on auxiliary memory and then trans-


BIT PO^^ " C

"BITPOSITION ' (UUTPIN) a

err PosmON ' d #BIT CHAffiES PER PATFERN B

b XBITCHANQESPERPAlTERN C '

BITPOS!TIC+4 (UUTPIN) a BIT pogmohl " b ' BIT PQSITION

. * BIT PoalloN

. '

-1 BIT POSITION

9 BlTS Fig. 6. Example af state change format file.

ferred in compacted format to local memory. An example list for three patterns with four state changes in the first pattern, two state changes in the second, qnd three state changes in the third is &own in Fig. 6. The first pattern is created from a pattern with qros in every bit pasition. A real-time hardware cpmpsrison i s used to check the actual response patterns q a b s t the expected response ac- cording to the mask patterns.

B. State €hange Archiremres Figure 7 presents an architecture that implements the

state change format. Just h e pattern memories are required for the entire tester. Each of these contains information describing which of the tester's 512 interface pins must change state (toggle) for each pattern output. This

quires fewer (optical) disk the 64 of the previous ar-

chitecture. The ATE/UUT test points can be accessed uniquely by treating the batkrn stoked in local memory as address bits. For 512 test whits the local memory must be 9 bits wide. The maxim& nuhber of state changes from pattern X to pattern X +. 1 is 512. The minimum number of state changes fro mXtopatternX + 1 is zero but this still it. Zero state cha lkation and wait- ing. Initialization defines an input sequence that will drive a circuit from an unknown state tp a fixed state. A real- time hardware decompaction will occur during each burst, thus decoding hardware will have no effect on ETR.

In an attempt to keep the total amount of memory per refresh channel equal to 24 x N bits (for comparison with the previous basic architecture of Fig. 3), the depth of each state, tristate, and mask pattern memoPies is 24 x N bits. Each column of local menlory is lrefrtshed sirnulta- neously by its own optW'Idisk channel. The horizontal compaction ratios pmented below represents the relative

((24 X N)/(avgST + burst time =

burst rate

MEMORY STATE

MEYRY 8 TRISTATE

ADDRESS DECODER

UUT PINS

Fig. 7. State change format architecture.

amount of auxiliary memory required for storage of the pattern set as compared to the previous architecture. Let us again assume that the interburst overheact is negligible. C. DeJinitions and Formulas

The following definitions and formulas establish a baseline for comparison.

ST = number of state changes from pattern X to pattern x + 1.

avgST = average # of state changes.

avgST + 1 * average # of words required to represent a pattern (where "1" represents the word required to store the number of bit changes per pattern).

(24 x N ) /( avg ST + 1 ) = # of patterns represented

CH = horizontal compaction ra-

The ceiling functioq denotes the least integer that is greater than or equal to the quantity in the, parenthesis.

ceiling (log, # of TP) = the number of bits required to

' per burst.

tio.

address the test points. # of TP = number of test points.

%H = # of TP/(ST X ceiling (log, # of TP) + ceiling (log, # of T P ) ) .

CH = # o f TP/((ST + 1) x ceil- irlg ( logz # of TP) ).

( 5 ) (24 X Nbits/channel/burst) X B

qefresh rate (N )/channel refresh time =

2 4 x N x B refresh rate (N)

refresh time =

((24 X N)/(avg$T + 1)) x d ' 24 X N X B (24 x N)/(avaST + 1) X B

+ K x B , I \ " + ' refresh rate (N) burst rate

74 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 31. NO. I , MARCH 1988

30 T

TP CH . .............................

(ST+llxcpiling(logZTP)

wiIhTP.512

0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 ST

Fig. 8. Horizontal compaction ratio [CHI versus number of state changes [ST].

N = 192K N = 64K N - 32K

, N - 4K

Fig. 9. Effective throughput rate [ETR] versus average number of state changes.

Now assuming again that K refresh time and burst time,

is negligible with respect to (8) reduces to

+ ‘ . - refresh rate (N) burst rate

The number of state changes varies from one pattern to another, also tristate and mask patterns typically exhibit a very small average number of state changes per pattern, as compared to state patterns. Therefore, the “avgST” term of (9) is the worst case average number of state changes per pattern among the pattern types, namely: state, tristate, and mask. Again, (9) shows that the ETR is independent of the number of bursts, and dependent only on the refresh rate, the burst rate, and the average number of state changes (since N X B can be factored out

zontal compaction ratio is highest for a small number of state changes per pattern. The horizontal compaction ratio is approximately equal to one for 56 state changes in 512 test points. Figure 9 plots the effective throughput rate versus the average number of state changes for different values of N using the data of Fig. 4. Thus as the average number of state changes decreases, the ETR improves.

IV. VERTICAL COMPACTION A. Pin Electronics

A measure of the effectiveness of a variable-to-block coding scheme is the compaction ratio, which is propor- tional to the average number of code digits per source output. The state, tristate, and mask patterns are stored in compacted format on auxiliary memory and then transferred in compacted format to local memory. This reduces the required number of local memory refreshes, thus in- creasing total test throughput. The absolute data is con- verted to compacted format via a high-level software al- gorithm before it is stored on auxiliary memory. Real- time hardware data decompaction occurs as the stimulus patterns are burst to the UUT. The system has 512 test point interfaces with the UUT. The electronics for these test points are provided on 64 test points cards, all of which are refreshed simultaneously. This architecture is the same as Fig. 3 except that the memory configuration on each test point card is different. Each test point card has electronics for eight test points. Thus, each of four (optical) disk drives provides data for 16 test point cards. For each UUT test point interface, a fixed length code word is stored in memory to represent the string of ones and zeros behind the UUT pin. The fixed length code word will be 16 bits wide and, in order to keep the total amount of memory the same (for comparison purposes), the byte depth will be N/16 words. Each test point card contains 48 (N/16) x 8 bit memories for the state, tristate, and mask patterns.

B. Definitions and Formulas

by a 16 bit code word/l6. CV = vertical compaction ratio = # of bits represented

(10) (1 TP card/channel) X (8 TP’sITP card) X (48 X N/16 bits/TP/burst) X B

refresh rate ( N )/channel refresh time =

16 x CV x (N/16) x B burst rate

burst time =

16 x CV x (N/16) x B ETR =

1 x 8 x 48 x (N/16) x B 16 x CV x (N/16) x B + + refresh rate (N) burst rate

Now, assuming that interburst overhead is negligible as before, (12) reduces to of the numerator and denominator). This is valid only if

the number of bursts is an integer. The three pattern sets are refreshed simultaneously and then decompacted simultaneously. Figure 8 plots the horizontal compaction ratio ( CH ) versus the number of state changes (ST) from pattern X to pattern X + 1. It can be seen that the hori-

(13) CV

refresh rate ( N ) burst rate cv * + 24

ETR =


Mpaiierns/sec N - 192K

ETU

I .

o 5 I O IS 20 2s ao cv

Fig. 10. Effective throughput rate [ ETR] versus average vertical compaction ratio [CV].

Again, these formulas show the ETR to be indepeadent of the number of bursts and de-pendent only on the refresh rate, the burst rate, md the vertical compaction ratio. CY varies from one code word to another, alsa tristate and mask patterns typicatiy exhibit a very large w t i c d compaction Fatio. Therefore the term “CY” in (13) is the worst case a-ge vrrttical eampction ratio among state, tristate, and ma& p S e m s af a test point card. The number of bum sh gaL, be aa integer fan (13) to be

oohumff could improve the worst case vertical comphc64011 ratio fo ra t a t poia card. Op- timizing the vextic&I cowqmtion c t & ~ t d n i q u e would increase ttre vertbd c m j w t i o n ratio and oansequently ETR. Figure 10 plots the effective throughput rate versus the average vertical compaction ratio.

V. CONCLUSION that as the block size in-

decrease, and the ETR in- tant if the number of bursts

TR is data dependent. This r of bits refikshed by the

effect on h e effective

large. Studying UUT test nformation on how to test e of investigation can be

done in an automated manner with specialized software routines which analyze the compactibility of a pattern set.

Several computer simulations were carried out on some example test pattern sets of different sizes ranging from tens of patterns to thousands of patterns and the above conclusions were verified. Simulations also revealed that ETR increases as the number of patterns increase for both horizontal and vertical compaction. Sequential logic circuits typically have long pattern sets with a small average number of state changes per pattern. Combinational logic

given digital tepter architectures. Further study of interburst overhead is also in order. Data compaction decreases the number of refre

against the ??‘I% benefits.

REFERENCES

cuits,” I&%!? Spec&, p [8] M. Strieb, “Qpticd disk

Res. and Develop. Rep. C641, 1986, pp. 316-318.

Documents

Evaluation of effective throughput rate for certain ATE architectures with data compaction/decompaction