Laboratory 3 Build a ball counter

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ENGG 1203 Tutorial _03

Timing diagram of a DFF

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Lab 3Gate Timing

• difference timing for difference kind of gate, cost dependence

What is the difference between Combinationaland Sequential Circuit ?

(1) Setup Time = t2-t1

(2) Propagation delay = t3-t2

(3) Hold time = t4-t2

Sequential factor - TIME CLKhttps://www.semiconvn.com/home/hoc-thiet-ke-vi-mach/bai-hc-vi-mch/691-important-questions-related-to-timing-analysic-sta.html

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Draw a state transition diagram◦ An initial state◦ Other states to keep track of various activities◦ Transitions

Generate a state transition table and a output table◦ Write state transition table and output table in binary◦ State assignment, i.e., the code used for each state

Lab 3Steps in designing a State Machine

Derive canonical sum-of-product expressions◦ K map, Logisim…..

Draw the circuit◦ Register, State Transition Logic and Output Logic Circuit

Lab 3

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- State diagram

- Next state and output logic

- K-map, Logisim, simplification

- Design logic circuit

FPGA oretc..

Sequential Logic•Type of Flip Flop : RS, JK, D, T

•D flip-flop

http://www.electronics-tutorials.ws/sequential/seq_4.htmlhttp://www.rfcafe.com/references/electrical/flip-flop-table.htm 5 6

- Sequential logic- TIME

Q(t)

D

Q(t+1)

D Flip flop

Example :

Divide-by-2 counter

T Flip Flop

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T Flip flop

https://learn.digilentinc.com/Documents/2868

`

While T : 0, Q NOT ChangeT : 1, Q Change

Draw timing diagram of the following circuit

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Example 1Solution 1

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Solution 1

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DFF1 DFF2 DFF3

Which triggered by CLK ??

Note the trigger edge - CLK

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Example 2

Draw timing diagram of the following circuit

a’

Solution 2

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Consider Delay ?a’, Q1, b, Q2, c,.. -> d

Example 3 Which of the

following diagrams correctly describes the behavior of the following circuit, with a DFF ?

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Ans : A

Useful webb http://falstad.com/circuit/e-edgedff.html

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Type of FSM

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Moore and Mealy Machine

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Mealy MachineMoore Machine

Less gates….faster or slower ?

(Input /Output)

Less integratedSafer for use..

FSM design flow

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Start with counting states

Complete the State diagramrepresent in form of state transition tablesimilar to a truth-table

State encodingdecide coding for stateswork out the Boolean equation

Implementationflip-flop for state registercombinational logic for next state and output logic

Example 4

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From state transition diagram to truth table for the flow diagram

Four states Two-bit registers q / q* : Present / Next state Z : Output

Input (x) Output (z)

Mealy Machine : current state and inputMoore Machine : current state

From truth table to K-map

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DA DB DA DBA B

From K-map to circuit

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Logic for state transition

State register

Logic for output

Example 5

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Design a 2-bit counter with input x that can be◦ A down counter when x = 0

(…1110010011…)◦ A Johnson counter when x = 1

(…0001111000…)

DA DB DA DB

K-map to Circuit

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Example 6 : <110> pattern detector

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Design a state machine with input A and output B Minimize number of state Transition/output table Logic diagram with logic, output logic and memory

Ack : http://meseec.ce.rit.edu/eecc341-winter2001/341-2-6-2002.pdf

Solution 6 : State table and diagram

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Moore State Machine

Mealy State Machine : current state with input

output

input

Code the next state

Wait for the “0”11..11<110>

NEXT First ‘1’

Solution 6 : K map

B can be obtained from table

A : InputD1, D2 : next stateQ1, Q2 : current state

B : Output

Solution 6 : circuit

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Next state Logic state register output logic(Logic for transition) (memory)

Similarly, FSM for any pattern could be generated, TRY some

D1 = Q1Q2 + Q2AD2 = A

B = Q1Q2’

Example 7 When interfacing an external signal into the FPGA, it is possible that the internal digital signal may bounce between “1” and “0” when the external voltage is very close to the threshold voltage.  To solve this problem, a digital debounce circuit can be used.

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A simple debounce circuit operates as follows:◦ If the output is “0”, it is changed to “1” only after twoconsecutive “1”s have been present in the input.◦ If the output is “1”, it is changed to “0” only after twoconsecutive “0”s have been present in the input.

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The debounce (two times) logic is implemented as a state machine with the following states:

Draw a state transition diagram.◦ Input is din; Output is dout. ◦ Output of the state machine (dout) should be specified

within the state as it is a Moore machine.

Express the output dout in terms of s1 and s0.

Expected output from switch

Actual output from switch

State Encoding (s1 s0) Description

OUT0 00 Current output is “0”

OUT1 01 Current output is “1”

SEEN0 10 encountered a “0” but is not changing output yet

SEEN1 11 encountered a “1” but is not changing output yet

Solution 7

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Next state of OUT 0◦ din=0 OUT0◦ din=1 SEEN1

Next state of SEEN1◦ din=0 OUT0◦ din=1 OUT1

State Encoding (s1 s0) DescriptionOUT0 00 Current output is “0”OUT1 01 Current output is “1”

SEEN0 10 encountered a “0” but is not changing output yetSEEN1 11 encountered a “1” but is not changing output yet

Ex: OUT 0 OUT 1

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Next state logic….Current state din Next state dout

OUT0 0 OUT0 0OUT0 1 SEEN1 0OUT1 0 SEEN0 1OUT1 1 OUT1 1

SEEN0 0 OUT0 0SEEN0 1 OUT1 1SEEN1 0 OUT0 0SEEN1 1 OUT1 1

Current state S1 S0 din Next state ns1 ns0 doutOUT0 0 0 0 OUT0 0 0 0OUT0 0 0 1 SEEN1 1 1 0OUT1 0 1 0 SEEN0 1 0 1OUT1 0 1 1 OUT1 0 1 1

SEEN0 1 0 0 OUT0 0 0 0SEEN0 1 0 1 OUT1 0 1 1SEEN1 1 1 0 OUT0 0 0 0SEEN1 1 1 1 OUT1 0 1 1

dout = ns0 ⊕ ns1 K-map

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1 1 0 1 0= 1 (din s0)

0

dout 1 0 1

ns1

ns0

dout

Circuit

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TRY :If we have debounce for 3 times,

what should be added ? Split the state seen0 into seen0a and seen0b

seen1 into seen1a and seen1b……

** dout related to din ?Could it be NOT related ?

dout = ns0 ⊕ ns1 Example 8

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Combination LOCKMoving the knob

START from “1”, CW to 3,

CCW to 2 OPEN

OR TWO turns during “1” CW to 3

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Solution 8 : State DiagramAssume START at “1” ; RESET to STARTMoving the knob, arrow is the adjacent next numberStart, A, B… states.(1) Start(3) -> A (1) -> C (2)->OPEN

1 (START) CW 3 CCW1 CCW2 (OPEN)(1) Start(3) -> A(2) -> B (1) -> D (3) -> A (1) -> C (2) -> OPEN

1 (START) CW 3 CW 2 CW 1 CW 3 CCW 1 CCW 2 (OPEN)

Solution 8 : State Coding

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Total 7 states list for 8, one is dummy (not care)Input : 4

The states and input positions are encoded with 3 bits (s2 s1 s0) and 2 bits (p1 p0) respectively as shown below :

Solution 8 : Input/Output ports

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Implement the above lock control state machine in Logisim. Apart from the I/O described above, the FSM should also include CLK, and CLR

The following table summarizes the input/output ports of the state machine.

Truth table

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Example 8 a

- Extended Rotational Lock ( 1, 3, 2 ) could be OPEN by

EITHER (i) CW followed by CCW, <1> <3> 1 <2> <1> 3 2 1 <3> 1 <2> <1> 3 2 1 3 2 1 <3> 1 <2>………….

OR (ii) CCW followed by CW<1> 2 <3> <2><1> 2 3 1 2 <3> <2> <1> 2 3 1 2 3 1 2 <3> <2> ………….

With two turns from 1 to 3

Example 9 Traffic Light

Basic Light Control – State Transition Diagram◦ Begin by implementing the basic pedestrian light

control as a finite state machine.

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◦ To keep track of the light being displayed, it have determined the FSM can be in one of the four (4) states: 2 states for red (Red1, Red2), 1 state for green (Green), and 1 state for flashing green (Green Flash).

Example 9 : State Transition Diagram A timer signal t (CLK) serves as input to your FSM. ◦ The signal t is set to `1' for 1 clock cycle every 30

seconds. It is `0' otherwise. ◦ This signal controls the switching of light.

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The FSM produces 3 output : r, g, f. ◦ If g is set to `1', the green light is on. ◦ If r is set to `1', the red light is on. ◦ When f is set to `1', the light flashes, ◦ otherwise, the light stay solid.

For sake of hardware implementation, assume the clock is running at 1 Hz. ◦ The FSM resets to Red1.

The following table summarizes the I/O signals for the pedestrian light control :

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Type Name Descriptioninput t ‘1’ every 30 seconds have passed, ‘0’ otherwise.

output r ‘1’ to turn on red light, ‘0’ otherwise.g ‘1’ to turn on green light, ‘0’ otherwise.f ‘1’ to flash light, ‘0’ otherwise.

Next State and Output Logic The state encoding for the

four states is as followed :

Following is the truth table of the next state and output logic of the traffic light control state machine.

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State s1 s0RED1 0 0RED2 0 1

GREEN FLASH 1 0

GREEN 1 1

…… Logisim to have the circuit

K-map and circuitComplete with

K-map for Boolean expressions :◦ Next state : s0, s1, t ns1, ns0◦ Output : s0, s1, t r, g, f

Logic Circuits :◦ Memory : 2 DFF◦ Logic circuits : gates

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RECALL :Steps in designing a State Machine Draw a state transition diagram◦ An initial state◦ Other states to keep track of various activities◦ Transitions

Generate a state transition table and a output table◦ Write state transition table and output table in binary◦ State assignment, i.e., the code used for each state

Derive canonical sum-of-product expressions◦ K map, Logisim…..

Draw the circuit◦ Register, State Transition Logic and Output Logic Circuit

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Examples A Design Example - Traffic Lights

http://www.doc.ic.ac.uk/~dfg/hardware/HardwareLecture10.pdf

Finite state machine that recognizes the particular pattern http://pages.cs.wisc.edu/~markhill/cs252/Fall2009/handouts/hw4_sol.pdf

FSM with outputs http://www.math.uiuc.edu/~ash/Discrete/213Ch5.pdf

How To Design A Finite State Machine http://www.cs.princeton.edu/courses/archive/spring06/cos116/FSM_Tuto

rial.pdf

Finite State Machines http://web.mit.edu/6.111/www/f2012/handouts/L05.pdf

& MORE46

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