Embedded System Design Unit - 2_last 2 Topics_06!06!2013

8/12/2019 Embedded System Design Unit - 2_last 2 Topics_06!06!2013

1/51

Unit - 2PROCESSOR AND MEMORY ORGANIZATION

1


2/51

Processor selection for an embedded system Memor devices

Contents

Memory selection for an embedded system Memory map of a system Direct memory accesses

2


3/51

Types of MemoryMemory

RAM ROM

3

DRAM SRAM

SDRAM

ADRAM

DDRAM

PROM

EPROM

EEPROM

FLASH


4/51

Memory org nis tion

Systemspace

Codespace

ROMdata

IOspace

RAMdata

Heap Stack

0X

00000

0

0X

00040

0

0XFFFFFF

ROM implementationRAM implementation


5/51

System sp !e

Use" for e#!eption $e!tor t %&es Motoro& '() f mi&y reser$es *+2, mem &o! tions for

e#!eption $e!tor t %&e E#!eption $e!tors re r".ire" ""resses t t t e

pro!essor /ses to i"entfiy . i! !o"e s o/&" r/n . en iten!o/nters n interr/pt 0or1 ot er e#!eptions

T e system s/pports 23' "ifferent $e!tors E ! $e!tor !o&/mns - , %ytes


6/51

Co"e sp !e

Stores t e instr/!tion Norm &&y .e p& !e %ot system sp !e n" !o"e sp !e in

t e s me p ysi! & ROM


7/51

D t Sp !e

Rom " t sp !e stores !onst nt $ &/esE#

Error mess ges String &iter &s


8/51

A%o$e t e " t sp !e t e memory org ni4 tion%e!omes &ess reg/& r

More "epen"ent on r". re "esign !onstr int

T t is nee" not %e e# !t&y s s o.n in t e org ni4 tion"i gr m


9/51

T ree % si! re of re "5.ritestor ge nee" to %e i"entifie"

St !6 8e p


10/51

St !6

Use" to 6eep tr !6 of !/rrent n" && s/spen"e" e#e!/tion!onte#ts

Cont ins && &i$e &o! & or /tom ti! $ ri %&es 9 && f/n!tions

No interr/pt ser$i!e 9 no f/n!tion ! && .it o/t st !6 P& !e" in t e /pper en" of memory T e st !6 is gener &&y p& !e" t t e /pper en" of memory

%e! /se t e '() f mi&y p& !es ne. st !6 entries in"e!re sing memory ""resses; t t is< t e st !6 gro.s"o.n. r"s to. r"s t e e p


11/51


12/51

7ree memory

A&& st ti! &&y &&o! te" $ ri %&esE g

C St ti! > ri %&es

Any mo"ifi %&e $ ri %&e .it g&o% & &ife


13/51

T e 8e p

Dyn mi! &&y &&o! te" o%?e!ts n" $ ri %&es @in6e" " t str/!t/re m n e" % !om i&ers r/ntime

p !6 ge Not /se" in Em%e""e" systems


14/51

Unpop/& te" memory sp !e

It represents t e $ i& %&e ""ress sp !e nottt ! e" to ny memory

T ere is &ot of empty sp !e in memory m p A typi! & em%e""e" system mig t $e fe.

meg %ytes of ROM-% se" instr/!tion n" " t n"

per ps not er meg %yte of RAM


15/51

Memory

required

ase !"

Automaticc#ocolate

vendin$ m%c

ase &" Data

Acquisitionsystem

ase '" Di$ital

camera

Pro!essor /se" MC M/&tipro!essor MP

Se&e!tion of memory

Intern & ROM 5EPROM , to 2 )B ( )B -

Intern & EEPROM 23' 3*2 B 23' 3*2 B -

Intern & RAM 23' 3*2 B 23' 3*2 B -

ROM or EPROM"e$i!e

No No ', )B

RAM "e$i!e No ', 3*2 MB * MB

EEPROM or f& s"e$i!e

No ', 3*2 MB 7& s *' MB (GB15


16/51

Interf !ing of pro!essor< memory n" IO "e$i!es/sing memory system %/s

Interf !ing Using System B/s

System %/s inter!onne!tions for simp&e %/sstr/!t/re s t ree sets of sign &s System %/s "efines %y ""ress %/s< " t %/s< n"

!ontro& %/s A system-%/s interf !ing-"esign is !!or"ing to t e

timing "i gr ms of pro!essor sign &s< spee"< n".or" &engt for instr/!tions n" " t

16


17/51

Inter!onne!tions for simp&e %/sstr/!t/re

17


18/51

Pro!essor iss/es t e ""ress of t e instr/!tion %yteor .or" to memory system t ro/g t e ""ress %/s

A""ress B/s

Pro!essor e#e!/tion /nit< . en re /ire"< iss/es t e""ress of " t 0%yte or .or"1 to %e re " or .ritten

/sing t e memory system t ro/g ""ress %/s T e ""ress %/s of 2-%its /se" to fet! t e

instr/!tion or " t from n ""ress spe!ifie" %y 2-%itn/m%er

18


19/51

@et pro!essor t t e st rt reset t e progr m!o/nter t ""ress + T en t e pro!essor iss/es

E(AMPLE

""ress + on t e %/s n" t e instr/!tion t ""ress +is fet! e" from memory on reset @et pro!essor instr/!tion %e s/! t t it nee"s to

&o " register r* from t e memory ""ress M T epro!essor iss/es ""ress M on t e ""ress %/s n"" t t ""ress M is fet! e"

19


20/51

Instr/!tion fet! Pro!essor iss/es t e ""ress of t einstr/!tion< it gets % !6 t e instr/!tion t ro/g t e " t

Data )us

D t Re " en it iss/es t e ""ress of t e " t < it&o "s t e " t t ro/g " t %/s

D t rite en it iss/es t e ""ress of t e " t < itstores t e " t in t e memory t ro/g t e " t %/s A" t %/s of 2-%its fet! es< &o "s< or stores t e instr/!tionor " t of 2-%its

20


21/51

Pro!essor iss/es ""ress m for n instr/!tion< it fet! est e instr/!tion t ro/g " t %/s from ""ress m F7or 2-

E(AMPLE

<

Documents

Embedded System Design Unit - 2_last 2 Topics_06!06!2013