Electronics, Trigger and DAQ

M. Bruschi – INFN Bologna (ITALY)

1

Electronics, Trigger and DAQ

• General Architecture of the system for phase I

• Parts of the system which are already available/tested or in advanced design phase

• What is needed for phase I• The possible temporary solution for 2007• The calibration system• Conclusions


2

General Architecture of the system for phase I


3

LUCID Readout Goals• The basic operation of the LUCID electronics is to count the

track multiplicity per bunch crossing in the detector• The track multiplicity in a Cerenkov tube is proportional to

the light signal collected by a photosensitive device (in our case PMT or MAPMT)

• In the baseline readout scheme proposed for phase I the light produced in a single Cerenkov tube will be readout directly by a single PMT device and the amplitude and time of arrival of the signal will be used to count the detector track multiplicity.

• In the second readout scheme the light produced in a single tube will be split in many (up to 16) groups of quartz fibers connected to a MAPMT placed in a moderately low radiation area (5 Gy/year at highest lumi).

The LUCID information relevant to measure the luminosity of the experiment must be available:

1. in the global ATLAS triggered event2. in the online monitor3. to possibly form a trigger for interaction or high event

multiplicity rejection.


4

Readout Schemes for Phase I

LUCID Nose Sh. USA15~4m ~80-100 m

• Number of channels (per detector side): 16 PMT/ 1 MAPMT (4 ch.)

•The front end has been conceived as having as least components as possible for two reasons:

- short time to produce it (from April 2006)- it is deployed in an area that during is not easily accessible

LUCID+PMT

PMTFED

RODTRIGGER

LUCIDMAMPT

FED (MAROC)

coaxial Shielded Tw. Pair

Quartz Fibers ROD

TRIGGER

Shielded Tw. Pair/optical fibers

1)

2)


5

Baseline Readout Scheme Description• Signals from PMT are fed into a PMT FED card (formed by a PMT

mother card and PMT daughters cards both tested on Dec. 06) providing the necessary amplification. The differential output is sent to USA15 via twisted pair shielded cable

• The received analog signal is processed by a ROD CARD. The multiplicity per tube is evaluated by LUT combining time of arrival and amplitude information. The result of the processing is stored in pipeline to be read pending a L1A and sent directly to the trigger card

• The TRIGGER CARD processes the multiplicity from all the tubes and forms the LUCID trigger (interaction/high multiplicity rejection/ …). Online luminosity scalers are implemented in the logic and readout via VME. The processed data, stored in a pipeline, are sent to ROS pending a L1A and form part of the LUCID event.

• The design of the TRIGGER CARD is already started since it must be used also in another project expected to run this year (R&D on a fast tracking trigger for silicon devices)

• In case the ROD CARD were not available for the end of this year we propose a temporary readout solution for 2007 based on the TRIGGER CARD plus a VME based system. The online luminosity and trigger features would still be available while the system debugging would be performed via the VME QDC system (tested on Dec. 06)

• The feature of time arrival of the event readout will be in this case added to the system tested on Dec. 06 by means of a Constant Fraction Discriminator (CFD) card already in the production phase and of a VME TDC module


6

LUCID READOUT+TRIGGER (PHASE I)

PMT 1

ROD

PMT 16

MAMPTMAMPT

FED (MAROC)

4 diff. TX lines

GOL LINK+TTCRQ

TRIGGER

CARD

ROD

100 m

100 m

100 m

FED

USA 15

HV, LV, SLOW CONTROL

ROS

TTCRQ

TTCRQ

TTCRQ

To LVL1

VME IFOnLineLUMI

PMT FED


7

The FED CARDS

PMF: HV DividerSignal Routing MAROC chip

MAPMT FED

PMT MOTHER CARD

1 2 3 16

PMTDAUGHTER CARDS

In Out

PMT FEDAmplifier+Diff. Line Drivers

MAROC (ROMAN POTS):4 SUM OVER 16 CHANNELS (ANALOG OUT)64 THR. DISCRIMINATOR (DIGITAL OUT/GOL LINKS)

MRO


8

stru 1stru 2

stru 16

GOLRX

LVDSS/P

3

3

3

LVDS 1 (to trig. unit)




stru 2

TTCRQ i.f.opt. lnkfrom TTCEX

VME P1VME I.F

DPRAMDPRAM

DPRAM

CTRLLOGIC

6 Bytes

6 Bytes

6 Bytes

EVENTBUFFER

s-LINKto ROS

from CTRL LOGICfrom CTRL LOGIC

160 MB/s

s-LINK Busy

LUCID ROD CARD (2+2units ) – VME 9U

Analog_In 1

Analog_In 2

Analog_In 16

GOL_In 1

GOL_In 2

GOL_In 10

~200 Bytes/ev


9

Single Tube Readout Unit

20 nsint

5 nsreset

25 ns

time

LHC Clock

LHC Int. Time

ADC GATE

to thetrigger

unit

FanOut

GI+

ADC

Multiplicity per Tube

LUT

8

1

3

TUBE

LUT

(1 MB) 3

#1

#16

GOL

LINK

1/4 datafrom the MRO

DIFF. ANALOGINPUT (FROM FED)

STRU

CFD (Prog.

Thr+NR)

ADC GATE

RAW DATA TO READOUT per STRU ~ 6 Bytes/BC

12

20

Progr. GATE & DEL

LHC Clock

Note: the dashed components are usedonly for the MAPMT readout scheme


10

SignalBuffer

TTCRQ i.f.opt. lnkfrom TTCEX

VME P1VME I.F

CTRLLOGIC

s-LINKto ROS 160 MB/s

s-LINK Busy

LUCID TRIGGER CARD (1 unit ) – VME 9U

Detector

1

Detector

2

LVDS 1

LVDS 2

SignalBuffer

FPGA basedTRIGGER

PROCESSINGUNIT

5 ser. Inp60 bit/BC

5 ser. Inp60 bit/BC

to the L1 trigger

~40 Bytes/ev

FPGA:Algorithm Flexibility

LVDS 3

LVDS 4

LVDS 5

LVDS 1

LVDS 2

LVDS 3

LVDS 4

LVDS 5

ONLINELUMINOSITYSCALERS


11

Scalers in the Trigger Card (Firmware)

for Online Luminosity

LUCID A LUCID C

II. Particle Counting

I. Collision/Zero Counting

16 tubes

1

2

3

4

4 x 3564 x 32bit ~ 60kB (1-4 x BCIDs x Scaler depth) L

R

1

2 (If LUCID A-C Coincidence)

34 (If LUCID A-C Coincidence)

4 x 3564 x 32bit ~ 60kB

III. Total Orbit Counter • For normalization (Average)

• All scalers start/stop are synchronized with the Orbit signal to scale over the same interval at a BC precision• Scalers are incremented on L1A (for dead time correction) • Scalers read-out by VME and sent to DCS (~ 120 kB for each Luminosity Block –few min-) for processing, to be published at any time

32bit


12

The LUCID Data Flow

LUCID

Run Control• Luminosity Block

DCS

IS

CTP/LVL1• Dead-time• Pre-scale

LVL2 + EF• Pre-scale

ATLAS TDAQOffline Luminosity • Luminosity data stream

Control Room

Conditions DatabaseAnalysis

LUCID Trigger (X Hz)

L1A ~100 kHz (~1 kHz)

~200 Hz (~2 Hz)ROS…

S-link

Online Lum.Scalers (Ethernet)

Cross checks with CTP Monitoring

SBC

(VME)

LB (Ethernet)


13

Parts of the system which are already available/tested or in advanced design phase


14

The prototypePMT FED Test Board

MAPMT

PMT Inputs

MAPMT HV

ANALOG SIGNAL Outputs(18x4)

x10 x5

2ch Preamp+DriverPMT Daughter Card

Mother Card


15

The prototype TX-RX SystemTX system:

PMT Mother Card+ 36 Daughter Cards

x2÷4

PZ adj

Gain adj

DEC. 06 Test DAQ

7 VME RX cards

SBCCORBOQDCADCSCALER

ATLAS TDAQ-01-06-01

RX system:VME RX card8 channelsPZ adjGain adj


16

Signal Characteristics

PMT: R2496Cable length=100 mSource: Led pulses

The pole-zero correction performed bythe RX card to compensate for cable lossesworks properly

Cable length=100 mSource: Pulser


17

The Electronics GainMeasured at the Dec. 06 Test

BeamPMT

2QDCCH 2

PMT2 TX RX

QDCCH 2

100 m cable

S= 28.7 N=0.56

S= 345.2 N=6.7

GAIN=345.2/28.7~12

(S/N)=51.4 to be compared with 51.3

0

200

400

600

800

1000

1200

1400

0 100 200 300 400 500 600

Series1

Series2

Series3

Series4

Series5

Series6

Series7

Series8

Series9

Series10

Series11

Series12

Series13

Series14

Series15

No S/N worsening observed

Good linearity and uniformity of response


18

TDAQ-01-06-01 at the DEC. 06 Test Beam

During the December 2006 Test Beam we took data using the last version of TDAQand the following VME modules:1 SBC + Hard Drive (Standalone mode)1 CORBO (Trigger and Busy)2 CAEN QDC V7921 CAEN SCALER1 CAEN SEQUENCER V5512 CAEN ADC V550


19

The CFD card• We are producing (the design is

completed) a Constant Fraction Discriminator card which will be used:

1. to test the timing performances of the readout chain

2. as system block for the possible temporary solution in 2007 (see next)

• Each VME 6U card will handle 8 channels

CFD

ANALOG (TO QDC)

FROMVME RX CARDOUTPUT

LVDS (TO TDC)LVDS (TO TRIGGER CARD)NIM (AUXILIARY)


20

THE TRIGGER CARD (SLIM/LUCID)

•We merged the need of two projects (SLIM/LUCID) in a unique Trigger Card (EDRO)whose design is already started •The specific purpose of each project will be defined by the design of the Mezzanine (input signals routing) and of the FPGAs firmware

ALTERASTRATIX IIEP2S130F1508


21

What is Needed for phase IITEM STATUS AVAILABL

E

PMT FED: PMT mother card

TO BE MODIFIED

Spring ‘07

MAPMT FED:PMF

TO BE MODIFIED

Spring ‘07

MAPMT FED:MRO

DBT,DBR,DBF (PRODUCTION)ANB,DBB * (TO BE DESIGNED)

Spring ‘07

CFD card PRODUCTION Spring ‘07

TRIGGER card DESIGN STARTED

Fall ‘07

ROD card TO BE DESIGNED

2007/8

* NOT DIFFICULT DESIGN. MOSTLY SIGNAL ROUTING

MRO


22

The possible temporary solution for 2007(in case ROD card not available)

PMT 1

PMT 16

MAMPTFED

MAROC

4 diff. TX lines

TRIGGER

CARD

100 m

100 m

100 m

FED USA 15

HV, LV, SLOW CONTROL

ROS

TTCRQ

To LVL1

VME IFOnLineLUMI

3

RX

BOARDS

3

CFD

BOARDS

20

20

VMEQDC/TDC

•INTEGRATED ON TDAQ •ONLINE SCALERS •DEBUGGING VIA VME•MAROC DIGITAL PART NOT AVAILABLE


23

LED Calibration System - I• The readout chain gain will be measured

using a calibration system based on LED light.

• We tested already such a system during the past test beam

• The small amount of channels to be tested will allow to use the simple manual method used during the test beam

• An improved version (VME programmablesystem, fully automatic ) is under design


24

LED Calibration System - II

PULSER

Amplitude: ~ 4 V (variable in 10 mV steps)Duration: ~ 20 ns

Trigger Output (to the DAQ trigger logic)

Led amplitude adjusted to see the single photoelectron signal

LEDCARD

PMTOptical Fiber LUCID TUBE


25

Conclusions• An intense work for design and debugging the

electronics solutions for LUCID has been performed during the last year

• Tests on important elements for the FED and DAQ system of phase I have been successfully performed during the last test beam on December

• We are reasonably confident that the phase I detector can be run integrated in the ATLAS TDAQ starting from the end of this year providing valuable and unique information for the experiment online and offline luminosity determination


26

Backup Slides


27

Description of some of the building blocks of the readout electronics

OPERA MAROC CHIP • Adapted to LUCID needs from the RP design (ATLAS Orsay

group)

Gated Integrator + ADC • 8 bit for the total sum

should be enough • Contacts have been taken with the LHCb preshower group

(Clermont) for adapting their GI+ADC solution

LOGIC• Mainly Based on LUT• IMPLEMENTED on FPGAs • Flexible and robust

ENGINEERING• Integration in standard VME 9U


28

Fibers readout scheme description

• The high radiation dose level around LUCID in phase II suggests the possibility to transmit the light collected by the Cerenkov tubes on rad. hard quartz fibers (typ. ~60 fibers/tube grouped in up to 16 readout channel) to the front end electronics sitting on a low level irradiated area (nose shielding, 5 Gy/year)

• Charged tracks crossing the fibers at an angle off the fiber axis could produce unwanted light (background)

• The signals affected by this kind of background can be rejected by examining the pattern of hit fibers (and not only the total amount of light collected by the fibers)

• The front end chip developed by the ROMAN POT group (MAROC) to read MAPMT (8x8 matrix of readout channel) offers the possibility to produce, for each tube:

1. An analog signal proportional to the light produced in the cerenkov tube (this feature was added for LUCID)

2. A digital signal based on the fast discrimination of the single MAPMT readout channel (used to study the pattern of hit fibers)

No event

Signal event

Backgroundevent


29

The MAROC CHIP

Bipolar Fast Shaper

3 Discriminators

Buffer RC Slow Shaper

charge

V th0

trigger

1 0 p F 1 5 k

V th1

V th2

Vd d

Unipolar Fast Shaper

O T A

W idlar bufferHo ld 1

R e a d

T Z

O T A

x 1

C f: 3 0 fF

R f: 5 0 k

3 0 k

1 0 0 k3 p F

1 0 0 fF

1 5 01 5 k

2 p F

E N_s eria lis er*

V re f_HS TL

cm d_HS TL

cmd

_LU

CID

c urrent mirrors

c m d 0 à c m d 5 SUM

Variable Gain

Preamplifier

input

en

cod

er E N_s eria lis er

1 k

FS _c hoic e

FS _choice*

Ho ld 2R e a d

2 p F

EN_A DC H1H2_c hoic e

H1H2_c hoic e*W ilkinson

ADCOUT_ADC

c m d_S UM

LVDS /CMOS

cmd_LVDS

0

1

CK_CMOS_80MCK_80M

CK_80M*

EN_A DC

DC_FS

EN_CK

LUCIDANALOG

LUCIDDIGITAL

LUCIDSLOWCTRL

The MAROC chip design (ROMAN POT)has been modified in order to group up to 16 channel (ANALOG SUM)


30

LUCID FED (for MAPMT)


31

LUCID FED (for MAPMT)•The FED will sit in an areairradiated by 5 Gy/year at max.luminosity

•Nevertheless, also for phase I,all radiation tolerant componentshave been used(GOL, TTCrq, ELMB, voltageregulators LHC4913, FPGA Flash ACTEL APA andCPLD Xilinx XC9500)

•In the FPGAs, the Triple ModuleRedundancy logic has beenimplemented

•All the cards are in productionexcept the analog one (BUT:the basic analog circuit is alreadyproduced and tested)

•Prototype (with MAROC2) ready in spring


32

AVERAGE ANODE CURRENT DRAWN BY PMT IN PHASE I

19

19 6int

int

5 19 6int

int

5 19

1.6 10.

1.6 10 40 10. 3564

280810 1.6 10 3 5 40 10

. 3564

10 1.6 10 3 5 32

pe BCANODE PMT

pe BC

pe b BCPMT

pe BC

pe BC

pe BC

N NCoulombI G

N N s

N N k NCoulombG

N N N s

N N NCoulomb

N N N s

6

6

10

8 10

A

A

Total average current per tube: 8 A


33

AVERAGE ANODE CURRENT DRAWN BY MAPMT IN PHASE I

19

19 6int

int

5 19 6int

int

5 19

1.6 10.

1.6 10 40 10. 3564

280810 1.6 10 0.06 5 40 10

. 3564

10 1.6 10 0.0

pe BCANODE PMT

pe BC

pe b BCPMT

pe BC

pe BC

pe BC

N NCoulombI G

N N s

N N k NCoulombG

N N N s

N N NCoulomb

N N N s

6

9

6 5 32 10

160 10

A

A

10 fiber/tube (40 channel/MAPMT)

Total average current per tube: 1.6 A

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Electronics, Trigger and DAQ