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20. Feb. 2002, LTP 1
Electronics for the e experiment
• Short introduction and status• Trigger electronics• DAQ electronics• Slow Control
Developments useful for other experimentsDevelopments useful for other experiments
20. Feb. 2002, LTP 2
Search for e at 10-14
1m
e+
Liq. Xe ScintillationDetector
Drift Chamber
Liq. Xe ScintillationDetector
e+
Timing Counter
Stopping TargetThin Superconducting Coil
Muon Beam
Drift Chamber
MEG Detector
• LFV Process forbidden by SM
• oscillations expected to enhance LFV rate
• Present limit: 1.2 • 10-11 (MEGA)
• SUSY Theories: ~ 10-12
• LFV Process forbidden by SM
• oscillations expected to enhance LFV rate
• Present limit: 1.2 • 10-11 (MEGA)
• SUSY Theories: ~ 10-12
Required:
• stopping rate: 108/s
Resolutions (all FWHM):
• Ee: 0.7%
• E: 1.4% @ 52.8 MeV
• e: 12 mrad
• te: 150ps
Required:
• stopping rate: 108/s
Resolutions (all FWHM):
• Ee: 0.7%
• E: 1.4% @ 52.8 MeV
• e: 12 mrad
• te: 150ps
Ee = 52.8 MeV
Kinematics e= 180°
E = 52.8 MeV
e
20. Feb. 2002, LTP 3
Detector Design
2002
2003
2004
2005
2006
2007
Tests & Design
Assembly
Engineering Run
Data taking
.
.
.
20. Feb. 2002, LTP 4
Cryogenics Design
20. Feb. 2002, LTP 5
Status update• New xenon purification with SAES
mono-torr getter filter. Should reduce all non-noble gases to < ppb level
• Very low noise on PMTs (1mV peak-to-peak) 0.2% resolution when summing all 240 PMTs
• PMT gain equalized reproducible with LED method to ~3%, limited by HV stability
• Beam time at TERAS starts today
20. Feb. 2002, LTP 6
Trigger Requirements
Beam rate 108 s-1
Fast LXe energy sum > 45MeV 2103 s-1
interaction point e+ hit point in timing counter time correlation – e+ 200 s-1
angular corrlation – e+ 20 s-1
Beam rate 108 s-1
Fast LXe energy sum > 45MeV 2103 s-1
interaction point e+ hit point in timing counter time correlation – e+ 200 s-1
angular corrlation – e+ 20 s-1
Ee = 52.8 MeV
Kinematics e= 180°
E = 52.8 MeV
e
M.C.
e+
20. Feb. 2002, LTP 7
LXe energy sum
• Total ~800 PMTs
• Common noise contributes significantly to analog sum
• AC coupling Baseline drift
• How to evaluate of shower center?
• Total ~800 PMTs
• Common noise contributes significantly to analog sum
• AC coupling Baseline drift
• How to evaluate of shower center?
20. Feb. 2002, LTP 8
Digital Trigger• Commodity electronics available
– 100 MHz FADC 10 bit (10$)– FPGA 100k Gates, 90kB, 230 MHz, 300 pins
(100$)– SRAM 10ns, 128kB (30$)– LVDS 200Mb/s/line, (2$)– VME32/VME64
FADC
FPGAFADC
FADC SRAM
Trigger
…
PMT
PMT
PMT
20. Feb. 2002, LTP 9
Lat
ch
Lat
ch
Lat
ch
Lat
ch
Lat
ch
Baseline SubtractionBaselineSubtractionL
atch
10 bit
100 MHz Clock
-+
<thr
+
-
BaselineRegister
Uses ~120 out of 5000 logic cells
8 channels/FPGA use 20% of chip
Uses ~120 out of 5000 logic cells
8 channels/FPGA use 20% of chip
Baselinesubtracted
signal LUT10x10
Calibrated and
linearized signal
20. Feb. 2002, LTP 10
QT Algorithmoriginal
waveform
smoothed anddifferentiated (Difference Of
Samples)Threshold in DOS
Region for pedestal
evaluation
integration area
t• Inspired by H1 Fast Track Trigger (A.
Schnöning)
• Difference of Samples (= 1st derivation)
• Hit region defined when DOS is above threshold
• Integration of original signal in hit region
• Pedestal evaluated in region before hit
• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time
• Inspired by H1 Fast Track Trigger (A. Schnöning)
• Difference of Samples (= 1st derivation)
• Hit region defined when DOS is above threshold
• Integration of original signal in hit region
• Pedestal evaluated in region before hit
• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time
20. Feb. 2002, LTP 11
Finding center of shower
ε (|φ(center)-(max. PMT)| < 3.5°) > 99%
Enough to find PMT with max. value Enough to find PMT with max. value
20. Feb. 2002, LTP 12
Schema for max. finding
8
8
Latch
Latch B
A A<B
8
Index bit
8
8
Latch
Latch B
A A<B
8
Index bit
Latch
Latch B
A A>B
8
Index bit
LSB
MSB
index
value
20. Feb. 2002, LTP 13
e+ - coincidence
or
or
or
e+
counterLUT
> 45MeV
LUT
AND phi
e+ phi
Trigger
back-toback
other veto
LUTmaxPMT
LXeSum
20. Feb. 2002, LTP 14
Trigger latency
BS
BS
BS
BS
Max
Max
Max
.
.
.
T[ns] 0 50 100 110 120..200 220 230
>45MeV
e+
AND
10 stages = 1024 chn
. . .
ADC
ADC
ADC
ADC
.
.
.
20. Feb. 2002, LTP 15
VME Boards
VMEInterface(Cypress)
3.3V 2.5VFADC
LVDS
FPGA
SRAM
FADC
FADC
FADC
FADC
FADC
FADC
FADC
LVDS
FPGA
FPGA
FPGA
SRAM
VMEInterface(Cypress)
3.3V 2.5V
LVDS
FPGA
SRAM
LVDS
LVDS
LVDS
FPGA
FPGA
FPGA
SRAM
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Type1 Type2
8 channels
LVDS
8 channelsclck, clear 48 bits output
LVDS
LVDS
20. Feb. 2002, LTP 16
Board hierarchy
• 42 Type 1 boards for 600 channels
• 6 Type 2 boards (VME 9U)
• 3 VME crates (2x6U, 2x9U)
• Total latency 350ns
• Processing power 600 * 100 MHz * 10 bit = 75 GB/s
• “Golden Rule”: plan for FPGAs with 2x gates
• Totally re-programmable
• Estimated costs: 230k$
• Made by INFN, Pisa
• 42 Type 1 boards for 600 channels
• 6 Type 2 boards (VME 9U)
• 3 VME crates (2x6U, 2x9U)
• Total latency 350ns
• Processing power 600 * 100 MHz * 10 bit = 75 GB/s
• “Golden Rule”: plan for FPGAs with 2x gates
• Totally re-programmable
• Estimated costs: 230k$
• Made by INFN, Pisa
20. Feb. 2002, LTP 17
Prototype board
ADCSignal-
Generator DACFPGA
Peter Dick
20. Feb. 2002, LTP 18
DAQ Hardware Requirementsn
E[MeV]50 51 52
e
Micheledge
t
PMTsum
e
e
e
51.5 MeV
0.511 MeV
• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)
• Timely separated ’s need waveform digitizing > 300 MHz
• If waveform digitizing gives timing <100ps, no TDCs are needed
• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)
• Timely separated ’s need waveform digitizing > 300 MHz
• If waveform digitizing gives timing <100ps, no TDCs are needed
~100ns
20. Feb. 2002, LTP 19
Fast waveform Digitizing
VMEInterface(Cypress)
3.3V 2.5VFADC
LVDS
FPGA
SRAM
FADC
FADC
FADC
FADC
FADC
FADC
FADC
LVDS
FPGA
FPGA
FPGA
SRAM
8 channels
LVDS
8 channelsclck, clear 48 bits output
• Trigger boards can directly be used for Drift Chamber (10ns sampling 1ns interpolation 2-3ns chamber resolution)
• Waveforms stored in SRAM, sparcified readout via LVDS
• Calorimeter readout needs sampling with > 1GHz
Analog Waveform Domino Sampling Chip
2GHz 40MHz, 12 bit
DSC FADC FPGA
SRAM
20. Feb. 2002, LTP 20
Domino Sampling Chip
• 0.5 – 1.2 GHz sampling speed
• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 100 CHF/channel
Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout• < 100ps accuracy
20. Feb. 2002, LTP 21
Domino Ring Sampler (DRS)
• Free running domino wave, stopped with trigger
• Sampling speed 2 GHz (500ps/bin)
• Readout 40 MHz 12 bit
• 1024 bins 150ns waveform + 350ns delay
• Free running domino wave, stopped with trigger
• Sampling speed 2 GHz (500ps/bin)
• Readout 40 MHz 12 bit
• 1024 bins 150ns waveform + 350ns delay
input
20. Feb. 2002, LTP 22
Domino Celldomino enable
• “Tail-biting” mechanism to chop off domino wave
• Coupling in of Domino Start in all cells for homogeneity
• Minimal number of components in critical path
• Global Domino Enable
• Capacitor to slow down speed
• “Tail-biting” mechanism to chop off domino wave
• Coupling in of Domino Start in all cells for homogeneity
• Minimal number of components in critical path
• Global Domino Enable
• Capacitor to slow down speed
20. Feb. 2002, LTP 23
Domino Wave stability
NMOS=PMOSNMOS<PMOSw/o tail biting
NMOS<PMOSwith tail-biting
“starving” widened stable
20. Feb. 2002, LTP 24
Gate sampling
signal
trigger gate
500ps 50ps
• Domino stop only accurate by one cell (500ps)
• Need 50ps timing resolution
• Domino stop only accurate by one cell (500ps)
• Need 50ps timing resolution
Trigger gate samplingTrigger gate sampling
20. Feb. 2002, LTP 25
DAQ Board8
inpu
ts
triggergate
FADC
3 state switches
FPGA
SRAM
shift register
• 9 channels 1024 bins / 40 MHz = 230 ms acceptable dead time
• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Readout controller in FPGA (instead pattern generator)
• 9 channels 1024 bins / 40 MHz = 230 ms acceptable dead time
• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Readout controller in FPGA (instead pattern generator)
40 MHz 12 bitVME
Interface(Cypress)
3.3V 2.5V8 channel
DRS
TriggerInput
Board inter-connect
FPGA
FPGA
SRAM
SRAM
SRAM
SRAM
FADC
8 channelDRS
8 channelDRS
FADC
8 channelDRS
Trigger BUS(2nd level tr.)
20. Feb. 2002, LTP 26
Status DRS
• Simulation finished in AMS 0.35 process
• Layout started• Switch to 0.25 process• First version summer ’02• Readout with trigger
prototype board• Costs per channel:
~25$ (board) + 6$ (chip)
20. Feb. 2002, LTP 27
DAQ Muegamma
PMT
FADCFPGA
trigger
2GHz
40MHz
DC TriggerBoard
trigger
100MHz
DSC
TriggerBoard
CPU
CPU
LXee+
wiresstrips
Waveformor QT readout
DAQ board
Waveformor QT readout
Split andPreamplifier
optional2nd level trigger
20. Feb. 2002, LTP 28
“Redefinition” of DAQ
Conventional New
AC coupling Baseline subtraction
Const. Fract. Discriminator
DOS – Zero crossing
ADC Numerial Integration
TDCBin interpolation (LUT)
Wafeform Fitting
Scaler (250 MHz) Scaler (50 MHz)
Oscilloscope Waveform sampling
400 US$ / channel 50 US$ / channel
TDCDisc.
ADC
Scaler
Scope
FADC
FPGA
SRAM
DSC ~GHz
100 MHz
20. Feb. 2002, LTP 29
Applications in other experiments• Technology in house (pool)• Substitution of old electronics (ADC, Scaler,
Discriminators)• LVDS-NIM converter and VME necessary• Integration in new experiments
VMEInterface(Cypress)
3.3V 2.5VFADC
LVDS
FPGA
SRAM
FADC
FADC
FADC
FADC
FADC
FADC
FADC
LVDS
FPGA
FPGA
FPGA
SRAM
LVDS
PMTPMT
PMT
BeamCounters
calorimeter
ttrigger= 10ns
tTDC 1ns
20. Feb. 2002, LTP 30
Slow ControlHV
PC
RS
232
12345
Temperature, pressure, …
GP
IB
Valves
??? 15° C
heater
PLC
12:30 12.3
12:45 17.2
13:20 15.2
14:10 17.3
15:20 16.2
18:30 21.3
19:20 18.2
19:45 19.2
MIDASDAQ
Eth
ern
et
Terminal Server
20. Feb. 2002, LTP 31
Slow Control BusHV
Temperature, pressure, … Valves
heater
MIDASDAQ
20. Feb. 2002, LTP 32
LXe calorimeter HV requirements
• 12 stage bases @ 1000V• g = (U)12 1V accuracy = 1.2% gain
variation• Need <0.3V accuracy over full temperature
range• Low ripple• 1000 channels ~ 200k$ commercially• Fast readout for monitoring (RS232 would take
~3 min to read)
• 12 stage bases @ 1000V• g = (U)12 1V accuracy = 1.2% gain
variation• Need <0.3V accuracy over full temperature
range• Low ripple• 1000 channels ~ 200k$ commercially• Fast readout for monitoring (RS232 would take
~3 min to read)
20. Feb. 2002, LTP 33
Field Bus Solutions
• CAN, Profibus, LON available
• Node with ADC ~100$• Interoperatibility not
guaranteed• Protocol overhead• Local CPU? User
programmable?• How to integrate in HV
(CAEN use CAENET)
• CAN, Profibus, LON available
• Node with ADC ~100$• Interoperatibility not
guaranteed• Protocol overhead• Local CPU? User
programmable?• How to integrate in HV
(CAEN use CAENET)
Reinhard Schmidt
20. Feb. 2002, LTP 34
RS485 bus• Similar to RS-232 but
– Up to 256 (1/8 load) units can be connected to a single segment
– single line, half duplex– differential twisted pair– Segment length up to km
• MAX 1483 transceiver chip for HV control• MAX 1480 for opto decoupled applications• Use repeater to extend to many segments
20. Feb. 2002, LTP 35
Generic Node
• ADuC812 / C8051F000 Microcontrollers
• MAX 1483 Tranceiver• Flat ribbon connector• Power through bus• Costs ~30$• Piggy back board
• ADuC812 / C8051F000 Microcontrollers
• MAX 1483 Tranceiver• Flat ribbon connector• Power through bus• Costs ~30$• Piggy back board
B
RxD
9
INT
A
7
54
21
9
1
8
1 5
TC
KT
DI
TM
ST
DO
2
+3
V
4
A5 A4
1 1
P0.
2
TxD
1
P0.
4
B
+ 3V
-12V
+ 3V
6
0
3
2 2
1 6 2
1
+3
V
DG
ND
+1
2V
8
P 0
11.0
59 M
Hz
AG
ND
+3V
I/O _2
1 0
I/O _1
D E
A
RES
5V
in in
g nd g nd
/RS TP3 .4
+5VD G N D
J1
7
4
1
J1
+ 3V
J3
LED
+ 5V
0 6
+3
V
+3
V
2 2
SCS 200
A7 A6
J2
9
A2 A1
2J4
P0.
3
D I
R OR E
g nd
V c c
MAX1483
RE
SE
T
+ 5V
C 4 2 ,2uF
n c
in in
g nd
g ndn c
1 o ut
n c
8in
g nd
78L03
+ 12V
C 7 2 ,2uF
P 1
+5V
D G N D
56
23
0
P 2
4K
7R
2
1
AG
ND
-12
V
AV
+ AG
ND
1 2 .10 .2001
S C S 200
R .S CH M ID T
A0
1 o ut 8n c
C 6 2 ,2uF
RE
SE
T
C1
22
,2u
F
C9
27p
F
C 10 2 ,2uF
79L12V R 3
78L12
V R 1
J2
A3
C 3 2 ,2uF
V R 2C 2 2 ,2uF
C 1 2 ,2uF
+ 15V
-15v
4K 7R 1
Pau l-Scherrer-InstitutCH-5432 Villigen / PSI
C 112 ,2uF
C8
27p
F
C 5 2 ,2uF
17
AV
+
20
/RS
T6
2V
DD
23
P3
.35
9P
1.7
26
P3
.05
6P
0.7
29
TD
O5
3P
2.3
32
P1
.55
0P
0.5
1 6AV +
1 3A IN 6
1 0A IN 3
7A IN 0
4C P 0 +
1C P 1 -
3 3 P 2 .0
3 6 P 1 .2
3 9 P 0 .0
4 2 P 0 .1
4 5 P 3 .7
4 8 P 0 .3
19
XTA
L2
18
XTA
L1
1 5A G N D
1 2A IN 5
9A IN 2
6V R E F R
5A G N D
8A IN 1
11A IN 4
1 4A IN 7
63
DA
C1
64
DA
C0
3C P 0 -
2C P 1 +
22
TC
K
25
P3
.1
28
TD
I
31
VD
D
24
P3
.2
27
P2
.1
30
DG
ND
60
P1
.6
57
P3
.5
54
P2
.2
51
P2
.5
55
P0
.6
58
P3
.4
52
P2
.4
3 4 P 1 .4
3 7 P 1 .1
4 0 V D D
4 3 P 2 .7
3 5 P 1 .3
3 8 P 1 .0
4 1 D G N D
4 6 P 3 .6
4 7 P 0 .2
4 4 P 2 .6
21
TM
S6
1D
GN
D
49
P0
.4
6051F000
U 1
20. Feb. 2002, LTP 36
2 versions
• Generic node with signal conditioning (OP-AMPs)
• Sub-master with power supply and PC connection (Parallel Port, USB planned)
• Integration on sensors, in crates• RS232 node planned
BUS OrientedBUS Oriented
Crate OrientedCrate Oriented
• 19” crate with custom backplane• Generic node as piggy-back• Cards for analog IO / digital IO / temperature /
220V / …• Crate connects to parallel port (USB planned)
20. Feb. 2002, LTP 37
Protocol• Asynchronous 345 kBaud• 16-bit addressing (65536 nodes)• CRC-code for error detection• Optional acknowledge• Concept of channels and configuration
parameters (256 each per node)
• Asynchronous 345 kBaud• 16-bit addressing (65536 nodes)• CRC-code for error detection• Optional acknowledge• Concept of channels and configuration
parameters (256 each per node)
command LSB MSB CRC
address command
command channel value CRC
write data
node
param1
param2
param3
channel1
channel2
channel3
ADC
ADC
port
1 Byte
20. Feb. 2002, LTP 38
Midas Slow Control Bus• 256 nodes, 65536 with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, voltage output,
TTL IO, 220V output, available from pool on request• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Connects to parallel port, USB planned• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and
regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network
http://midas.psi.ch/mscb
• 256 nodes, 65536 with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, voltage output,
TTL IO, 220V output, available from pool on request• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Connects to parallel port, USB planned• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and
regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network
http://midas.psi.ch/mscb
20. Feb. 2002, LTP 39
LabView Logger• Used for POLDI
detector HV and gas monitoring
• Graph, logging and alarm notification
20. Feb. 2002, LTP 40
High Voltage System
20. Feb. 2002, LTP 41
HV performance• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high
accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels,
crates with 192 channels• 30$/channel
• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high
accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels,
crates with 192 channels• 30$/channel
Prototype
20. Feb. 2002, LTP 42
Conclusions
• Lots of new electronics for Muegamma• Can be useful for other experiments• Knowledge and support in-house• Open to suggestions and modifications
• Lots of new electronics for Muegamma• Can be useful for other experiments• Knowledge and support in-house• Open to suggestions and modifications
Credits to Reinhard Schmidt and Peter DickCredits to Reinhard Schmidt and Peter Dick
20. Feb. 2002, LTP 43
Muegamma Web Site
http://kochbuch.unix-ag.uni-kl.de/bin/rezept?17731http://kochbuch.unix-ag.uni-kl.de/bin/rezept?17731
http://meg.psi.ch/doc/talks/s_ritt/feb02_psihttp://meg.psi.ch/doc/talks/s_ritt/feb02_psi
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