Electronics Ch10

8/12/2019 Electronics Ch10

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CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

Chapter Outline10.1 The Two-Stage CMOS Op Amp

10.2 The Folded-Cascode CMOS Op Amp

10.3 The 741 Op-Amp Circuit

10.4 DC Analysis of the 74110.5 Small-Signal Analysis of the 741

10.6 Gain, Frequency Response, and Slew Rate of the 741

10.7 Modern Techniques for the Design of BJT Op Amp

NTUEE Electronics L.H. Lu 10-1


2/21

10.1 The Two-Stage CMOS Op Amp

Multi-stage amplifiersPractical transistor amplifiers usually consist of a number of stages connected in cascade

Input stage:

High input resistance to avoid signal loss due to high-resistance source

Voltage gain

Large CMRR for differential amplifiersMiddle stages:

Voltage gain

Shifting of the dc level for required voltage swing

-


Output stage: Low output resistance to avoid loss of gain due to low-resistance load

Current supply required by the load

Sufficient voltage swing required by the load

Small-signal approximation may not apply


3/21

Circuit ConfigurationMost widely used op amp in VLSI circuits

Bias circuit:IREFand Q8Input stage: Q1-Q5 Active-loaded MOS differential pair

Differential input and single-ended output Provides voltage gain and high input resistance

Output stage: Q6-Q7 Active-loaded common-source amplifier

High output resistance (not suitable for low-impedance loads)DC arrangement:

The bias current of the input differential pair is provided by Q5 The bias current of the second stage is provided by Q7 To avoid systematic (predictable) offset:


5

7

4

6

)/(

)/(2

)/(

)/(

LW

LW

LW

LW


4/21

Input common-mode range and output swingThe transistors are supposed to be in saturation for proper circuit operation

ICMR:

Output swing:

Voltage gain

Low-frequency small-signal gain:

513 OVOVtpDDICMtptnOVSS VVVVVVVVV

76 OVDDOOVSS VVvVV

)||(

||

421111

421

211

oomm

oo

mmm

gG

rrgRGA

rrR

ggG

Amplifier prototype:

Input resistance:

Output resistance:

Transconductance:

Common-mode rejection ratio:


)||()||(

)||(||

76642121

766222

762

oomoomv

oomm

oo

rrgrrgAAA

rrgRGArrR

6421 )||( moomm grrgG

iR

76 || ooo rrR

SSmoom RgrrgCMRR 3421 2)||(


5/21

Frequency responsePoles and zeros

C

mZ

mP

Cm

P

Lgddbdb

gsdbgddbgd

C

Gf

C

Gf

CRGR

f

CCCCC

CCCCCC

21

2

22

221

1

7762

644221

2

1

2

1

1

2

1

fP2 decreases for a capacitive load

May result in stability issue

Unity-gain frequency for a dominant pole case

and

Phase margin


C

mPvt

C

GfAf 11

2

1

21 mm GG 2

21

C

G

C

G m

C

m

)/(tan)/(tan90180

)/(tan)/(tan90

)/(tan

)/(tan

1

2

1

12

1

1

21

2

ZtPttotal

ZtPttotal

ZtZ

PtP

ffffPM

ffff

ff

ff


6/21

Phase margin improvement technique Adding a series resistance in the feedback path

The zero is defined by

The zero can be moved toward higher frequencies for better phase margin

Slew rate

Slew rate is defined as the maximum voltage change rate at output

222

1 imi VG

sCR

V

RG

C

s

m

C

2

1

1

C

Extreme cases: Limited by bias current of Q5 (typical case): SR =I/CC Limited by bias current of Q7: SR =I7/CC

Relationship between SR andft SR = 2ftVOV= tVOV

Slew rate is determined by the overdrive voltagefor a given unity-gain frequency

PMOS devices are preferred for the differential pair

with a fixed current I at the cost of lower gain



7/21

Power-supply rejection ratio (PSRR)PSRR is defined as the ratio of the amplifier differential gain to the gain from the supply voltage

Design trade-offs

CMOS two-stage op amp performance is determined by

The channel length of the MOSFETs

sso

idod

ddo

idod

vv

vv

A

APSRR

vv

vv

A

APSRR

/

/

/

/

Performance benefit for a larger channel length: gain, CMRR, PSRR

Performance benefit for a smaller overdrive voltage: gain, CMRR, PSRR, ICMR, output swing and offset

Performance benefit for a larger overdrive voltage: high-frequency characteristics (gain)

For modern submicron CMOS technologies:

Typical VOVbetween 0.1 to 0.3 V

Channel length is at least 1.5 to 2 times minimum length (Lmin)


2

5.1

2

1

2

1

L

V

CC

gf OVn

gdgs

mT


8/21

10.2 The Folded-Cascode CMOS Op Amp

Circuit ConfigurationCascode topology to increase the gain of the input differential pair

Folded topology to improve the ICMR and to reduce the required supply voltage

Is generally considered a single-stage amplifier

Also called operational transconductance amplifier (OTA)

DC bias:

Bias current for Q1-Q2 isI/2

Bias current for Q3-Q8isI/2 IBIB can be realized by MOS current mirrors



9/21

Input common-mode range and output swingICMR:

Output swing:

Voltage gain

High voltage gain due to increased output resistance

Not desirable for applications where low output resistance is needed for the op amp

tnOVDDICMtnOVOVSS VVVVVVVV 9111

41075 OVOVDDOtnOVOVSS VVVvVVVV

)}(||)]||({[

)(||)]||([||

866102442

8661024464

21

oomooommomv

oomooomooo

mmm

rrgrrrggRGA

rrgrrrgRRR

ggG

requency response

Dominant pole at the output node

Excellent high-frequency response

Slew rate

The slew rate is limited by the bias current I and the load CL

Slew rate SR =I/CL = 2ftVOV1 forIB >I

TypicallyIB is set 10% ~ 20% larger thanI


oL

om

id

o

RsC

RG

V

V

1 L

mt

C

Gf

2

1


10/21

Increasing the ICMR: rail-to-rail input operationNMOS and PMOS differential pairs in parallel

ICMR exceeds the power supply voltage

Differential output voltage provided

ICM in the middle:

Both pairs operate simultaneouslyAv = 2GmRo

ICM near supply voltage:

Only one of the pairs is operational

Increasing the output voltage range: wide-swing current mirror

Modified cascode current mirror

Output swing increased by VtOutput resistance remains the same

A proper dc bias voltage VBIASis needed



11/21

The BJT DeviceHigh-frequency hybrid- model:

The base-charging or diffusion capacitance Cde:

The base-emitter junction capacitance Cje:

The collector-base junction capacitance C:

T

CFmFde

V

IgC

02 jje CC

m

CB

V

V

CC

0

1

The cutoff (unity-gain) frequency:


c

T

CmT

mfe

m

b

c

fe

bb

mc

VCC

I

CC

gf

rCCsrCCs

rgh

CCsr

sCg

I

I

h

sCsCr

ICCrIV

VsCgI

)(2

1

2

1

)(1)(1

)(/1

/1)||||(

)(

0


12/21

8.3 The 741 Op-Amp Circuit

741 Op-AmpDevice parameters:

npn:IS= 10-14 A, = 200, VA = 125 V

pnp:IS= 10-14 A, = 50, VA = 50 V



13/21

Bias circuit: Reference current generated by Q11, Q12 andR5 Bias for input stage: Widlar current source (Q10, Q11 andR4) and current mirror Q8, Q9 Bias for second stage: current mirror Q12, Q13B (Q13 is a two-output current source)

Bias for output stage: current mirror Q12, Q13A /Q18-Q19provides 2VBEdrop between VB14 and VB20

Input stage: (Q1-Q7,R1-R3) Input emitter follower (Q1-Q2): high input resistance

Current-mirror load (Q5-Q7,R1-R3):high output resistance and differential to single-ended conversion

Level shifting (Q3 and Q4): for required voltage swing and dc level at the input of the second stage

Second sta e: - R -R

Emitter follower Q16for high input resistance Common-emitter Q17for voltage gain

Miller compensation technique by CCOutput stage: (Q14, Q20)

Complementary pair Q14 and Q20

Low output resistance Relatively large load current without dissipating a large amount of power

Emitter follower Q23 to increase input resistance of the output stage

Short-circuit protection circuitry Q15, Q21, Q24, Q22,R6,R7,R11



14/21

10.4 DC Analysis of the 741

Reference bias currentProvided by Q11, Q12 andR5

IREF= 0.73 mA (for VCC= VEE= 15 V)

Input-stage biasWidlar current source Q11, Q10 andR4:

5

1112 )(

R

VVVVI EEBEEBCCREF

410

10

ln RII

IV C

C

REFT

C10 =

Current mirror Q8and Q9:

IC1 =IC2IC3 =IC4 = 9.5 A

Q1-Q4 and Q8-Q9 form a negative feedback loop

Bias current can be stabilized by the negative feedback


10

2

/21

2C

PP

III


15/21

Current-source load Q5-Q7andR1-R3

IC7= 10.5 A

Input bias current and offset currents Input bias current:

IB = 47.5 nA

3

2

3

2677

65

)/ln(22

R

IRIIVI

R

IRVIII

III

ST

N

BE

N

EC

CC

N

BBB

IIII

221

nput o set current:

Non-zero input offset due to mismatches in thevalue

Input common-mode range:

Input common-mode voltage over which the input stage remains in the linear active mode

The upper end limited by saturation of Q1 and Q2 The lower end limited by saturation of Q3 and Q4


21 BBOS III


16/21

Second-stage bias

IC17IC13B = 550 A

VEB17= 618 mV andIC16= 16.2 A

Output-stage bias

DC for Q23:

S

CTBE

REFBCC

I

IVV

III

1717

1317

ln

75.0

9

17817171616

R

VRIIII BEEBEC

IC23 180 A (IB23 3.6 A negligible forIC17)

DC for Q18-Q19:

IC18 165 A andIC19VBE18/R10 +IB18= 15.8 A

DC for Q14 and Q20:

VBB = VBE18+ VBE19 = 588 mV + 530 mV = 1.118 V

IC14 =IC20 = 154 A (forIS14 =IS20 = 310-14 A)


REFEC III 25.02323

S

CTBE

BEREFC

I

IVV

RVII

1818

101818

ln

/25.0


17/21

10.5 Small-Signal Analysis of the 741

The input stageDifferential input resistance:

re = 2.63 k andRid= 2.1 M

Transconductance:

Gm1 = 0.19 mA/V

eNid

eie

rR

rvi

)1(4

)4/(

112

1

2

2m

ei

e

i

om g

rv

i

v

iG

Ro4 = ro4[1 + gm4(re4||r2)] = 10.5 M

Ro6= ro6[1 + gm6(R2||r6)] = 18.2 M

Ro1 =Ro4||Ro6= 6.7 M

Equivalent circuit for the input stage:


)]||(1[ rRgrR emoo


18/21

The second stageInput resistance

Ri2 4 M

Transconductance

)]})(1(||[){1( 81717916162 RrRrR eei

179172

1796

179217

817

1717

||

||

||

icm

ie

iib

e

bc

RRiG

RRr

RRvv

Rr

vi

Gm2 = 6.5 mA/V

Output resistance

Ro2 = 81 k

Equivalent circuit for the second stage:


17968172 ieei

)]}||(1[{|||| 81717171317132 RrgrrRRR moBooBoo


19/21

The output stageOutput voltage limits

approximately 1 V below VCCand 1.5 V above VEE

Input resistance (forRL = 2 k, IC20 = 5 mA andIC14 =0)

Rin3 3.7 M

-

2023min

14max

EBEBCEsatEEO

BECEsatCCO

VVVVv

VVVv

)||()||)(1(

)1(

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20202020

AoiAoiin

LLi

rRrRrR

RRrR

Transconductance


12

3 LRo

ovo

vvG

20

20

0

3

3

2023233

1m

e

R

i

om

bebi

grv

iG

vvvv

L


20/21

Output resistance

Rout 34

Equivalent circuit for the output stage

11

||

1

20

2320

20

132320

23

22323

oe

Aooeout

oeo

Rr

rRrR

RrR

Output short-circuit protection

One of the two output transistors could conduct

a large amount of current if output is short-circuited

Short-circuit protection is adopted in the 741 op amp

For current source case (IC14 > 20 mA)

VBE15 > 540 mA

Q15 turns on and takes away the base current of Q14IC14 is limited as the base current is reduced

Similar case for current sink case (IC20 >20 mA)



21/21

10.6 Gain, Frequency Response and Slew Rate of the 741

Small-signal gain

Av = 243147 V/V = 107.7 dB

Frequency response

outL

Lvoomiom

o

o

i

o

i

i

i

ov

RR

RGRGRRG

v

v

v

v

v

v

v

vA

322211

22

22 ))(||(

Pt

tin

P

iot

Cin

fAf

RCf

RRRACC

0

21

2

1

2

1

|||)|1(

fP

= 4.1 Hz

ft= 1 MHz

Slew rate

SR = 0.63 V/s

Relationship betweenftand slew rate

Slew rate of MOS opamp with sameftis 2~3 times higher than the 741

Gm-reduction method: total bias current is kept constant with reduced Gm1


CC

ISR

2

tTVSR 4

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Electronics Ch10