Electronic System Level

Design

Data Types

in SystemC

Maziar Goudarzi

2009 ESL Design 2

Today Program

Bit-accurate data types provided by SystemC

2009 ESL Design 3

Data Types

SystemC data typesSingle-bit Typessc_bit, sc_logic

Integer Typessc_int, sc_uint, sc_bigint,

sc_biguint

Bit-Vector Typessc_bv, sc_lv

Fixed-Point Typessc_fixed, sc_ufixed, sc_fix, sc_ufix

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Data Types (cont’d)

Defined for all types

Streaming operator defined for all typesostream& operator << ( ostream&, T );

Examplesc_bit b;

cout<<b;

Trace functionsc_trace(<trace-file pointer>, <traced variable>,

<string>)

Example

sc_bit b;

sc_trace( tf, b, “message”);

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Single-bit Types

sc_bit

Two-valued logic: ‘0’ , ‘1’ (character literal)

Example:sc_bit b;

b=„1‟; // the same as b=1 or b=true

b=„0‟; // the same as b=0 or b=false

Defined operators

Bitwise: &(and) |(or) ^(xor) ~(not)

Assignment: = &= |= ^=

Equality: == !=

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Single-bit Types (cont’d)

sc_logic

Four-valued logic: ‘0’, ‘1’,‘X’,‘x’,‘Z’,‘z’ (char. literal)

‘x’ means unknown or indeterminate value

‘z’ means high impedance or floating value

Example:sc_logic l;

l=„0‟; // the same as l=0, false, sc_logic_0

l=„1‟; // the same as l=1, true, sc_logic_1

l=„z‟; // the same as l=2, sc_logic_Z

l=„x; // the same as l=3, sc_logic_X

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Single-bit Types (cont’d)

sc_logic (cont’d)

Defined operators

Bitwise: &(and) |(or) ^(xor) ~(not)

Assignment: = &= |= ^=

Equality: == !=

2009 ESL Design 8

Single-bit Types (cont’d)

Any mixture of sc_bit, sc_logic, and booltypes in comparison and assignments is possible, except:

sc_logic k;

sc_bit b; // or bool b

k = „z‟; // or k = „x‟

b = k; // Result is undefined.

// Run-time warning is issued

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Example: 3-state buffer

SC_MODULE(tristate_buf){

sc_in< sc_bit > input;

sc_out< sc_logic > output;

sc_in< sc_bit > enable;

void process() {

sc_bit in, en;

sc_logic out;

in=input; en=enable; // reading inputs to temporary variables

if(en)

out = in;

else

out = 'z';

output = out; // writing a temporary variable to output

}

SC_CTOR(tristate_buf) {

SC_METHOD(process);

sensitive<<enable<<input;

}

};

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Integer Types:

Fixed Precision

Fixed Precision Unsigned and Signed Integers

Integer variables with fixed width (number of bits)

sc_int<n>, sc_uint<n>

1<= n <=64

Signed representation uses 2’s complement

Underlying implementation: 64 bit integer

-D_32BIT_ compiler directive

Can freely be mixed with C++ integers (int, short, long)

2009 ESL Design 11

Fixed Precision Integers

(cont’d)

Defined operators

Bitwise ~ & | ^ >> <<

Arithmatic + - * / %

Assignment += -= *= /= %=&= |= ^= =

Equality == !=

Relational < <= > >=

Auto-inc/dec ++ --

Bit Select []

Part Select .range(,)

Concatenation (,)

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Fixed Precision Integers

(cont’d)

Examples:

sc_logic mybit;

sc_uint<8> myuint;

mybit = myuint[7];

sc_uint<4> myrange;

myrange = myuint.range(5,2);

sc_uint<12> my12int;

my12int = (myuint, myrange);

2009 ESL Design 13

Fixed Precision Integers

(cont’d)

sc_uint<8> u1, u2;

sc_int<16> i1, i2;

u1 = i1; // convert int to uint

i2 = u2; // convert uint to int

// BUG! in SystemC 2.0 User‟s Guide

2009 ESL Design 14

Integer Types:

Arbitrary Precision Integers

Integers with (virtually) no width limit

MAX_NBITSdefined in sc_constants.h

sc_bigint<n>, sc_biguint<n>

Signed representation uses 2’s complement

Operators are the same as sc_int, sc_uint

Can be intermixed with sc_int, sc_uint,

and C++ integer types

2009 ESL Design 15

Bit-Vector Types:

Arbitrary Length Bit Vector

Arbitrary Length Bit Vector

Vector of 2-valued bits

sc_bv<n>

No arithmetic operation

Assignment: String of ‘0’ and ‘1’ chars

Reduction operationsand_reduce(), nand, or, nor, xor, xnor

sc_bv<6> databus;

databus = “100100”;

sc_logic result;

result = databus.or_reduce();

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Arbitrary Length Bit Vector

(cont’d)

Defined operatorsBitwise ~ & | ^ >> <<

Assignment = &= |= ^=

Equality == !=

Bit Select []

Part Select .range(,)

Concatenation (,)

Reduction and_reduce() or_reduce()xor_reduce() …

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Arbitrary Length Bit Vector

(cont’d)

Examples:sc_bv<16> data16;

sc_bv<32> data32;

data32.range(15,0) = data16;

data16 = (data32.range(7,0), data32.range(23,16));

(data16.range(3,0),data16.range(15,12)) =

data32.range(7,0);

sc_bit y;

sc_bv<8> x;

y = x[6];

sc_bv<16> x;

sc_bv<8> y;

y = x.range(0,7);

2009 ESL Design 18

Arbitrary Length Bit Vector

(cont’d)

Arithmetic operations not directly supported

sc_bv<8> b8=“11001010”;

sc_uint<8> u8;

u8=b8;

u8+=5; // or any other arithmetic

b8=u8;

2009 ESL Design 19

Bit-Vector Types:

Arbitrary Length Logic Vector

Arbitrary Length Logic Vector

Vector of 4-valued bits

sc_lv<n>

No arithmetic operation

Any ‘x’ or ‘z’ in the RHS: runtime warning + undefined result

Assignment: String of ‘0’, ‘1’, ‘x’, ‘z’ chars

Operators are the same as sc_bv

2009 ESL Design 20

Arbitrary Length Logic Vector

(cont’d)

Example:

sc_lv<8> bus1;

if(enable)

bus1 = “01xz10xx”;

else

bus1 = “zzzzzzzz”;

cout<<bus1.to_string(); // OR: cout<<bus1

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Example: A Memory Module

#define DATA_WIDTH 8

#define ADDR_WIDTH 4

SC_MODULE(memory) {

sc_in< sc_bit > chipEnable;

sc_in< sc_bit > readWrite;

sc_inout< sc_lv<DATA_WIDTH> > dataBus;

sc_in< sc_lv<ADDR_WIDTH> > addrBus;

sc_uint<DATA_WIDTH> memArray[2^ADDR_WIDTH];

void process() {

if ( chipEnable.read()=='0') {

dataBus.write( "zzzzzzzz" );

return;

}

sc_lv<ADDR_WIDTH> addr_lv = addrBus.read();

sc_uint<ADDR_WIDTH> addr = addr_lv;

if (readWrite.read()=='1')

dataBus.write( memArray[addr] );

else

memArray[addr]=dataBus.read();

}

SC_CTOR(memory) {

SC_METHOD(process);

sensitive<<chipEnable<<readWrite<<dataBus;

// Also: initialize memArray to zero

}

};

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Fixed-Point Types

Usage

HW implementation of Floating-point arithmetic

MantissaS Exponent

Floating point representation

(2’s complement) binary value

Fixed point representation

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Fixed-Point Types (cont’d)

Advantages

Less area

More speed

Disadvantages

Narrower representable range of numbers

Uniform resolution over entire range

Problems to be addressed

Overflow

Quantization

Your Reading Assignment!

Data Types in

SystemC

Complementary Issues

Regarding Data Types

2009 ESL Design 25

Complementary Issues

Simulation Speed Issues

User Defined Type Issues (future lectures)

Equality-check Operator

Tracing a User-Defined Type

2009 ESL Design 26

Speed Issues:

Integer Types

sc_bigintsc_biguint

sc_intsc_uint

C++Types

sc_intsc_uint

with -D_32BIT_with

MAX_NBITSnot defined

with MAX_NBITS

defined

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Speed Issues:

Bit and Logic Types

sc_logicsc_bit

sc_lv sc_bv

2009 ESL Design 28

What we learned today

Hardware-centric data types in SystemC

Reading Assignment:

Fixed-point data types

Chapters 6 and 8 of SystemC Users’ Guide

Assignment 2

Design a parameterized shared bus system

Due date: next Sunday (Aban 3rd)