Design Verification Using SystemC

DV Club, Boston

Experiences with SystemC

Design Verification Using SystemC

Greg Tierney

Presented toDV Club, BostonMarch 5, 2007

DV Club, Boston


About AvidInvented digital video editingHeadquartered in Tewksbury

– http://www.avid.com/company/Products

– Film/Video Editing and Finishing

– Audio– Broadcast– Animation– Storage & Workgroups– Digital Asset and Production

ManagementServices

– Support– Training– Consulting

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Agenda

What is SystemC?Why did Avid choose to use SystemC?DV problems solved by SystemC.Summary

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What is SystemC?

Provides hardware constructs and a simulation kernel for C++ It is a class library– And it is a language standard (IEEE 1666TM 2005)

It has utilities and constructs– Data types, ports, channels, processes

Adopted by different disciplines– Architectural Modeling (SoC, performance)– DV (RTL simulation, HW/SW co-verification)– Synthesis

It is open source (OSCI)– http://www.systemc.org

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Why Avid Chose SystemC

Enhanced existing C++ DV code– Replaced an unreliable in-house framework

• Signal encapsulation• Thread management• Random seed management

– Smooth transition from C++ to SystemCTool availability– Single kernel multi-language simulator

Industry acceptanceLow costCame with built-in verification capabilities

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Agenda


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Crossing Language Boundaries

Connect an entire HDL module to the testbench.– Wrap the module with a SystemC class

(sc_foreign_module).– Provide a string mapping for each port.

Connect a foreign signal anywhere in the hierarchy.– Bind a sc_signal (observe_foreign_signal).– Provide a string of hierarchical path to wire or reg.

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Code Examples SC_MODULE(MyVTB){public:SC_CTOR(MyVTB) :

MyDUTInst(“MyDUTInst”, “MyDUT”),MyMonitorInst(“MyMonitorInst”,

“MyVTB.MyDUTInst.FooInst”){

MyDUTInst.reset(tb_reset);MyDUTInst.clock(tb_clock);MyDUTInst.AD(tb_AD);

}private:MyDUT MyDUTInst;MyMonitor MyMonitorInst;

sc_signal<sc_logic> tb_reset;sc_signal<sc_logic> tb_clock;sc_signal<sc_lv<16> > tb_AD;

};

class MyDUT : public sc_foreign_module {public:sc_in<sc_logic> reset;sc_in<sc_logic> clock;sc_out<sc_lv<16> > AD;

MyDUT(sc_module_nam nm, const char* hdl_name): sc_foreign_module(nm, hdl_name),reset(“reset”),clock(“clock”),AD(“AD”){}

};

class MyMonitor : public sc_module {public:MyMonitor(sc_module_name,

const string& path2DUT){string path2sig = path2DUT + “.snoop”;snoopSig_.observe_foreign_signal(path2sig);SC_THREAD(threadT);sensitive <<

snoopSig_.value_changed_event();}

private:sc_signal<sc_logic> snoopSig_;void threadT();

};

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Issues with Binding

No clear standard for language boundary resolution.– Each vendor has its own implementation.– Implementation we use doesn’t map arrays or

records (yet).Supporting foreign interface requires two pass compilation. – First pass creates object files.– Second pass builds a symbol library used in

design elaboration.

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SystemC Connections

Call a public method via pointer to object

Connect sc_port to a sc_export

Connect sc_port to a channel

start()start()

outp inp

p

p

write() read()

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Code Examplesstruct start_stop_if : public sc_interface{virtual void start()=0;virtual void stop()=0;

};

class MyBFM : public sc_module, public virtual start_stop_if

{public:sc_in<sc_logic> Clock;sc_out<sc_logic> Request;sc_in<sc_lv<16> > AD;tlm::tlm_put_port<MyX> MyXReceivePort;sc_export<start_stop_if> StartStopExport;

void start();void stop();

SC_CTOR(MyBFM){StartStopExport(*this);

}};

SC_MODULE(MyTest){public:sc_port<start_stop_if> bfm_port;

};SC_MODULE(vtb){public:SC_CTOR(vtb);

private:sc_signal<sc_logic> Clock;sc_signal<sc_logic> Request;sc_signal<sc_lv<16> > AD;tlm::tlm_fifo<MyX> MyXReceiveChan;MyTest MyTestInst;MyBFM MyBFMInst;

};

vtb:vtb(sc_module_name) :MyBFMInst(“MyBFMInst”), MyTestInst(“MyTestInst”)

{MyBFMInst.Clock(Clock);MyBFMInst.Request(Request);MyBFMInst.AD(AD);MyBFMInst.MyXReceivePort(MyXReceiveChan);MyTestInst.bfm_port(MyBFMInst.StartStopExport);

}

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Issues with Connections

Construction and binding are separate steps.– Ports must be public.– Ports bound after modules and channels are constructed.

Binding uses “strict type checking”.– Compilation will fail if type mismatch in the connection.– Splitting a vector across multiple ports is complicated.

Binding errors detected at elaboration.– Simulation should abort at runtime if a port is not bound.– Need to assign attributes to port (e.g. # of connections).

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Randomization

Separate library dedicated to verification constructs (SCV).Robust, rich feature set for randomization.– Simple constraints (ranges and lists).– Complex constraint solver.– Thread-safe seeding.– Extendible to custom object types.

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Randomization at Avid

SCV more than we needed.– So, we use a subset of the features.

Provide a Tcl interface to apply constraints.– Wrap scv_smart_ptr.– Define string representations for simple

constraints.– Recompilation not required to change constraints.– Reapply constraints over course of simulation.

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Processes

Hardware is inherently parallel.DV must be multi-threaded.SystemC solves this with processes.– Macros: SC_THREAD and SC_METHOD.– Events, mutexes, semaphores.– Dynamic processes (sc_spawn).

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Hierarchy

SystemC defines an object hierarchy.– Relates objects (parent/child).– Familiar to HDL design.

Avid DV defines a layer hierarchy.– Relates connections.– Familiar to communication stacks.

Issue: SystemC is not a methodology.

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Example HierarchyVTOP

VTEST

VTB

DUT

Snooper_BFM

Monitor Monitor

Commander_BFM

Driver Monitor

TX_BFM

Driver

RX_BFM

Monitor

TLM Agent

STIMGEN

Translator Reference Model

Analysis Agent

Scoreboard

Analysis Agent

Test

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Agenda


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Additional Issues

Compile and link performance is disappointing.– Overuse of C++ templates in library.– Partially attributed to vendor implementation.

Libraries are huge.Being a language standard has tool implications.C++ learning curve.– C++ code debug very different than HDL.

• Segmentation faults, stack traces, code stepping

Think like a HW engineer, code like a SW engineer.

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Avid’s Experience

Used reliably for nearly 3 years.Runtime performance very satisfactory.Provides opportunity to assist product development beyond DV.– Evaluate architectures and predict

performance.– Create programmer’s view models for

emulation and HW/SW co-verification.

Technology

Design Verification Using SystemC