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Grading: 50% - Final exam 20% - Labs 15% - Project 15% - Test & Assignment/Quizzes Textbook: Logic and Computer Design Fundamentals M. Morris Mano & Charles R. Kime 3 rd Edition, Prentice Hall
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EKT 221 / 4ELECTRONIC DIGIT II
SUBJECT INTRODUCTION
1. Lecturers: Mdm. Norina Idris/Ms. Sanna Taking (G1,2) Mr. Mohd. Najmuddin Mohd. Hassan (G3,4) Mr. Zainuddin Mat Isa (G5,6)
2. PLVs: Mdm. Wan Azlianawati Wan Aziz Mdm. Norlida Abu Bakar Mr. Mohammad Nazri Md. Noor Mr. Baharuddin Ismail
Grading: 50% - Final exam 20% - Labs 15% - Project 15% - Test & Assignment/Quizzes
Textbook: Logic and Computer Design Fundamentals
M. Morris Mano & Charles R. Kime 3rd Edition, Prentice Hall
Chapter 0 : Combinational Logic Design Revision CAD Tools Design Procedure
OUTLINE
Chapter 1 : Registers & Register Transfers Registers, Microoperations & Implementations Counters, register cells, buses & serial
operations Counters Register cell design Multiplexer and bus-based transfers for multiple
registers Serial transfers & microoperations
OUTLINE
Chapter 2 : Sequencing & Control State machine Datapath & control Algorithmic State Machine (ASM) Hardwired control Microprogrammed control
OUTLINE
Chapter 3 : Memory Basics Memory definitions Random Access Memory (RAM) Static RAM integrated circuits Arrays of SRAM IC Dynamic RAM IC DRAM types Arrays of DRAM IC
OUTLINE
Chapter 4 : Computer Design Basics Datapath
OUTLINE
EXPERIMENTS Lab 1 -- Introduction to MaxPlus II Lab 2 -- Introduction to UP2 Training Board Lab 3 -- Combinational System Lab 4 -- Multiplier Lab 5 -- Up-Down Counter Lab 6 -- Serial Multiplier (Part 1) Lab 7 -- Serial Multiplier (Part 2) Lab 8 -- State Machine (Moore Model)
Course Outcomes (COs)
CO1: Ability to design digital systems at the sub-system level. CO2: Ability to use MaxPlus II design software. CO3: Ability to download the design software to FPGA device for testing purposes. CO4: Ability to participate effectively in a team.