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EEM 334 Digital Systems II

Outline

•  Hierarchical Design •  Components •  Generics •  Configuration •  Asd •  Adasd •  Asdad •  adasd

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Hierarchical Design

Introduction

•  Hierarchical design: How to deal with 1M gates or more? – Divide a system recursively into small modules – Construct each module independently

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Complexity Management

•  Focus on entire system vs. each module – Analyze, design, and verify each module in

isolation •  Let a team on designers work on the system

in parallel – Hierarchy and modules need to be specified first

•  Large memory space and computation time for the synthesis software

Design Reuse

•  Use predesigned modules or third party cores – No need to construct every system from the

scratch •  Keep verified modules for the future designs •  Portability

– Device-dependent components should be isolated – They should be substituted wrt the target techology

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VHDL Constructs for Hierarchy

•  Component •  Generic •  Configuration •  Library •  Package •  Subprogram

Components

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Component - Declaration

•  component name: Any legal identifier •  generic: Optional •  port: Ports described in entity •  Let you use the predesigned modules/IP cores

in your designs

Component - Declaration

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Decade Counter

Component - Instantiation

•  instance_label: Any legal identifier •  component name: Any legal identifier •  generic map: Optional •  port map •  Instantiate inside the architecture body

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Hundred Counter

Generics

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Generic - Declaration

•  Let you pass information into – Entity – Component

•  generic_names: Any legal identifier

A Parametrized Design

•  generic (WIDTH: natural := 8); --Default value

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A Parametrized Design

Configuration

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Configuration

•  Configuration of VHDL is the process of binding a component with a design entity and architecture

•  The process includes two parts: – Bind a component with a design entity – Bind the design entity with an architecture body

•  IEEE RTL synthesis standard supports only – Bind the design entity with an architecture body

Default Binding

•  The component is bound to an entity with the identical name

•  Component ports are bound to entity ports of the same names

•  The most recently analyzed architecture body is bound to the entity declaration

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Configuration - Declaration

•  configuration – A design unit (like entity, architecture, etc.) to

specify the binding of a component – Analyzed and stored independently

•  conf_name: Any legal identifier •  entity_name: Entity related to the config •  architecture_name: Architecture related to

the config

Configuration - Declaration

•  instance_label: A specific component instance

•  component_name: A specific component •  use…: Clause which indicates the entity and

architecture to be bound to the instance •  lib_name: Name of the library in which the

entity and architecture reside

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Decade Counter - Up

Decade Counter - Down

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Configuration

Library

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Library

•  Library: A virtual repository that stores the analyzed design units.

•  VHDL does not define the physical location of a library

•  The current design units are stored in a working library named work

Library

•  To access the content of a library

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Library

•  To make visible a design unit of a library

Subprograms

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Subprograms

•  Functions and procedures •  They are not design units

– They cannot be processed (synthesized) independently

•  Their body includes sequential statements

Functions

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Function Examples

Function Examples

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Package

Package

•  Package: A way of organizing declarations – Group commonly used declarations

• Constants, data types, components, functions, etc.

– Store them in a package •  Package has two parts:

– Package declarations – Package body

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Package

Package Example

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Synthesis Guides