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DANANG UNIVERSITY OF TECHNOLOGY

CENTER OF EXCELLENCE

EE271 LABORATORY REPORT:

LAB 01An Introduction to Mod!in"# Vri!o"#

$nd R$! %or!d Di"it$! &$rt'

Grou( )*+ L Vng Thi Trn Quc Trung Trn Bo Tin

C!$''+ 12ECE

&$rt 1+

,Sourc cod++ testBench.

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module testBench;

// wires connect things together

wire lesseq, a, b, c, d;

Comparator myComp (lesseq, a, b, c, d);

TestModule myTester (a,b,c,d, lesseq);

endmodule

+ Co!"#r#tor.module Comparator(lesseq, a, b, c, d);

parameter delay = !

output lesseq; // "uputs# lesseq

input a, b ,c, d; // $nputs# to compare, ab and

cd

and %delay and(term!, notC, not&);

and %delay and'(term, a,b);

and %delay and(term', a, c, not&);

and %delay and(term, b, notC);

and %delay and*(term, a, notC);

not %delay in+!(notC, c);

not %delay in+(not&,d);

or %delay or(lesseq, term!, term, term', term, term);

endmodule //close Comparator module

+ Test$o%u&e.

module TestModule (a,b,c,d, lesseq); // declare test module

// &eclare +ariables#

input lesseq; // Module inputs

output a, b, c, d; // Module outputs

parameter stim&elay = *; // &elay between generating

stimuli

reg a, b, c, d; // regs or setting +alues

or chec-ing outputs

// a +ariable must be o type

reg in order to// assign a +alue to it

initial // this initial bloc- assigns

initiali.ing

begin // +alues to the designated

+ariables

a = !;

b = !;

c = !;

d = !;

end

initial // this initial bloc- will

apply the test +ectors

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begin // begin initial loop

display(0C1"C23t3t $456T7 3t3t "6T56T3t3tT$M80);

display(099a99 3t 99b993t 99c993t99d993t 99lesseq993t3t9999990);

monitor(0 :b 3t :b 3t :b 3t :b 3t3t :b0

,a,b,c,d,lesseq,time);

// The ollowing is our test code or test +ectors

// begin a second bloc- to perorm the simulation

repeat (') // repeat this process

twice or illustration

begin // begin a,b,c,d? = !; // a=!, b=!, c=!, d=!

%stim&elay >a,b,c,d? = ; // a=!, b=!, c=!, d=

%stim&elay >a,b,c,d? = '; // a=!, b=!, c=,

d=!%stim&elay >a,b,c,d? = ; // a=!, b=!, c=, d=

%stim&elay >a,b,c,d? = ; // a=!, b=, c=!, d=!

%stim&elay >a,b,c,d? = *; // a=!, b=, c=!, d=

%stim&elay >a,b,c,d? = @; // a=!, b=, c=, d=!

%stim&elay >a,b,c,d? = A; // a=!, b=, c=, d=

%stim&elay >a,b,c,d? = ; // a=, b=!, c=!, d=!

%stim&elay >a,b,c,d? = ; // a=, b=!, c=!, d=

%stim&elay >a,b,c,d? = !; // a=, b=!, c=, d=!

%stim&elay >a,b,c,d? = ; // a=, b=!, c=, d=

%stim&elay >a,b,c,d? = '; // a=, b=, c=!, d=!

%stim&elay >a,b,c,d? = ; // a=, b=, c=!, d=

%stim&elay >a,b,c,d? = ; // a=, b=, c=, d=!

%stim&elay >a,b,c,d? = *; // a=, b=, c=, d=

end // close the a,b,c,d? = !; // a=!, b=!, c=!, d=!

%stim&elay >a,b,c,d? = !; // a=, b=!, c=, d=!

end

%('Fstim&elay); // needed to see 84& o

simulation

stop; // temporarily stops

simulation

// goto Gerilog interacti+e

mode

// need to type or

Hinish;H

inish; // inish simulation

end // close second initial loop

endmodule // close test9module

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- .u'tion'+1. 'r#( # &ogic %i#gr#! using the &ogic g#tes th#t (ere use% to )ui&% the %igit#& circuit in the

Veri&og source co%e. *se the s#!e sign#& n#!es in%ic#te% in the source co%e. *se ,'- /- #n%,T g#tes.

2. 'r#( the truth t#)&e 0or this circuit. Looing #t the (#e0or! 0ro! our si!ution !# he&". truth t#)&e 0or # &ogic circuit h#s #n in"ut si%e #n% #n out"ut si%e. The in"ut si%e &ists #&& o0 the"ossi)&e in"ut co!)in#tions to the circuit #n% the out"ut si%e &ists the #&ue3s4 o0 the out"ut3s4 0ore#ch in"ut co!)in#tion. 5igure 6 )e&o( sho(s the &ogic s!)o& #n% #ssoci#te% truth t#)&e 0or #n

,' g#te. The &e0t h#n% si%e o0 the truth t#)&e e)or#tes #&& 6 "ossi)&e in"ut co!)in#tions #n%the right h#n% si%e gies the corres"on%ing out"ut.A B C D Term1 Term2 Term3 Term4 Term5 lesseq

0 0 0 0 1 0 0 0 0 1

0 0 0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0 0 0

0 1 0 0 1 0 0 1 0 1

0 1 0 1 0 0 0 1 0 1

0 1 1 0 0 0 0 0 0 0

0 1 1 1 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1 1

1 0 0 1 0 0 0 0 1 1

1 0 1 0 0 0 1 0 0 1

1 0 1 1 0 0 0 0 0 0

1 1 0 0 1 1 0 1 1 1

1 1 0 1 0 1 0 1 1 11 1 1 0 0 1 1 0 0 1

1 1 1 1 0 1 0 0 0 1

7. 8hen ou run the si!ution. 'oes the out"ut o0 the Veri&og "rogr#! #gree or %is#gree (ithour truth t#)&e9

The output of the er!lo" pro"r#m $!s#"rees %!th m& truth t#'le(

Be)#use there #re $el#& t!me !* pro)ess( Del#& + 10 t!me u*!t ,!*!t!#l- #*$ st!m$el#& + 15 t!me

u*!t(

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6. :&e#se e;"in the #""#rent& incorrect or%er in (hich the resu&ts in the out"ut &og #re "rinte%&itch? "rints.Be)#use the t!me $el#&. the /#lue of output lesseq !s %he* ,A+0.B+0.C+0.D+0- #*$ lesseq !s

$!ffere*t from truth t#'le %he* the /#lues of A.B.C.D !*)re#s!*"(

pe)!f!)#ll&. %he* the output l!*e Pro$u)!*" l!t)h pr!*ts. the /#lue of lesseq !s set to 1 %he*

,A+0.B+0.C+0.D+0-(A*$ #fter th#t %he* ,A+0.B+1.C+0.D+1- the /#lue of lesseq )h#*"e repe#tl&

,from 0 to 1-(

@. Ch#nge the #&ue o0 the %e in the "rogr#! 0ro! 1A to A. /erun the si!ution. 'oes theout"ut o0 the Veri&og "rogr#! #gree or %is#gree (ith our truth t#)&e9 :&e#se e;"in #n%i00erences.he* the $el#& t!me !s 0. the output of er!lo" pro"r#m #"ree %!th m& truth t#'le(

he* the output l!*e Pro$u)!*" l!t)h pr!*ts. there #re 6ust 3 /#lues $!spl#&. #*$ !t !s the s#me %!th

truth t#'le

A*other $!ffere*t po!*ts !s %he* the $el#& t!me !s 0. the output )h#*"e there st#tus from 0 to 1 /er&

qu!)7l& #*$ #lmost !mme$!#tel&(

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L!*e lesseq )h#*"e from 1 to 0 #*$ 0 to 1 /er& f#st

. Ch#nge the %e in the "rogr#! )#c to 1A ti!e units. Ch#nge the sti!'e in the test!o%u&e to @ ti!e units. 8h#t #00ect %oes this ch#nge h#e on the out"uts o0 our si!ution9The outputs %!ll $el#& for # lo*" t!me

. 8h#t #%#nt#ges #re there to using # "rogr#! &ie Veri&og9 ,#!e three or !ore.8 9ree

8 oo$ user !*terf#)e

8 Po%erful s!mul#t!o*

#/eform of the output er!lo" %!th t!me $el#& + 0

#/eform of the output er!lo" %!th t!me $el#& + 10

#/eform of the output er!lo" %!th t!me $el#& + 10 #*$ st!mDel#& + 5

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&$rt 2+

1. co" the Veri&og source co%e 0or the $u&ti5unction Logic B&oc- the test)ench-#n% the tester.

+ The testermodule TestModule (781,781',,B, 781,781',,B? = ;

%stim&elay >781,781',,B? = ';

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = ; %stim&elay >781,781',,B? = *;

%stim&elay >781,781',,B? = @;

%stim&elay >781,781',,B? = A;

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = !;

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = ';

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = ;

%stim&elay >781,781',,B? = *;

end // close the

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// we use the speciic 78D684C8 o e+ents to cause a glitch 9 were there others

begin

display(05roducing Elitch0);

%stim&elay >781,781',,B? = !; // a=!, b=!, c=!, d=!

%stim&elay >781,781',,B? = !; // a=, b=!, c=, d=!

end

%('Fstim&elay); // needed to see 84& o simulationstop; // temporarily stops simulation

// goto Gerilog interacti+e mode

// need to type or Hinish;H

inish; // inish simulation

end // close second initial loop

endmodule // close test9module

+ testBench

module testBench;

// wires connect things together

wire

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EE271_Lab1_Group06