EE247 Lecture 13 - University of California, Berkeleyee247/fa05/lectures/L13_f05.pdfEE247 Lecture 13 • Administrative issues To avoid having EE247 & EE 142 midterms on the same day,

EECS 247 Lecture 13: Data Converters © 2005 H.K. Page 1

EE247Lecture 13

• Administrative issues§ To avoid having EE247 & EE 142 midterms

on the same day, EE247 midterm moved from Oct. 20th to Tues. Oct. 25tho You can only bring one 8x11 paper with noteso No books, class handouts, calculators,

computers, cell phones....


EE247Lecture 13

• Data Converters0Summary last lecture0ADC & DAC testingú DNL & INL§ Code boundry servo test§ Histogram testing

ú Spectral testing§ Direct Discrete-Fourier-Transform (DFT) based

measurements§ DFT measurements including windowing


Offset and Full-Scale Error

-1 0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7

Dig

ital

Ou

tpu

t C

od

e

ADC Input Voltage [LSB]

Real ADC characteristicsIdeal converter

Offset error

Full-scale error

For DNL, INL measurementsneed to elliminate offset and full-scale erroràconnect

endpoints & deriving ideal codes based on non-ideal endpoints


-1 0 1 2 3 4 5 6 7 8 9

0

1

2

3

4

5

6

7

8

ADC characteristicsideal converter

ADC Differential Nonlinearity

DNL = deviation of code width from

∆ (1LSB)

+0.4 LSB DNL error

-0.4 LSB DNL error

à Endpoints connected

à Ideal characteriscticsderived

à DNL measured

0 LSB DNL error

Dig

ital

Ou

tpu

t C

od

e

ADC Input Voltage [∆]


DAC Differential Nonlinearity


ADC Integral Nonlinearity

• A straight line through the endpoints used as reference à offset and full scale errors ignored in INL derivation

• Ideal converter steps is found for the endpoint line, then INL is measured

• Note that INL errors can be much larger than DNL errors and vice-versa -1 0 1 2 3 4 5 6 7 8

0

1

6

7

Dig

ital

Ou

tpu

t C

od

e


INL = deviation of code transition from its ideal location

-1 LSB INL

2

3

4

5


DAC Integral Nonlinearity


DAC DNL and INL

* Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.


Example: INL & DNL

Large INL & Small DNL Large DNL & Small INL


Monotonicity• Monotonicity guaranteed if

| INL | = 0.5 LSBThe best fit straight line is taken as the reference for determining the INL.

• This implies| DNL | = 1 LSB

• Note: these conditions are sufficient but not necessary for monotonicity


How to measure DNL/INL?• DAC:

– Apply codes and use a good voltmeter to measure output

• ADC– Not as simple as DACà need to find "decision levels", i.e.

input voltages at all code boundaries• One way: Adjust voltage source to find exact code trip points

"code boundary servo"• More versatile: Histogram testingàApply a signal with known distibution and analyze digital code distribution at ADC output


Code Boundary Servo

C1

ADCInputR2

C2

ADCUnder Test

VREF

i1

i2

DigitalComp.

A<B

BA≥B

A

InputDigitalCode

ADCOutput

fS


Code Boundary Servo

AD

C D

igit

al O

utp

ut

ADC Analog Input

111

110

101

100

011

010

001

000

∆ 2∆ 3∆ 4∆ 5∆ 6∆ 7∆

• i1 and i2 are small, and C1 is large, so the ADC analog input moves a small fraction of an LSB each sampling period

• For a code input of 101, the ADC analog input settles to the code boundary shown


Code Boundary ServoGood DVM

C1

R2

C2

ADC

VREF

i1

i2

DigitalComp.

A<B

BA≥B

A

InputDigitalCode

ADCOutput

fS


Code Boundary Servo• A very good digital voltmeter (DVM)

measures the analog input voltage corresponding to the desired code boundary

• DVMs have some interesting properties– They can have very high resolutions (8½ decimal

digit meters are inexpensive)– To achieve stable readings, DVMs average

voltage measurements over multiple 60Hz ac line cycles to filter out pickup in the measurement loop


Code Boundary Servo

• ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs

• A magnified view of an analog input glitch follows …

Good DVM

R2

C2

ADC

VREF fS


Code Boundary Servo

• Just before the input is sampled and conversion starts, the analog input is pretty quiet

• As the converter begins to quantize the signal, it kicks back charge

time0 1/fS

anal

og

inp

ut

start of conversion


Code Boundary Servo

• The difference between what the ADC measures and what the DVM measures is not ADC INL, it’s error in the INL measurement

• How do we control this error?

time0 1/fS

anal

og

inp

ut

ADC converts this voltage

DVM measures the averageinput including the glitch


Code Boundary Servo

• A large C2 fixes this

• At the expense of longer measurement time

Good DVM

R2

C2

ADC

VREF fS


Histogram Testing

• Code boundary measurements are slow– Long testing time– May miss dynamic errors

• Histogram testing– Quantize input with known pdf (e.g. ramp or

sinusoid)– Measure output pdf– Derive INL and DNL from deviation of measured

pdf from expected result


Histogram Test Setup

Ramp

0

VREF

ADC PC

VREF

• Slow (wrt conversion time) linear ramp applied to ADC• DNL derived directly from total number of occurrences of each

code @ the output of the ADC

Time


A/D Histogram Test Using Ramp SignalDigital Output

Analog input

Ramp

Time

n/fs

ADCInput/Output

Example:

Ramp slope: 10µV/µsec1LSB =10mVEach ADC code à1msec

fs =100kHz à Ts=10µsec

à n =100 samples/code


A/D Histogram Test Using Ramp Signal

Dig

ital O

utpu

t

Analog input

RampT

ime

n/fs

ADCInput/Output

Example:

Ramp slope: 10µV/usec1LSB =10mVEach ADC codeà1msec

fs =100kHz à Ts=10µsec

à n =100 samples/code#

ofSa

mpl

esP

er c

ode


Measuring DNL

• Ramp speed is adjusted to provide large number of output/code - e.g. an average of 100 outputs of each ADC code (for 1/100 LSB resolution)

• Ramp test can be quite slow for high resolution ADCs• Example:

16bit ADC & 100conversions/code @100kHz sampling rate

(216or 65,536 codes)(100 conversions/code)

100,000 conversions/sec= 65.6 sec


Ramp HistogramExample: Ideal 3-Bit ADC

0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7ADC characteristicsideal converter

0 1 2 3 4 5 6 70

20

40

60

80

100

120

140

160

180

200

ADC output code

Co

de

Co

un

t

Dig

ital

Ou

tpu

t C

od

e



Ramp HistogramExample: 3-Bit ADC with Error

0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7


+0.4 LSB DNL

-0.4 LSB DNL

+0.4 LSB INL

0 1 2 3 4 5 6 70

20

40

60

80

100

120

140

160

180

200

ADC output code

Co

de

Co

un

t

Dig

ital

Ou

tpu

t C

od

e



Example: 3 Bit ADCDNL Extracted from Histogram

1- “Over-range bins” removed (0 and full-scale)

2- Compute average count/bin (100 in this case)

0 1 2 3 4 5 6 70

20

40

60

80

100

120

140

ADC output code

Co

de

Co

un

t, E

nd

bin

s re

mo

ved



Normalize:3- Divide by average count/bin

(ideal bins have exactly the average count, which, after normalization, is 1)

0 1 2 3 4 5 6 70

0.2

0.4

0.6

0.8

1

1.2

1.4

ADC output code

No

rmal

ized

Co

de

Co

un

t



4- Subtract 1 from the normalized code count

5- Result is DNL (+-0.4Lsb in this case)

0 1 2 3 4 5 6 7-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

ADC output code

DN

L =

Co

un

ts /

Mea

n(C

ou

nts

)


Example: 3-Bit ADCStatic Characteristics Extracted from Histogram

• Width of all codes derived from measured DNL (Code=DNL + 1LSB)

• DNL histogram à used to reconstruct the exact converter characteristic (having measured only the histogram)

• INL- (deviation from a straight line through the end points)- is found

-1 0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7

ADC Input Voltage

Rec

on

stru

cted

Ch

arac

teri

stic


Example: 3 Bit ADCDNL & INL Extracted from Histogram

-1 0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7


+0.4 LSB DNL

-0.4 LSB DNL

+0.4 LSB INL

1 2 3 4 5 6-1

-0.5

0

0.5

1

DN

L [

LS

B]

DNL and INL of 3 Bit converter (from histogram testing)

1 2 3 4 5 6bin #

INL

[L

SB

]

Dig

ital

Ou

tpu

t C

od

e


bin #

-1

-0.5

0

0.5

1


ADC Histogram Testing Sinusoidal Inputs

• Highly linear ramp signals not readily available (>8 to10bits)

• Solution: àUse sinusoidal test signal

(may need to filter out harmonics)

• Problem: ideal histogram is not flat but has “bath-tub shape”

0 500 1000 1500 2000 2500 3000 3500 40000

50

100

150

200

250

ADC Output- Raw Histogram


A/D Histogram Test Using Sinusoidal Signals

Sinusoid

At sinusoid midpoint crossings:dv/dt à max.

à least # of samples

At sinusoid amplitude peaks:dv/dt à min.

à highest # of samples

ADCInput/Output

Dig

ital O

utpu

t

Analog input

Tim

e

# of

Sam

ples

Per

cod

e


Resulting DNL and INL

0 500 1000 1500 2000 2500 3000 3500 4000-1

0

1

code

DN

L [

LS

B]

DNL = +1.3 / -1 LSB, missing code if (DNL<-0.9)

0 500 1000 1500 2000 2500 3000 3500 4000-1

0

1

2

code

INL

[L

SB

]

INL = +1.7 / -0.69 LSB


Correction for Sinusoidal PDF

• References:– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,

“Dynamic Testing and Diagnostics of A/D Converters,” IEEE Transactions on Circuits and Systems, vol. CAS-33, no. 8, Aug. 1986.

– [2] IEEE Standard 1057

• Is it necessary to know the exact amplitude and offset of sinusoidal input? No!


DNL/INL Code

function [dnl,inl] = dnl_inl_sin(y);%DNL_INL_SIN% dnl and inl ADC output% input y contains the ADC output% vector obtained from quantizing a% sinusoid

% Boris Murmann, Aug 2002% Bernhard Boser, Sept 2002

% histogram boundariesminbin=min(y);maxbin=max(y);

% histogramh = hist(y, minbin:maxbin);

% cumulative histogramch = cumsum(h);

% transition levelsT = -cos(pi*ch/sum(h));

% linearized histogramhlin = T(2:end) - T(1:end-1);

% truncate at least first and last % bin, more if input did not clip ADCtrunc=2;hlin_trunc = hlin(1+trunc:end-trunc);

% calculate lsb size and dnllsb= sum(hlin_trunc) / (length(hlin_trunc));dnl= [0 hlin_trunc/lsb-1];misscodes = length(find(dnl<-0.9));

% calculate inlinl= cumsum(dnl);


DNL/INL Code Test

% converter modelB = 6; % bitsrange = 2^(B-1) - 1;% thresholds (ideal converter)th = -range:range; % ideal thresholdsth(20) = th(20)+0.7; % error

fs = 1e6;fx = 494e3 + pi; % try fs/10!C = round(100 * 2^B / (fs / fx));

t = 0:1/fs:C/fx;x = (range+1) * sin(2*pi*fx.*t);y = adc(x, th) - 2^(B-1);

hist(y, min(y):max(y));

dnl_inl_sin(y);

-30 -20 -10 0 10 20 30-1

-0.5

0

0.5

1

codeD

NL

[L

SB

]

DNL = +0.7 / -0.7 LSB, 0 missing codes (DNL<-0.9)

-30 -20 -10 0 10 20 30-0.2

0

0.2

0.4

0.6

0.8

INL

[L

SB

]

INL = +0.7 / -0.0 LSB


Histogram Testing Limitations

• The histogram (as any ADC test, of course) characterizes one particular converter. Test many devices to get valid statistics.

• Histogram testing assumes monotonicityE.g. “code flips” will not be detected.

• Dynamic sparkle codes produce only minor DNL/INL errorsE.g. 123, 123, …, 123, 0, 124, 124, … à look at ADC output to detect

• Noise not detected or improves DNL E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …

Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.


Example: Hiding Problems in the Noise

• INL à 5 missing codes

• DNL "smeared out" by noise!

• Always look at both DNL/INL

• INL usually does not lie...

[Source: David Robertson, Analog Devices]


Why Additional Tests/Metrics?

• Static testing does not tell the full story– E.g. no info about "noise"

• Frequency dependence (fs and fin) ?– In principle we can vary fs and fin when performing

histogram tests– Result of such sweeps is usually not very useful– Hard to separate error sources, ambiguity– Typically we use fs=fsNOM and fin << fs/2 for

histogram tests• For additional infoà Spectral testing


Direct ADC-DAC Test

• Need DAC with much better performance compared to ADC under test

• Actually a good way to "get started"...

Vin Vout SpectrumAnalyzer

SignalGenerator

ClockGenerator

Device Under Test (DUT)

ADC DAC


DFT Test

ADCVin PCSignal

Generator

ClockGenerator

Device Under Test (DUT)

DataAcquisition

System


Analyzing ADC outputs via Discrete Fourier Transform

• An ideal, infinite resolution ADC would preserve ideal, single tone spectrum

• Deviations reveal ADC non-idealities

⇒x(t) x(k)


Discrete Fourier TransformThe DFT of a sequence of N samples

{x(k)} = {x(0), x(1), x(2),…,x(N-1)}

yields a set of N frequency bins

{Am} = {A0,A1,A2,…,AN-1}

where:

Am = Σn=0

N-1

xn WNmn

m = 0,1,2,…,N-1

WN ≡ ej2π/N


DFT Properties

• DFT of N samples spaced T=1/fsseconds:– N frequency bins– Bin m represents frequencies at m * fs/N

[Hz]

• DFT frequency resolution:– Proportional to 1/(NT) in [Hz/bin]


DFT Magnitude Plots

• Because Am magnitudes are symmetric around fS/2, it is redundant to plot Am’s for m >N/2

• Usually magnitudes are plotted on a log scale normalized so that a full scale sinewave of rms value aFS yields a peak bin of 0dBFS:

Am (dBFS) = 20 log10

Am

aFS N/2

0 fs/2 fs


Normalized DFTfs = 1e6;fx = 50e3;Afs = 1;N = 100;

% time vectort = linspace(0, (N-1)/fs, N);% input signaly = Afs * cos(2*pi*fx*t);% spectrums = 20 * log10(abs(fft(y)/N/Afs*2));% drop redundant halfs = s(1:N/2);% frequency vector (normalized to fs)f = (0:length(s)-1) / N;

0 0.2 0.4 0.6 0.8 1x 10

-4

-1

-0.5

0

0.5

1

Time

Am

plit

ud

e

0 0.1 0.2 0.3 0.4 0.5

-300

-200

-100

0

Frequency [ f / fs]

Mag

nit

ud

e [

dB

FS

]


“Another” Example …

This does not look like the spectrum of a sinusoid …

0 1 2 3 4 5

x 10-5

-1

-0.5

0

0.5

1

Time

Sig

nal A

mpl

itude

0 0.1 0.2 0.3 0.4 0.5-50

-40

-30

-20

-10

Frequency [ f / fs ]

Am

plitu

de [

dB

FS ]


DFT Periodicity• The DFT implicitly assumes that

time sample blocks repeat every N samples

• With a non-integer number of periods within the observation window, the input yields significant amplitude/phase discontinuity at the block boundary

• This energy spreads into all frequency bins as “spectral leakage”

• Spectral leakage can be eliminated by either– An integer number of sinusoids in

each block– Windowing

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-4

-1

-0.5

0

0.5

1

Time

Sig

nal A

mpl

itude

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-4

-1

-0.5

0

0.5

1

TimeS

igna

l Am

plitu

de

Actual Signal

DFT Perceived Signal


Spectra

0 0.1 0.2 0.3 0.4 0.5-60

-50

-40

-30

-20

-10


Am

plitu

de [

dB

FS

]

0 0.2 0.4 0.6 0.8 1 1.2 1.4x 10

-4

-1

-0.5

0

0.5

1

Time

Sig

nal A

mpl

itude

0 0.2 0.4 0.6 0.8 1 1.2 1.4

x 10-4

-1

-0.5

0

0.5

1

Time

Sig

nal A

mpl

itude

0 0.1 0.2 0.3 0.4 0.5-400

-300

-200

-100

0


Am

plitu

de [

dB

FS

]

Integer number of cycles Non-integer number of cycles


Choice of Number of Cycles & Number of Samples

To overcome frequency spectrum leakage problem:

– Number of Cycles à integer

– N/cycles = fs / fxà non-integer

– Preferable to have N à power of 2 (FFT instead of DFT)

N/cycles = fs / fx=6 à integer

-1

-0.5

0

0.5

1

Sig

nal A

mpl

itude

-1

-0.5

0

0.5

1

Sig

nal A

mpl

itude

N/cycles = fs / fx=5.55 à non-intege

Time

Time


Example: Integer Number of Cycles

fs = 1e6;% Number of full cycles in

testcycles = 67;

% Make N/cycles non-integer!% N=power of 2 speeds up

analysis

N = 2^10;

% signal frequencyfx = fs*cycles/N

0 0.1 0.2 0.3 0.4 0.5-350

-300

-250

-200

-150

-100

-50

0

Frequency [ f / fs]s ]

Am

plit

ud

e [

dB

]


Example: Integer Number of Cycles

• Fundamental falls into a single DFT bin

• Noise (this example numerical quantization noise) occupies all other bins

• “integer number of cycles” constrains signal frequency fx

• Alternative: windowing à 0 0.1 0.2 0.3 0.4 0.5-350

-300

-250

-200

-150

-100

-50

0

Frequency [ f / fs]s ]

Am

plit

ud

e [

dB

]


Windowing• Spectral leakage can also be virtually

eliminated by “windowing” time samples prior to the DFT– Windows taper smoothly down to zero at the

beginning and the end of the observation window– Time samples are multiplied by window

coefficients on a sample-by-sample basis

• Windowing sinusoidal waveforms places the window spectrum at the sinewave frequency– Convolution in frequency


Window

• Time samples are multiplied by window coefficients on a sample-by-sample basis

• Multiplication in the time domain corresponds to convolution in the frequency domain

• Example: Nuttall window100 200 300 400 500 600 700 800 900 1000

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time


Windowed Data

• Signal before windowing

• Signal after windowing

– Windowing removes the discontinuity at block boundaries

0 0.2 0.4 0.6 0.8 1-1

-0.5

0

0.5

1

Time

Sig

nal

Am

plit

ud

e

0 0.2 0.4 0.6 0.8 1

x 10-3

-2

-1

0

1

2

TimeWin

do

wed

Sig

nal

Am

plit

ud

e

x 10-3


Nuttall Window DFT

• Only first 20 bins shown

• Response attenuated by -120dB for bins > 5

• Lots of windows to choose from (go by name of inventor-Blackman, Harris…)

• Various window trade-off attenuation versus width (smearing of sinusoids)

2 4 6 8 10 12 14 16 18 20

-120

-100

-80

-60

-40

-20

DFT Bin

No

rmal

ized

Am

plit

ud

e [d

B]


DFT of Windowed Signal

• Spectra of signal before and after windowing

• Window gives ~ 100dB attenuation of sidelobes(use longer window for higher attenuation)

• Signal energy “smeared” over several (approximately 10) bins

0 0.1 0.2 0.3 0.4 0.5-70

-60

-50

-30

-20

-10

0

Frequency [ fx/ fs]

Spe

ctru

m n

ot W

indo

wed

[ d

BFS

]

0 0.1 0.2 0.3 0.4 0.5-140

-120

-100

-80

-60

-40

-20

0

Win

dow

ed S

pect

rum

[ d

BF

S ]

Frequency [ fx/ fs]

-40

Before windowing

After windowing


Integer Cycles versus Windowing• Integer number of cycles

– Signal energy for a single sinusoid falls into single DFT bin– Requires careful choice of fx– Ideal for simulations– Measurements à need to lock fx to fs (PLL)

• Windowing– No restrictions on fxàno need to have the signal locked to fsà ideal for measurements

– Signal energy (and harmonics) distributed over several DFT bins

– Requires more data points for a fixed accuracy


Spectral ADC Testing

• ADC with B bits• ±1 full scale input

B = 10;delta = 2/(2^B-1);th = -1+delta/2:delta:1-delta/2;x = sin(…);y = adc(x, th) * delta - 1;s = abs(fft(y)/N*2);s = s(1:N/2);f = (0:length(s)-1) / N;


ADC Output Spectrum

0 0.1 0.2 0.3 0.4 0.5-120

-100

-80

-60

-40

-20

0

N=2048

Am

pliu

tde

[dbF

S]

f/fs

• Signal amplitude:– Bin: N * fx/fs + 1

(Matlab arrays start at 1)

– A = 0dBFS

• SNR?


ADC Output Spectrum

• Noise bins: all except signal bin

bx = N*fx/fs + 1;As = 20*log10(s(bx))s(bx) = 0;An = 10*log10(sum(s.^2))SNR = As - An

• SNR = 62dB (10 bits)• Computed SQNR = 6.02xN+1.76dB

0 0.1 0.2 0.3 0.4 0.5-120

-100

-80

-60

-40

-20

0

N=2048

Am

pliu

tde

[dbF

S]

f/fs


Why is noise floor not 62dB ?

• DFT bins act like an analog spectrum analyzer with bandwidth of fs/N, rather than fs/2

• The DFT noise floor is 10log10(N/2)dB below the actual noise floor (assuming white noise)

• For N=2048: 30dB 0 0.1 0.2 0.3 0.4 0.5-120

-100

-80

-60

-40

-20

0

N=2048

Am

pliu

tde

[dbF

S]

f/fs

30dB


DFT Plot Annotation

1. Specify how many DFT points (N) are used, or

2. Shift DFT noise floor by 10log10(N/2)dB, or

3. Normalize to "noise power in 1Hz bandwidth"


Spectral Performance Metrics

• Signal S• DC• Distortion D• Noise N

• Signal-to-noise ratioSNR = S / N

• Signal-to-distortion ratioSDR = S / D

• Signal-to-noise+distortion ratio SNDR = S / (N+D)

• Spurious-free dynamic rangeSFDR


Harmonic Components• At multiples of fx

• Aliasing:– fsignal = fx = 0.18 fs– f2 = 2 f0 = 0.36 fs– f3 = 3 f0 = 0.54 fsà 0.46 fs

– f4 = 4 f0 = 0.72 fsà 0.28 fs

– f5 = 5 f0 = 0.90 fsà 0.10 fs

– f6 = 6 f0 = 1.08 fsà 0.08 fs


Spectrum versus INL, DNL

100 200 300 400 500 600 700 800 900 1000-1

-0.5

0

0.5

1

1.5

2

bin

DN

L [i

n LS

B]

DNL and INL of 10 Bit converter (from converter decision thresholds)

avg=0.0053, std.dev=0.0048, range=0.019

100 200 300 400 500 600 700 800 900 1000-1

-0.5

0

0.5

1

1.5

2

2.5

3

binIN

L [i

n LS

B]

avg=0.21, std.dev=0.75, range=2.1

Good DNL and poor INLsuggests distortion problem


Relationship INL-SFDR/SNDR

• Depends on "shape" of INL • Rule of Thumb: SFDR ≅ 20log(2B/INL)

– E.g. 1LSB INL, 10bà SFDR≅60dB

• Beware, this is of course only true under the same conditions at which the INL was taken, i.e. typically low input frequency

Documents

EE247 Lecture 13 - University of California, Berkeleyee247/fa05/lectures/L13_f05.pdfEE247 Lecture 13 • Administrative issues To avoid having EE247 & EE 142 midterms on the same day,