EE247 Lecture 17 - University of California, Berkeleyee247/fa06/lectures/L17c_f06.pdf · EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 7 DAC Implementation Examples • Untrimmed

EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 1

EE247Lecture 17

DAC Converters (continued)• DAC dynamic non-idealities• DAC design considerations• Self calibration techniques

–Current copiers–Dynamic element matching

• DAC reconstruction filterADC Converters• Sampling

–Sampling switch induced distortion–Sampling switch charge injection


Summary of Last Lecture

D/A converters continued:– Current based DACs-unit element versus binary weighted– R-2R type DACs– Static performance

• Component matching-systematic & random errors– Component variations Gaussian pdf – INL for both unit-element and binary-weighted DACs σDNL= σε x2B/2-1

– DNL for unit-element σDNL= σε– DNL for binary-weight DAC: σDNL= σε x2B/2

– Practical aspects of current-switched DACs

– Segmented current-switched DACs


DAC Dynamic Non-Idealities• Finite settling time

– Linear settling issues: (e.g. RC time constants)

– Slew limited settling• Spurious signal coupling

– Coupling of clock/control signals to the output via switches

• Timing error related glitches– Control signal timing skews


Dynamic DAC Error: Timing Glitch

• Consider binary weighted DAC transition 011 100

• DAC output depends on timing

• Plot shows situation where the control signals for LSB & MSB– LSB/MSBs on time– LSB early, MSB late– LSB late, MSB early

1 1.5 2 2.5 30

5

10

Idea

l

1 1.5 2 2.5 30

5

10

Ear

ly

1 1.5 2 2.5 30

5

10

Time

Late


Glitch Energy• Glitch energy (worst case) proportional to: dt x 2B-1

• dt error in timing & 2B-1 associated with half of the switches changing state

• LSB energy proportional to: T=1/fs

• Need dt x 2B-1 << T or dt << 2-B+1 T

• Examples:

<< 488<< 1.5<< 2

121610

120

1000

dt [ps]Bfs [MHz]


DAC Dynamic Errors• To suppress effect of non-idealities:

– Retiming of current source control signals• Each current source has its own clocked latch

incorporated in the current cell • Minimization of latch clock skew by careful

layout ensuring simultaneous change of bits

– To minimize control and clock feed through to the output via G-D of the switches• Use of low-swing digital circuitry


DAC Implementation Examples• Untrimmed segmented

– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983

– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315

• Current copiers:– D. W. J. Groeneveld et al, “A Self-Calibration Technique for

Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517

• Dynamic element matching:– R. J. van de Plassche, “Dynamic Element Matching for High-

Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795


2μ tech., 5Vsupply6+2 segmented8x8 array


Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistance


Current-Switched DACs in CMOS( )

( )

( )

( )

M 1

M 2 M 1 M 3 M 1

M 4 M 1 M 5 M 1

M 2

M 1

M 1

M 1

M 1M 1

M 1M 1

2GS th1

GS GS GS GS

GS GS GS GS2

2GS th2 1

GS th

1m

GS th2

m2 1 1 m

2m

3 1 1 m

V VI kV V 4RI , V V 7RIV V 9RI , V V 10RI

4RI1V VI k I

V V2I

gV V

4RgI I I 1 4Rg12

7RgI I I 1 7Rg12

I

−== − = −= − = −

⎛ ⎞−−= = ⎜ ⎟−⎝ ⎠=

−⎛ ⎞

→ = ≈ −−⎜ ⎟⎝ ⎠⎛ ⎞

→ = ≈ −−⎜ ⎟⎝ ⎠

→ ( )

( )

M 1M 1

M 1M 1

2m

4 1 1 m

2m

5 1 1 m

9RgI I 1 9Rg12

10RgI I I 1 10Rg12

⎛ ⎞= ≈ −−⎜ ⎟

⎝ ⎠⎛ ⎞

→ = ≈ −−⎜ ⎟⎝ ⎠

Iout

•Assumption: RI is small compared to transistor gate overdriveDesirable to have gm small

Example: 5 unit element current sources

VDD

I1 I2 I3 I4

Rx4I Rx3I Rx2I

M1 M2 M3 M4 I5M5

RxI


Current-Switched DACs in CMOSExample: INL of 3-Bit unit element DAC

Input

INL

[LS

B]

Example: 7 unit element current source DAC- assume gmR=1/100

• If switching of current sources sequential (1-2-3-4-5-6-7)INL= +0.25LSB

• If switching of current sources symmetrical (4-3-5-2-6-1-7 )INL = +0.09, -0.058LSB INL reduced by a factor of 2.6

-0.1

0

0.1

0.2

0.3

1 2 3 4 5 6 7

Sequential current source switchingSymmetrical current source switching

0


Current-Switched DACs in CMOSExample: DNL of 7 unit element DAC

Input

DN

L [L

SB

]

Example: 7 unit element current source DAC- assume gamer=1/100

• If switching of current sources sequential (1-2-3-4-5-6-7)DNLmax= + 0.15LSB

• If switching of current sources symmetrical (4-3-5-2-6-1-7 )DNLmax = + 0.15LSB DNL unchanged

-0.2

-0.1

0

0.1

0.2

1 2 3 4 5 6 7

Sequential current source switchingSymmetrical current source switching


More recent published DAC using symmetrical switching built in 0.35μ/3V analog/1.9V digital, area x10 smaller compared to previous example

(5+5)


• Layout of Current sources -each current source made of 4 devices in parallel each located in one of the 4 quadrants

• Thermometer decoder used to convert incoming binary digital control for the 5 MSB bits

• Dummy decoder used on the LSB side to match the latency due to the MSB decoder


• Current source layout– MSB current sources layout

in the mid sections of the four quad

– LSB current sources on the periphery

– Two rows of dummy current sources added to create identical environment for devices in the center versus the ones on the outer sections


• Note that each current cell has its clocked latch and clock signal laid out to be close to its switch to ensure simultaneous switching of current sources

• Special attention paid to the final latch to have the cross point of the complementary switch control signal such that the two switches are not both turned off during transition


• Measured DNL/INL with current associated with the cells as a variable



I

I/2 I/2

Current Divider

16bit DAC (6+10)- MSB DAC uses calibrated current sources



I

I/2 I/2

Ideal Current Divider

Current Divider Accuracy

I

I/2+dId /2

Real Current Divider

M1& M2 mismatched

d1 d 2d

d d1 d 2

d d

WLd

thWLd GS th

I II

2

dI I II I

ddI 2dV

I V V

+=

−=

⎡ ⎤⎛ ⎞= × +⎢ ⎥⎜ ⎟

− ⎝ ⎠⎣ ⎦

I/2-dId /2

M1 M2M1 M2

Problem: Device mismatch could severely limit DAC accuracy



Dynamic Element Matching

( ) ( )

(1) ( 2 )2 22

1 1o

o

I II

2

1 1I2 2

I2

+=

− Δ + + Δ=

≈

( )( )

(1) 1 o 11 2(1) 1 o 12 2

I I 1

I I 1

= + Δ

= − Δ

/ 2 error Δ1

I1

During Φ1 During Φ2

I2

fclk

Io

Io/2Io/2( )( )

( 2 ) 1 o 11 2( 2 ) 1 o 12 2

I I 1

I I 1

= − Δ

= + Δ



Dynamic Element Matching

( )( )

( )( )( )214

1

2)1(

121)1(

3

121)1(

2

121)1(

1

111

1

1

Δ+Δ+=Δ+=

Δ−=

Δ+=

o

o

o

III

II

II ( )( )

( )( )( )214

1

2)2(

121)2(

3

121)2(

2

121)2(

1

111

1

1

Δ−Δ−=Δ−=

Δ+=

Δ−=

o

o

o

III

II

II

During Φ1 During Φ2

( )( ) ( )( )

( )21

2121

)2(3

)1(3

3

14

21111

4

2

ΔΔ+=

Δ−Δ−+Δ+Δ+=

+=

o

o

I

I

III

E.g. Δ1 = Δ2 = 1% matching error is (1%)2 = 0.01%

/ 2 error Δ1

I1

I2

fclk

Io

Io/2

/ 2 error Δ2

I3 I4

fclk

Io/4Io/4


• Bipolar 12-bit DAC using dynamic element matching built in 1976• Element matching clock frequency 100kHz• INL <0.25LSB!


DAC In the Big Picture

• Learned to build DACs– Convert the

incoming digital signal to analog

• DAC output staircase form

• Some applications require filtering of DAC output reconstruction filter

Analog Post processing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Anti-AliasingFilter

Sampling+Quantization

"Bits to Staircase"

Reconstruction Filter


DAC Reconstruction Filter

• Need for and requirements depend on application

• Tasks:– Correct for sinc droop– Remove “aliases”

(stair-case approximation)

B fs/2

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

DAC

Inpu

t

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

sinc

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

DAC

Out

put

Frequency


Reconstruction Filter Options

• Digital and SC filter possible only in combination with oversampling (signal bandwidth B << fs/2)

• Digital filter– Band limits the input signal prevent aliasing– Could also provide high-frequency pre-emphasis to

compensate in-band sinc amplitude droop associated with the inherent DAC S/H function

DigitalFilter DAC SC

FilterCT

Filter


DAC Reconstruction Filter Example: Voice-Band CODEC Receive Path

Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.

fs= 1024kHz fs= 128kHz fs= 8kHz fs= 8kHz

fs= 8kHz fs= 128kHz fs= 128kHz

fs= 128kHz

fs= 8kHz


SummaryD/A Converter

• D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)

complexity proportional (2B1-1) + B2 – DNL compromise between the two

• Static performance– Component matching

• Dynamic performance– Time constants, Glitches

• DAC improvement techniques – Symmetrical switching rather than sequential switching– Current source self calibration– Dynamic element matching

• Depending of the application, reconstruction filter may be needed


Re-Cap

• ADC Converters:

– Need to build circuits that "sample“

– Need to build circuits for amplitude quantization

Analog Post processing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Anti-AliasingFilter

Sampling+Quantization

"Bits to Staircase"

Reconstruction Filter


MOS Sampling Circuits


Ideal Sampling• In an ideal world, zero

resistance sampling switches would close for the briefest instant to sample a continuous voltage vIN onto the capacitor C

Output Dirac-like pulses with amplitude equal to VINat the time of sampling

• In practice not realizable!

vIN vOUT

CS1

φ1

φ1

T=1/fS


Ideal T/H Sampling

vIN vOUT

CS1

φ1

• Vout tracks input when switch is closed• Grab exact value of Vin when switch opens• "Track and Hold" (T/H) (often called Sample & Hold!)

φ1

T=1/fS


Ideal T/H Sampling

ContinuousTime

T/H signal(Sampled-Data

Signal)

Clock

Discrete-TimeSignal

time


Practical SamplingIssues

vIN vOUT

CM1

φ1

• Switch induced noise power due to M1 finite channel resistance• Finite Rsw limited bandwidth finite acquisition time• Rsw = f(Vin) distortion• Switch charge injection & clock feedthrough• Clock jitter


kT/C Noise

• Switch resistance & sampling capacitor form a low-pass filter • Noise associated with the switch resistance results in Total noise

variance= kT/C @ the output (see noise analysis in Lecture 1)• In high resolution ADCs kT/C noise often dominates overall error

(power dissipation considerations).

vIN vOUT

C

S1RvIN vOUT

CM1

φ1 4kTRΔf


Sampling Network kT/C Noise

Required Cmin as a Function of ADC Resolution

0.003 pF0.8 pF13 pF

206 pF52,800 pF

812141620

Cmin (VFS = 1V)B

For ADCs usually sampling capacitor size is chosen based on having thermal noise smaller or equal to quantization noise:

22 121212 ⎟

⎟⎠

⎞⎜⎜⎝

⎛ −≥→Δ≤FS

BB

BV

TkCC

Tk

For high resolution ADCs oversampling results in reduction of required value for C (will cover in oversampled converter lectures)


Acquisition Bandwidth• The resistance R of switch

S1 turns the sampling network into a lowpass filter with finite time constant:

τ = RC

• Assuming Vin is constant during the sampling period and C is initially discharged

vIN vOUT

CS1

φ1

R

( )τ/1)( tinout evtv −−=


Switch On-Resistance

Example:B = 14, C = 13pF, fs = 100MHzT/τ >> 19.4, R << 40Ω

vIN vOUT

CS1

φ1

φ1

T=1/fS

R

( )

( )

12

12

Worst Case: 1

2 ln 2 1

1 12 ln 2 1

s

in outs

fin

in FS

B

Bs

V V tf

V eV V

T

Rf C

τ

τ

−

⎛ ⎞− = << Δ⎜ ⎟

⎝ ⎠

<< Δ=

<< −−

<< −−


Switch On-Resistance

( ) ( )

( )

( )( )

0

1,2

1 1

1 for

1

DS

D triodeDSD triode ox GS TH DS

ON DS V

ON

ox GS th ox DD th in

o

ox DD th

oON

in

DD th

dIW VI C V V VL R dV

R W WC V V C V V VL L

R WC V VL

RR VV V

μ

μ μ

μ

→

⎛ ⎞= − − ≅⎜ ⎟⎝ ⎠

= =− − −

=−

=− −

Switch MOS operating in triode mode:


Sampling Distortion

in

DD th

outT V12 V V

in

v

v 1 e τ

⎛ ⎞− −⎜ ⎟⎜ ⎟−⎝ ⎠

=⎛ ⎞⎜ ⎟−⎜ ⎟⎜ ⎟⎝ ⎠

Simulated 10bit ADC &T/τ = 10VDD – Vth = 2V VFS = 1VSampling Switch modeled:

Results in HD2=-41dBFS & HD3=-51.4dBFS


Sampling Distortion

10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V

Doubling sampling time (or ½time constant)Results in:

HD2 improved from -41dBFS to -70dBFS ~30dB

HD3 improved from -51.4dBFS to -76.3dBFS ~25dB

Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior


Sampling DistortionEffect of Supply Voltage

10bit ADC & T/τ = 10VDD – Vth = 4V VFS = 1V

10bit ADC & T/τ = 10VDD – Vth = 2V VFS = 1V

• Effect of lower supply voltage on sampling distortionHD3 increases by (VDD1/VDD2)2

HD2 increases by (VDD1/VDD2)


Sampling Distortion

10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V

• SFDR sensitive to sampling distortion -improve linearity by:

• Larger VDD • Higher sampling bandwidth

• Solutions:• Overdesign Larger

switchesIncreased switch

charge injectionIncreased nonlinear S

&D junction cap.• Maximize VDD/VFS

Decreased dynamic range if VDD const.

• Complementary switch• Constant & max. VGS ≠ f(Vin)


Practical SamplingSummary So Far!

22 112

B

BFS

C k TV

⎛ ⎞−≥ ⎜ ⎟⎝ ⎠

( )1 for inON o o ox DD th

DD th

WVg g g C V VV V Lμ⎛ ⎞= − = −⎜ ⎟−⎝ ⎠

( )1 1

2 ln 2 1Bs

Rf C

<< −−

• kT/C noise

• Finite Rsw limited bandwidth

• gsw = f(Vin) distortion

• Switch charge injection • Clock jitter

vINvOUT

CM1

φ1


Complementary Switch

φ1φ1B

φ1

φ1B

gon

gop

goT =go

n + gopgo

•Complementary n & p switch advantages:•Increases the overall conductance•Linearize the switch conductance for the range Vtp< Vin <Vdd-Vtn


Complementary Switch

φ1φ1B

φ1

φ1B

gon

gop

goT =go

n + gopgo

•Complementary n & p switch advantages:Increase in the overall conductanceLinearize the switch conductance for the range |Vth

p|< Vin < Vdd -|Vthn|


Complementary Switch IssuesSupply Voltage Evolution

• Supply voltage scales down with technology scaling• Threshold voltages do not scale accordingly

Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.


Complementary SwitchEffect of Supply Voltage Scaling

gon

gop

goT =go

n + gopgeffective

•As supply voltage scales down input voltage range for constant go shrinksComplementary switch not effective when VDD becomes comparable to Vth

φ1φ1B

φ1

φ1B


Boosted & Constant VGS Sampling

VGS=const.

OFF ON

• Increase gate overdrive voltage as much as possible + keep VGSconstant

Switch overdrive voltage independent of signal level

Error due to finite RON linear (to 1st order)

Lower Ron lower time constant

• Gate voltage VGS =lowDevice offBeware of signal

feedthrough due to parasitic capacitors


Constant VGS Sampling

(= voltage @ the switch input terminal)


Constant VGS Sampling Circuit

VP1100ns

M12

M8

M9

M6

M11VS1

1.5V1MHz

Chold

P

C1 C2

M1 M2

VDD=3V

M3

C3

M5

M4

P

This Example: All device sizes:10μ/0.35μAll capacitor size: 1pF (except for Chold)

P_N

Vg

Va Vb

Sampling switch & C

PB


Clock Voltage Doubler

C1 C2

M10ff

M2Saturation

mode

VP1

PB

VDD=0 3V

P

a) Start–up

0 3V

0 3V 0 0

0 3V 0 (3V-VthM2)

Acquire charge C1 C2

M1Triode

M2off

VP1

PB

VDD=3V

P

3V 0

3V 0

3V 0 3V (3V-VthM2) (6V-Vth

M2)

b) Next clock phase

0 3V



C1 C2

M10ff

M2

VP1

PB

VDD=3V

P

0 3V

0 3V

3V ~6V

3V 0

c) Next clock phase

(6V-VthM2) (3V-Vth

M2) ~ 3V

M2Triode

Acquires charge

• Both C1 & C2 charged to

VDD after one clock cycle



C1 C2

M1 M2

VP1Clock period: 100ns

PB

P_Boost

VDD

2VDD

0

VDD=3V

R1 R2

*R1 & R2=1GOhmdummy resistors added for simulation only

P


Constant VGS Sampler: Φ LOW

• Sampling switch M11 is OFF

• C3 charged to VDDInput voltage

source

M3Triode

C3

M12Triode

M4

OFF

VS11.5V1MHz

Chold1pF

~ 2 VDD(boosted clock)

VDD

VDD

OFF M11OFF

DeviceOFF

VDD=3V


Constant VGS Sampler: Φ HIGH

• C3 previously charged to VDD

• M8 & M9 are on:C3 across G-S of M11

• M11 on with constant VGS = VDD

C31pF

M8

M9 M11

VS11.5V1MHz

Chold1pF

VDD


Constant VGS Sampling

Input Switch VGate

Input Signal

Chold Signal


Complete Circuit

Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.

Clock Multiplier

Switch

M7 & M13 for reliability

Remaining issues:

-VGS constant only for Vin <Vout

-Nonlinearity due to Vth dependence of M11on body-source voltage


Constant Conductance Switch

Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000




OFF




ON

M2 Constant currentconstant gds

M1 replica of M2 & same VGSas M2M1 alsoconstant gds

* Note: Authors report a requirement of 280MHz GBW for the opamp for 12bit 50Ms/s ADC


Advanced Clock Boosting Technique

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314

Sampling Switch



• clk low– Capacitors C1a & C1b charged to VDD– MS off– Hold mode

Sampling Switch

clk low



Sampling Switch

• clk high– Top plate of C1a & C1b connected to gate of sampling switch– Bottom plate of C1a connected to VIN– Bottom plate of C1b connected to VOUT– VGS & VGD of MS both @ VDD & ac signal on G of MS average of VIN &

VOUT

clk high



• Gate tracks average of input and output, reduces effect of I·R drop at high frequencies

• Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S)

• Reported measured SFDR = 76.5dB at fin=200MHz

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Tech. Papers, pp. 314

Sampling Switch


Switch Off-Mode Feedthrough Cancellation

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314

Documents

EE247 Lecture 17 - University of California, Berkeleyee247/fa06/lectures/L17c_f06.pdf · EECS 247 Lecture 17: Data Converters © 2006 H.K. Page 7 DAC Implementation Examples • Untrimmed