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EE105 - Fall 2006Microelectronic Devices and Circuits

Prof. Jan M. Rabaey (jan@eecs)

Lecture 26: Bipolar Junction TransistorAmplifiers – Frequency Response

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Lecture Material

Last lecture– BJT amplifiers

This lecture– Emitter-degenerated CE Amplifier

– Frequency response of BJT Amplifiers

– Designing complex amplifiers

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Administrativia

Lab 8 this week

Lab 9 next week (no written report – just oral at end of lab session)

Last homework will be posted this weekNo lecture on Tu Dec 5 – Make-up lecture scheduled tentatively for December 11 at 2pm (203 McLaughlin)

Final: We December 13, 12:30-3:30pm, 105 North Gate

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Schedule for the rest of the semester

Tu 11/27: BJT Amplifiers (continued) – Complex amplifiers (start)

Th 11/29: Complex amplifiers; Advanced topics (start)

Th Dec 7: Advanced topics (cntd)

Mo Dec 11: Semester overview and review session

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One Last Exercise: Common-Collector Voltage Gain

KCL at the output node: note vπ = vt - vout

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Summary of Two-Port Parameters for CE/CS, CB/CG, CC/CD

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Frequency Response of Common-Emitter

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Frequency Response of Common-Emitter

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Assuming Rsig to be small

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BJT Biasing (Discrete)

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BJT Biasing (2)

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Common-Emitter with Emitter Degeneration

1. What is it?2. DC Bias3. Small-signal 2-port

model4. Output swing

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DC Bias for CEdeg

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CE(degen) Biasing

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Two-Port Model for CEdeg

Input looks like CC Rin =Output looks like CB (see p. 504 for details) Rout = Transconductance: Gm =

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Two-Port Model for CEdeg (cont.)

Find Gm

Voltage Gain:

Is it a good voltage amplifier (vs. CE)?

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Temperature Dependence

Gm of Bipolar strong function of temperature

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Analyzing Complex Amplifiers

Example: Discrete VHF Amplifier

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Multi-Stage Voltage Amplifier

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Cutting Through the Complexity

Two Approaches:

1. Eliminate “background” transistors to reduceclutter

2. Identify the “signal path” between the inputand output

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First Approach: Find I & V Sources

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What’s Left?

Voltage at base ofQ2 is set by totempole

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Second Approach: Find Signal Path

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Identifying the Stages

First stage (or two stages): CS/CB cascodeSecond stage (or two stages): CD/CC voltage buffer

Why does this make sense for a voltage amplifier?

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Find Key Two-Port Parameters

Output resistance of cascode:

( ){ }2222/, ||1(|| SmoocCBCSout RrgrrR π+=

( )666 1 Smoupoc RgrRr +==

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Two-Port Parameters (Cont.)

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Output Resistance and Voltage Gain

Source resistance of the CC stage is the output resistanceof the CD stage (small)

434

,

4,

1111

mommo

CCS

mCCoutout ggg

R

gRR ≈

β+=

β+==

Open-circuit voltage gain Av (last two stages have nearly unity gain):

( )( )76621 1|| omooomv rgrrgA +β−=

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Output Swing: VOUT,MIN

Minimum output voltage: M10, M3 , and Q2 are “suspects”

M10 goes into triode when VOUT = 0.5 V

M3 goes into triode when VSD3 = 0.5 V VOUT = 0.5 V – 0.7 V = -0.2 V

Q2 goes into saturation when VCE2 = 0.1 Vor VBC2 = 0.6 VVOUT = VB2 – VBC2 + VSG3 – VBE4

= 2 V – 0.6 V + 1.5 V – 0.7 VVOUT = 2.2 V

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Output Swing: VOUT,MAX

Maximum output voltage: Q4, M5, and M6 are “suspects”

Q4 goes into saturation when VCE4 = 0.1 V VOUT = 4. 9 V

M5 goes triode when VSD5 = 0.5 V VOUT = 3.8 V

M6 goes triode when VSD6 = 0.5 V VOUT = VS6 – 0.5 V + VSG3 – VBE4

= 3.5 – 0.5 + 1.5 – 0.7 V = 3.8 V

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Insight into the Frequency Response

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Qualitative Insight

Could always do “brute force” open-circuit time constants

CS*-CB is a wideband stage … so is the CD-CC buffer

Look for large RTxCx products: high-impedance nodesare likely candidates

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Node X

“High impedance node” is node X … look at RTxCx

Capacitance:

Cx = Cgd6 + Cμ2 + Cgd3 + CM3

Miller for CDstage (M3)

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Finding the Miller Capacitance CM3

Gain across Cgs3: 33

33 /1 Lm

LgsvC Rg

RA

+=

CD

X

Cgs3

RL3

RL3 = Rin4 =

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Dominant Pole of Voltage Amplifier

CDinCBoutinoutTx RRRRR ,,32 |||| ==

ooomoSmoocTx rrgrRrgrrR β+≅+= π 27662222 ||)1())||(1(||

Thévenin resistance for CX:

Dominant pole: xTxCR≈ω −11