Edgar Sánchez-Sinencio ELEN 607 (ESS) SPRING’15s-sanchez/607 Lect2-2015-Nested Gm-C Amps.pdf · sgg C S V V s H s L m1 m2 3 m3 m1 m2 2 01 02 03 m2 m3 m1 m1 m2 m3 i 0 mf1 m1 mf2

ELEN 607 (ESS) SPRING’15

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Edgar Sánchez-Sinencio

Analog and Mixed-Signal Center at Texas A&M University

Voltage Multistage Transconductance Amplifier Topologies

for LV Power Supply.

• Good voltage gain can be obtained using cascode stages. But these stages

are not amenable for LV power supply.

• Under LV conditions, high voltage can be obtained using cascade amplifiers.

That is growing horizontally, rather than vertically.

• Direct Cascade of simple (inverting) stages gives the required voltage gain

without control of poles and zeroes.

• Dynamic behavior for optimal performance requires feedback (and

feedforward) circuits.

Analog & Mixed-Signal Center (AMSC)

First Approach: Direct Cascade

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2mg1mg CL

inV

Symbolic Representation

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iV 0V

1M 2MxV

1bI2bI

(a)

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(b)

Two Possible Implementations

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i.e., 1 MHz and 10 MHz

How do you bring one pole close to the origin?

-Use feedback, i.e. Miller effect

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2mg1mg LC

inV

pC

1mC

Neglect Cp (i.e., Cp<<Cm1)

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The good news is that:

The poles locations are approximately at:

The bad news is that a zero is at the RHP.

Now we will use a feedforward circuit to cancel the zero at the RHP.

This will impact the complexity and performance of the design.

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LC

No zero

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1mL1m2m1m

in

0

CC/ggC/gC/gCC/CCgss

CC/)sCg(g

)s(V

)s(V)s(H

Now the corresponding H(s) becomes:

Recall that before applying the feedforward we had:

Assume a dominant pole, then

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mp

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g

Cg

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2

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0VinV

Let us consider a higher-order system, i.e. 3rd order.

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1mfg

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Three-stage amplifier topology with NGCC

21

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i

0

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CCCsCCgsCgsgggg

ggg

)s(V

)s(V)s(H

,gg and gg makingBy


Nested Gm-C Compensation Amplifier.

Observe the regularity and simplicity of the reduced expression

30V01

01

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030201

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1

1

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2

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2

22

1

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at located is poledominant that theNote

f ; f ,

f and

f

s1 1

A-H(s)

as written becan poledominant a assuming H(s)order 3 This

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2mC

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1mg 2mg 3mg

mfg

4mg

iV 0V

1mg 2mg

mfg

1mC

(a) Multipath nested miller compensation topology.

FF : NMC

(b) An abstract model for the amplifier proposed by

Castello, et.al.

(c ) The amplifier with multipath miller zero

cancellation.

Multipath Nested Miller Compensation Technology

Potential Feedforward Schemes: An Amplifier Topologies Re-Visit.


iV 0V

1mg 2mg

3mfg

1mC

3mg 4mg

2mfg

1mfg

2mC

3mC

CL

Four stage amplifier topology with NGCC (Fan You et al)

Let Us Now Compare Several Four-Order Topologies

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Comparison of Several Topologies.

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Comparison of Polynomial Coefficients for Four Stage NMC and NGCC Amplifier.

Ph(s)

NMC

NGCC

NMC

NGCC

Z(s)

a1 a2 a3

b1 b2 b3

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3m2m2m4m

gg

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4m3m2m

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ggg

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L3m2m

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CCC

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CCC

4m

3m

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C

0 0 0

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gg

CC

4m3m2m

3m2m1m

ggg

CCC

Design

Complex

Simple


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n Level

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Conceptual multistage amplifier topology with NGCC.

Abstract model.

Nested Gm-C Compensation (NGCC) Nth-Order


iV 0V

1mG 2mG

1mfG

1mC

iV

outV

ddV

ssV1mg

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(a) Representation

(b) Transistor Level

How to Implement a Positive Gm?

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Four stage operational amplifier with NGCC topology

Design Example of a Four-Stage Amplifier


• The dominant pole f1 is determined by GB

• Phase margin (m) is mainly determined by the high frequency poles

• The location of higher-order poles not only influence on the m, but also in settling time

and power consumption.

• For specification requiring Ao > 80 dB, a four-stage (n = 4) is usually required

• Stability considerations for n = 4 impose

4,1,1

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Design Approach

Step 1. Determine f1 based on GB

f1 = GB

Step 2. Determine f2 based on Phase Margin

Example:

f2 = 2 GB, f3 > f2, f4 > f2 m 60o

However, this does not guarantee small settling time

2

1

32

2

43

2

2

1 tan90/1

/1tan90

f

GB

ffGB

ffGB

f

GB oo

m

Design Approach

Step 3. Determine f3, f4 based on settling time and power

a. Sweep f3 and f4 Ts? (settling time)

Numerical Analysis (e.g. MATLAB)

b. Select a set of (f3, f4) with desired power and settling

time

432

3

32

2

21

11

)(

fff

s

ff

s

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s

f

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3

4

f4

f3

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1

2

3

4

5

6

7

8

1 2 3 4 5 6 7 80

20

40

60

80

Phase MarginTs*GB

f4/GB

___

-----

phase

Ts

The phase margin and normalized settling time (TsGB) of an

NGCC amplifier vs. f4/GB.


What is the effect of f4 /GB?

How far should one push f4?

• Trade-off between phase margin versus setting time.

*

*

*

*

*

**

* * * *

+

+

+

+

++

+ + +

0.5 1 1.5 2 2.5 3

3

3.5

4

4.5

5

5.5

6

6.5

7

7.5

8

NMC

NGCC

Ts*GB

Norm

ali

zed

Pow

er

The normalized power consumption of the NGCC and the NMC amplifiers as

a function of the normalized settling time.


How do the Two Topologies Compare for Power Consumption?


More Experimental Results.

Measured Performance of the 4-Stage NGCC Op Amp.

22

oo

0.22mm 0.22mm Area

//20pF10k 20//10k Condition Load

1.0V 1.0V Supply Power

5.0V S2.5V/ Rate Slew

5.2mV 5.2mV Offset Input

58 60 Margin Phase

1.0MHz 610kHz Bandwidth Gain

100dB 100dB Gain DC

1.40mW 0.68mW n ConsumptioPower

pF


OPTIMAL DESIGN OF LOW POWER

NESTED GM-C COMPENSATION

AMPLIFIERS USING A CURRENT-BASED

MOS TRANSISTOR MODEL

X. Xie, M. C. Schneider, S. H. K. Embabi, E. Sánchez-Sinencio

Department of Electrical Engineering

Texas A&M University

College Station, Texas 77843-3128, USA

Low Power Operational Amplifiers

• Applications: mobile communication & portable devices

• Major concerns: power, stability, area and speed.

• Design approach:

– Low voltage — multistage cascading.

Techniques for solving stability problem:

• Nested Miller Compensation (NMC)

• Nested Gm-C Compensation (NGCC)

– Low operating current — weak or moderate inversion.

• Optimal design in moderate inversion

• Continuous MOSFET model

Topology of Three-stage NGCC Amplifier

• feedforward path gmf1 and gmf2 to cancel

RHP zeros.

• Transfer function:

Making gmf1 = gm1 and gmf2 = gm2 gives:

Rewritten as:

Phase margin:

32

2

21

321

321

11)(

)()(

ff

s

f

s

f

kkks

kkk

sV

sVsH

i

o

+ + -

-

-

Vi

gm1

Cm2

gm2gm3

gmf2

gmf1

CL

(Cm3)

Vo

Cm1

21

3

21223

2

132321

2111

2

2221321

)(

)()(

)(

)(

mmLmmmmfmmmmooo

mmmmfmmmfmmmm

i

o

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sV

sV

oi

mii

g

gk

mi

mii

C

gf

)(

1tan90

3

2

1

f

GB

GB

fPM o

21

3

213

2

132321

321

)(

)(

mmLmmmmmmooo

mmm

i

o

CCCsCCgsCgsgggg

ggg

sV

sV

We define:

— unity gain frequency

— dc gain1

11

m

m

C

gf

321 kkkAo

Topology of Four-stage NGCC Amplifier

Compared to three-stage NGCC:

• easier to obtain high dc gain,

• more complicated design,

• potentially more power

consumption.

• Transfer function:

• Phase margin:

• Transfer function of an n-stage

NGCC amplifier:

432

3

32

2

21

0

0

11fff

s

ff

s

f

s

f

sA

A

sV

sV

i

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1

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2

43

2

2

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tan90

1

1tan90

f

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ffGB

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f

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o

o

n

ii

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s

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s

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sA

A

sV

sV

2

1

32

2

21

0

0

...11

gmf1--

+

Vi

gm1

+ + -

-

-

gm2gm3

gm4

gmf2

gmf3

Cm1

Cm2Cm3

CL

(Cm4)

Vo

Modification on Low Power Three-stage NGCC

Significant parasitic effect:

— very large transistors forweak inversion design,

— long channel transistors used for high dc gain.

Cm1

gm1

+ + -

-

-

Vi

Cm2

gm2 gm3

gmf2

gmf1

CL

Vo

C1C2 C3

• Modified transfer function:

• where

32

2

21

0

2

210

11

)(

ff

s

f

s

f

As

sasaAsH

3

2

2

32

221

12

)(

o

m

oo

m

g

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gg

CCCka

3

3

2

211k

g

Ckka

o

• Ci — parasitic capacitance at each output node,

• — phase delay due to the current mirror at second stage.

21

2

1

1

2

23

2

2

13

2

3

3

21

2

2

33

21

3

3

2

3

2

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22

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1

1

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m

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m

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C

C

C

C

C

g

g

g

gf

ff

g

gf

g

gff

111 mCC 222 m

CC

Modification on Low Power Three-stage NGCC

(cont.)

Moderate inversion:

— good stability,

— optimization of power, speed & area.

with and

11ff

Ex: f1 = GB, f2 = 2GB, f3 = 4GB, Cm1 = Cm2 = 8 pF, CL = 20 pF,

then gm1 = 50 S, gm2=100 S, gm3=500 S,

For go3=100 S (RL), C1=1 pF, C2=3 pF, C3= 6 pF

Assume = 0,

Then and 2266.0 ff

3367.0 ff

Current-Based Transistor Model

• Features of ACM model:

– physics-based model,

– universal and continuous expression for any inversion,

– independent of technology, temperature, geometry and gate voltage,

– same model for analysis, characterization and design.

• Main design equations: (design parameters: I, gm, if)

2

11 f

mt

i

ng

I

1122 2

ft

T iL

f

11

1

ftox

m

iC

g

L

W

411 f

t

DSAT iV

12ng

IC

g

L

W

mt

tox

m

I drain current in transistorgm transconductance in saturation

n slope factor

t thermal voltage

if inversion level of the transistor defined as

, where

is the normalization current.

if << 1 weak inversion,

if >> 1 strong inversion.

sf IIi L

WnCI t

oxs2

2

Specifications and Design Procedure

• Specifications:

– load 10 k/20 pF

– gain bandwidth GB=1 MHz

– dc gain A0 > 100 dB

– phase margin PM > 60o

– 0.2% settling time < 1S

– power consumption: minimum

• Other Specs can be included

( if determined by gm, I, and if ):

– noise,

– slew rate,

– common mode rejection.

Specs. (gain, power, PM,

GB, settling time, etc.)

Determine fi

Given Cmi,

Determine gm

Choose either if or I,

calculate the other and

W/L, select a length L.

Hspice simulation, all

specs satisfied? (YES/NO)

Layout, extraction, simulation

and check specs? (YES/NO)

NO

YES

NO

Fabrication

YES

Implementation of Three-Stage NGCC Amplifier

Remarks:

• Ideally, f1 = GB, f2 = 2GB, f3 = 4GB,

Choose f2=3GB, f3=5GB to

compensate large parasitic effect.

• Long channel to obtain adequate gain

— cause large parasitic effect.

Vdd=2V

M0

MP3 MP1 MP2 MP0 MP4 MP5

MP6

M3

MIN1 MIN2

M1 M2 M4

Cm1

M5 M6

M7M8

Cm2V- V+

gmf1

Vb1 Vb1

IB=5A

gm1 gm2 gm3 gmf2

Vo

M9

RL CL

Transistor NO. W(m) L(m) if

M1 M4 118 4.2 20

M0, M5 218 4.2 20

M6, M7, M9 618 4.2 20

M8 2518 4.2 20

MIN1, MIN2 2018 4.2 4

MP0 MP3 218 4.2 80

MP4, MP5 618 4.2 80

MP6 3318 4.2 80

Implementation of Four-Stage NGCC Amplifier

Remarks:

• f1=GB, f2=2GB, f3=5GB, f4=6GB

• shorter length — small parasitic effect

• lower inversion level than 3-stage one.

• Same implementation and same fi for

reference opamp (low-voltage strong

inversion 4-stage)

MP3 MP1 MP2 MP0 MP4 MP5 MP6 MP7

MP8

MIN1 MIN2V- V+

Vb

M1 M2 M3 M4 M5 M6

M7 M8

M9

M10

M11 M12Vb

Vb

Ib=6ACm1 Cm2 Cm3

CL

RL

Vout

gm1 gmf1 gm2 gm3 gm4 gmf2 gmf3

Vdd=2V

M0

Transistor NO. W(m) L(m) if

M1 M4 410.8 1.8 6

M0, M5 810.8 1.8 6

M6, M7, M11 810.8 1.8 6

M8, M9, M12 2010.8 1.8 6

M10 6010.8 1.8 6

MIN1, MIN2 818 1.8 6

MP0 MP3 218 1.8 30

MP4, MP5 218 1.8 30

MP6, MP7 518 1.8 30

MP8 2418 1.8 30

Specifications Three-Stage Four-Stage Four-Stage(ref.)

Power Consumption Minimum 0.28 mW 0.30 mW 0.93 mW

DC Gain 100 dB ~ 100 dB ~ 105 dB ~ 110 dB

Gain Bandwidth 1.0 MHz 1.08 MHz 1.03 MHz 1.09 MHz

Phase Margin > 60o

59.5o

62.7o

61.2o

0.2% Settling Time (100 mV) < 1 S 0.77 S 0.55 S 0.53 S

THD (1kHz 1VP-P) - 84.8 dB - 88 dB - 55.8 dB

1% THD Input (1kHz) 1.36V 1.38V 1.26V

Active Area (relative area) 0.01mm2 (1.75) 0.0052 mm

2 (0.91) 0.0057 mm

2 (1)

min if , max if 4 , 80 6 , 30 100 , 130

Simulation Results of NGCC Amplifiers

(VDD = 2 V, ZLOAD = 10 k/20 pF)

* 1.2 m AMI n-well CMOS technology

* BSIM (HSPICE level 13) simulation

Experimental Results

* The output stage of the reference op amp is realized with a

PMOS transistor for reduction of power.

Specifications Three-Stage Four-Stage Four-Stage(ref.)

Power Consumption Minimum 0.26 mW 0.28 mW 0.63 mW

DC Gain 100 dB ~ 96 dB ~ 105 dB ~ 100 dB

Gain Bandwidth 1.0 MHz 1.10 MHz 1.05 MHz 900 kHz

Phase Margin > 60o

56.7o

62.0o

63.6o

THD (1kHz 1VP-P) - 67.7 dB - 67.5 dB - 28.5 dB

1% THD Input (1kHz) 1.13 V 1.11 V 0.94 V

Active Area(Relative Area)

0.01mm2

(1.49)0.0052 mm

2

(0.78)0.0067 mm

2

(1)

Frequency Response

3-stage NGCC amplifier 4-stage NGCC amplifer

Response to 100 kHz 1Vp-p sine wave

3-stage NGCC amplifier 4-stage NGCC amplifier

2 S/DIV 2 S/DIV

Step Response with 100 kHz 100 mV Input


2 S/DIV2 S/DIV

Step Response with Large Signal (1 kHz 1V)

200 S/DIV200 S/DIV


Conclusions

• Using a new MOSFET model, NGCC amplifiers can

be designed in moderate inversion yielding optimal

trade-off design.

• With same or better performance, low power

amplifiers consume 65% less power than low voltage

(strong inversion) design.

• Four-stage op amp has better overall performance with

much less area and without dissipating evidently more

power.

• Three-stage one benefits for the reduction of design

complexity.

ELEN 607 (ESS) SPRING’06

V i

-A V1

Cm

Cp CL

Vo

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gm

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2

21

Review: Cascade with Miller effect

-AV2vi vo

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(b)

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R1

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R2

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Vo

Vi

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Vi

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11

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Pole splitting via RC feedback branch

vi-A V1 -AV2

Cm

Cp

v

(c)

AVf1

1/sCL-A1Vi

Vi Vo

Rf

R2

1/sCm

R

1

-A2Vg

Vg

AfVi

Transfer Function

RfCmR1)RfCpR1(CmR2RfCpR1CLR2RfCmR11(CLR2RfCpRs

R2AfCmR1))-CmR2RfA1s(CpR1R2Af-A1RfA2-(-R2Af-2

sVo

Vi

R2RfRfA2CmR1)R2CmR1R2CpR1CmR2RfCLR2Rf(

1

s

CLCmsCmgmsgogo

gmfgmsCmgmgm

Vi

Vo2221

)1(21

12

1

122

11

CmRACmRRgmwp

CL

gmwp

22

)11(

211

gmfgmCm

gmgmwz

Review: Feedforward compensation

vi-AV1 -AV3 vo

(d)

AVf1

CmCL

-AV2

1/sCL

Vi

1/sCm

V1Vo

Rf

R3

-A3V1

AfVi

-A1Vi

R1

-A2V1

R2

V2

Cm

gw gmgmp

2

02|

gm2)CmR2(gm1

gm1-211

CmRw RRfp

3

2|

CmRfR3

R3)(Rf-32

gm3R2)gm3R1R1gmfgm2R2gm1Cm(R1gmfR2

gm3R1gmfgm11

zw

Creating and internal zero cancellation DFCFC

Damping factor frequency controlled compensation (DFCFC)

Amplifier Comparisons

4 stage NGCC Amplifier.

3 stage DFCFC Amplifier

Parameters NGCC DFCFC

Av (dB) 100.3 100.4

GBW (MHz) 8.21 8.23

Phase Margin(`) 70 75

0.2% Settling Time(ns) 373 398

Slew Rate(+) (V/us) 11.2 8.2

Slew Rate(-) (V/us) -7.1 -6.7

CMR (V) 1.25 0.97

CMRR (dB) 63.02 28.55

PSRR+ (dB) 49.62 24.05

PSRR- (dB) 29.1 20.48

Input Referred Offset (v) 290n -4.13u

Active Area (um2) 233.4 228.88

Power Consumption (mW) 1.2 0.4

M4M5

M6 M7 M10M11

M14M15

M18 M20

M21

M22

M19

M3M8

M9 M12 M13 M16 M17

Vi+Vi-

Cm1

Cm2Cm3

Vb1

Vb2Vb3

Vdd

Vss

Vout

M1 M2

4 stage NGCC Amplifier.

# M1 M2 M3 M4 M5 M6 M7 M8

Size 49/.4 46/.4 36/.4 10/.4 10/.4 38/.4 6.5/.4 38/.4

# M9 M10 M11 M12 M13 M14 M15 M16

Size 38/.4 6.5/.4 22/.4 22/.4 22/.4 10/.4 20/.4 30/.4

# M17 M18 M19 M20 M21 M22

Size 30/.4 20/.4 70/.4 20/.4 23/.4 44/.4

Design Summary

M3

Vdd

Vss

M1 M2Vi- Vi+

M16M4 M5

M6

M7

M8

M9Vb

Va

Vc

M11M10 M13 M14

M12

M15

Cm1

Cm2

M17

M19

M18

Vout

M20

3 stage DFCFC Amplifier

.

# M1 M2 M3 M4 M5 M6 M7 M8 M9 M10

Size 38/.4 38/.4 48/.4 1.2/.4 1.2/.4 1.2/.4 1.2/.4 1.2/.4 1.2/.4 18/.4

# M11 M12 M13 M14 M15 M16 M17 M18 M19 M20

Size 18/.4 30/.4 22/.4 45/.4 45/.4 9/.4 3/.4 31/.4 95/.4 53/.4

References

S. Pernici, “A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested

Miller Compensation,” IEEE J. Solid-State Circuits, Vol. 28, No. 7, pp. 758-763, July 1993.

F. You, S.H.K. Embabi and E. Sánchez-Sinencio, “Multistage Amplifier Topologies with

Nested Gm-C Compensation,” IEEE J. of Solid-State Circuits, Vol. 32, No. 12, pp. 2000-2011,

December 1997.

X. Xie, M.C. Schneider, E. Sánchez-Sinencio and S.H.K. Embabi, “ Sound Design of low power nested

transconconductance-capacitance compensation amplifiers” Electronics Letters, Vol. 35, No. 12, pp956-

958, June 1999

K.N. Leung, P.K. T. Mok, W.-H. Ki, and J. K. O. Sin, “ Three-Stage Large Capacitive Load

Amplifier with Damping Factor-Control Frequency Compensation, “IEEE J. of Solid-State

Circuits, Vol. 35, No. 2, pp. 221-230, February 2000

B.K. Thandri, , and J. Silva-Martinez, “ A Feedforward Compensation Scheme for Multi-Stage Amplifiers

with No-Miller Capacitors”, IEEE J. Solid State Circuits, Vol. 38, pp. 237-243, Feb. 2003.


References


Author(s): Cherry Edward M.

Universal basis for ranking small-signal aspects of compensation techniques for

operational amplifiers INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND

APPLICATIONS Volume: 39 Issue: 11 Pages: 1105-1144 DOI: 10.1002/cta.689

Published: NOV 2011

Author(s): Peng Xiaohong; Sansen Willy; Hou Ligang; et al.

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

Source: IEEE JOURNAL OF SOLID-STATE CIRCUITS Volume: 46 Issue: 2 Pages: 445-

451 DOI: 10.1109/JSSC.2010.2090088 Published: FEB 2011

Author(s): Ito Rui; Itakura Tetsuro

Title: Phase Compensation Techniques for Low-Power Operational Amplifiers

Source: IEICE TRANSACTIONS ON ELECTRONICS Volume: E93C Issue: 6

Pages: 730-740 DOI: 10.1587/transele.E93.C.730 Published: JUN 2010

Reading Material

Documents

Edgar Sánchez-Sinencio ELEN 607 (ESS) SPRING’15s-sanchez/607 Lect2-2015-Nested Gm-C Amps.pdf · sgg C S V V s H s L m1 m2 3 m3 m1 m2 2 01 02 03 m2 m3 m1 m1 m2 m3 i 0 mf1 m1 mf2