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ECE2030 Introduction to Computer Engineering
Lecture 12: Building Blocks for Combinational Logic (3) Adders/Subtractors, Parity Checkers
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech
Half Adder (1-bit)A B S(um
)C(arry)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1HalfAdder
A B
S
C
Half Adder (1-bit)A B S(um
)C(arry)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
AB C
BABABAS
A
BSum
Carry
Full AdderCin A B S(um
)Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
FullAdder
A B
S
Cout
Carry In(Cin)
Full AdderCin A B S(um
)Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
00 01 11 10
0 0 1 0 1
1 1 0 1 0
CinAB
BACin
B)(ACin)BACin(
)BABA(CinAB)BACin(
BACinCinABBACinBACinS
00 01 11 10
0 0 0 1 0
1 0 1 1 1
CinAB
ABCinACinBCout
00 01 11 10
0 0 0 1 0
1 0 1 1 1
CinAB
B)Cin(AAB)BABACin(ABCout
Or
Full AdderBACinS
A
B
Cin
Cout
S
H.A. H.A.
B)Cin(AABCout
Full Adder
Cout
S
HalfAdder
S
C
A
B
HalfAdder
S
C
A
BB
A
Cin
BACinS B)Cin(AABCout
4-bit Ripple Adder using Full Adder
FullAdder
A B
CinCout
S
S0
A0 B0
FullAdder
A B
CinCout
S
S1
A1 B1
FullAdder
A B
CinCout
S
S2
A2 B2
FullAdder
A B
CinCout
S
S3
A3 B3
Carry
A
BS
C
Half Adder
A
B
CinCout
S
H.A. H.A.
Full Adder
Full Adder Propagation Delay
S0
A0 B0
Carry Cin
11stst Stage Critical Path Stage Critical Path = 3 gate delays= 3 gate delays= D= DXORXOR+D+DANDAND+D+DOROR
Full Adder Propagation Delay
S0
A0 B0
Cin
S1
A1 B1
22ndnd Stage Critical Path Stage Critical Path = 2 gate delays= 2 gate delays= D= DANDAND+D+DOR OR
(Since 1(Since 1stst Critical path Critical path> D> DXORXOR))
11stst Stage Critical Path Stage Critical Path = 3 gate delays= 3 gate delays= D= DXORXOR+D+DANDAND+D+DOROR
Issue of 4-bit Ripple Adder
Critical Path = DCritical Path = DXORXOR+4*(D+4*(DANDAND+D+DOROR) for 4-bit ripple adder ) for 4-bit ripple adder (9 gate (9 gate levels)levels)
For an For an NN-bit ripple adder-bit ripple adderCritical Path Delay Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays~ 2(N-1)+3 = (2N+1) Gate delays
S0
A0 B0
Cin
S1
A1 B1
S2
A2 B2
S3
A3 B3
Carry
Issue of Ripple Adder• Carry propagationCarry propagation is the main issue in
an N-bit ripple adder• A faster adder needs to address the
serial propagation of the carry bit• Let’s re-examine the equation for full
adders
Carry GenerateGenerate & PropagatePropagate
)B(ACBAC iiiii1i
)(propagate BAp
(generate) BAg
iii
iii
iii1i CpgC
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Note that all the carry’s are Note that all the carry’s are only dependent on input A and only dependent on input A and
B and CB and C
4-bit Carry-Lookahead Adder (CLA)
Carry Lookahead LogicCarry Lookahead Logic
g1g1 p1p1
A1 B1S1S1
C1C1
g2g2 p2p2
A2 B2S2S2
C2C2
g3g3 p3p3
A3 B3S3S3
C3C3
g0g0 p0p0
A0 B0S0S0
C0C0C4C4
)(propagate BAp
(generate) BAg
iii
iii
iiii BACS
InefficientInefficient Implementation of Carry Lookahead Logic
A0 B0S0S0A1 B1S1S1
C0C0
A2 B2S2S2A3 B3S3S3
C1C1C2C2C3C3
C4C4
g0g0p0p0g1g1p1p1g2g2p2p2g3g3p3p3
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Reuse some gate output results Reuse some gate output results Little ImprovementLittle ImprovementCarry Delay is 4*DCarry Delay is 4*DANDAND + 2*D + 2*DOROR for Carry C for Carry C44
Implementation of Carry Lookahead Logic
C4C4
A0 B0S0S0A1 B1S1S1
C0C0
A2 B2S2S2A3 B3S3S3
0012301231232333334
00120121222223
0010111112
0001
CppppgpppgppgpgCpgC
CpppgppgpgCpgC
CppgpgCpgC
CpgC
Carry Lookahead LogicCarry Lookahead Logic
Only 3 Gate Delay for each Carry COnly 3 Gate Delay for each Carry C ii
= = DDANDAND + 2*D + 2*DOROR
C3C3g3g3 p3p3 g0g0 p0p0C2C2g2g2 p2p2 C1C1g1g1 p1p1
4 Gate Delay for each Sum S4 Gate Delay for each Sum Sii
= = DDANDAND + 2*D + 2*DOROR + D+ DXORXOR
Cascading CLA
• Similar to ripple adder, but different latency
CLA
A B
CinCout
S
S[3:0]
A[3:0] B[3:0]
CLA
A B
CinCout
S
S[7:4]
A[7:4] B[7:4]
4 4
44 4 4
CLA
A B
CinCout
S
S[11:8]
A[11:8]B[11:8]
4
44
CLA
A B
CinCout
S
S[15:12]
A[15:12]B[15:12]
4
44
Delay of each stageis 3 gate levels instead of 9 of ripple adders
Subtractor Design
• A – B = A + (-B)– Take 2’s complement of B – Perform addition of A and 2’s complement of B
FullAdder
A B
CinCout
S
S0
A0
FullAdder
A B
CinCout
S
S1
A1
FullAdder
A B
CinCout
S
S2
A2
FullAdder
A B
CinCout
S
S3
A3
B0B1B2B3
C
Subtract
Overflow/Underflow for Signed Arithmetic
01001000 (+72)00111001 (+57)-------------------- (+129)
What is largest positive number represented by 8-bit?
8-bit Signed number addition
10000001 (-127)11111010 ( -6)-------------------- (-133)
8-bit Signed number addition
What is smallest negative number represented by 8-bit?
Overflow/Underflow DetectionCn-1 An-1 Bn-1 Sn-1 Cn OF
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
• Examine the MSB bit• Bottom line:
– P: positive; N: negative
– N + N = N – P + P = P– P+N or N+P always
fall into the range • E.g. -128+P cannot be
smaller than -128 or bigger than 127
• Problem lies in– N+N = P– P+P = N
Discarded
Overflow/Underflow DetectionCn-1 An-1 Bn-1 Sn-1 Cn OF
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 1 1 0
BACABCOF
Discarded
n1n CCOF
or
Overflow/Underflow Detection
FullAdder
A B
CinCout
S
S0
A0 B0
FullAdder
A B
CinCout
S
S1
A1 B1
FullAdder
A B
CinCout
S
S2
A2 B2
FullAdder
A B
CinCout
S
S3
A3 B3
Carry
Overflow/Underflow
n-bit Adder/Subtractorn-bit Adder/SubtractorOverflow/Underflow
Cn
Cn-1
Overflow/Underflow Example
01001000 (+72)00111001 (+57)-------------------- (+129)
8-bit Signed number addition
10000001 (-127)11111010 ( -6)-------------------- (-133)
8-bit Signed number addition
Cn-1 =
Cn =
Cn-1 =
Cn =
Parity Circuits
• To detect single bit error during transmission• Parity bit
– Even parity: even number for data+parity– Odd parity: odd number for data+parity
• Single parity bit – Cannot detect 2 bit error– Cannot correct the single bit error
Sender Receiver
N-bit data
Parity bit
Even Parity Generation
D0
D1
D2
D3
P_GEN
P_GEN = D0 D1 D2 D3
P=1 if odd number of inputs is 1P=0 if even number of inputs is 1
Sender Receiver
4-bit data
Parity bit (P_GEN)
Even Parity Detection
Sender Receiver
4-bit data
Parity bit (P_GEN)
D0
D1
D2
D3
Detection
P_GEN
P_RECV
P_RECV = D0 D1 D2 D3DETECTION = P_GEN P_RECV
DETECTION=1 if P_GEN P_RECV
Parity Detection Example
D3=0
D2=1
D1=1
D0=1
P_GEN=1
Sender Receiver
4-bit data
Parity bit (P_GEN)
0111
1
Parity Detection Example
Sender Receiver
4-bit data
Parity bit (P_GEN)
D3=0
D2=1
D1=0
D0=1
Detection=1
P_GEN=1
P_RECV=0
0101
1
Error occur during transmission
