Dual Core System-on-Chip Design to Support Inter-Satellite Communications

Liza RodriguezAurelio Morales

EEL 6935 - Embedded SystemsDept. of Electrical and Computer

EngineeringUniversity of Florida

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OutlineOutline

• IntroductionIntroduction• Picosatellite Demostrator DesignPicosatellite Demostrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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OutlineOutline

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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• Satellites that provide multi-point sensing• Low cost, redundancy, flexibility• Types of DSS:

• Formation Flying: strict formation• Clustering Mission: satellites are loosely coupled

around each other• Virtual Satellite Mission (fractioned mission): a

satellite has its subsystems divided onto multiple crafts (computing, imaging, etc.)

Distributed Satellite System (DSS)Distributed Satellite System (DSS)

IntroductionIntroduction

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IntroductionIntroduction

DSS in Low Earth Orbit (LEO)DSS in Low Earth Orbit (LEO)

• Small satellites deployed at the same time in multiple orbits• Use for disaster monitoring prevention• Ad-hoc network for multipoint sensing like WSN• Challenges:

• Attitude and orbit control, intersatellite links, on-board computing

• Deal with perturbations: Earth’s geophysical forces, solar radiation

• Network connectivity and topology over time

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Distributed Computing RequirementsDistributed Computing Requirements

IntroductionIntroduction

• Node LevelNode Level• At Individual satellite level• Store and forward data using the network:

• High priority apps using Client/Server. Payload data through the network such imaging data

• Low priority apps using Peer-to-Peer telemetry. Location and velocity changes, “byte” size payload data (GPS)

• Network LevelNetwork Level• Applied to multiple satellites• Provide adaptable and redundant ground-link

communication schemes, main “sink” to ground• React proactively and reactively to their environment

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IntroductionIntroduction

MotivationMotivation

• Meet requirements for processing and network capabilities in “cluster” of satellites in the presence of space disturbances

ProposalProposal

• Dual core System-on-Chip design using a general purpose soft-core processor and a specific core for real-time applications, such as agents

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AgendaAgenda

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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• Use of embedded hardware technology• Standard picosatellite platform CubeSat• For fast prototype, COTS components/boards:

• Flight OBC and satellite chassis from Pumpkin• Power module from Clyde-Space• SGR-05 GPS module from SSTL• MHX transceiver from Microhard Systems• PF5100 Virtex-4 FPGA FX60 Board for SoC• IEEE 802.11 PC/104 Board from Elcard

Picosatellite Demonstrator DesignPicosatellite Demonstrator Design

PrototypePrototype

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PrototypePrototype

CubeSat Platform with Flight Module, IEEE 802.11, FPGA and development boards

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PrototypePrototype

MHX 900 MHz Transceiver PF5100 Board with Virtex-4 FPGA

SGR-05U – Space GPS ReceiverFlight module and

satellite Chassis

Power Module

IEEE 802.11 Board

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• 1999, CalPoly and Stanford University developed specs to help universities worldwide perform space exploration.

• Very small satellite • Use COTS components• 10x10x10 cm structure• Weight of 1 Kg• Also in 2U and 3U sizes

CubeSatCubeSat

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Demonstrator Satellite Architecture

• FPGA board, IEEE 802.11 board, camera as payloads.

• Architecture controlled by the Flight OOn-BBoard CComputer (FM430 OBC)

• SoC to act as HW/SW mediator for:

• Hard and soft resets• Sleep mode

• SoC also used as interface between various buses

Demonstrator Satellite ArchitectureDemonstrator Satellite Architecture

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AgendaAgenda

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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Dual Core Processor DesignDual Core Processor Design

LEON3 ProcessorLEON3 Processor

• Synthesisable VHDL model of 32-bit processor compliant with SPARC V8 architecture

• Suitable for SoC designs

JOP ProcessorJOP Processor

• JJava OOptimized PProcessor• Enables real-time Java functionality• Smallest and fastest Java core

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LEON3 ProcessorLEON3 Processor

Dual Core Processor DesignDual Core Processor Design

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Dual Core Processor DesignDual Core Processor Design

LEON3 core and JOP core in a FPGA

FPGA SoC designFPGA SoC design

AMBA = AAdvanced MMicrocontroller BBus AArchitecture

APB = AAdvanced PPeripheral BBus

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Design ConsiderationsDesign Considerations

Dual Core Processor DesignDual Core Processor Design

• Memory sharing system between LEON3 and JOP for access to external RAM

• Cache between cores must maintain coherency

• Reconfiguration in cases of single event upsets (SEUs) or single event latch-ups (SELs)

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• System must have low low memory footprintmemory footprint, including OS and network stack

• System must be real-timereal-time• CLDCCLDC and pjavapjava are designed

for devices with intermittent network connection, slow processors, limited memory (e.g. mobile phones, PDAs), making them ideal for JOP core

Memory Footprint Comparison

CLDC = CConnection LLimited DDevice CConfiguration

pjava = PersonalJava

JADE= JJava AAgent DEDEvelopment Framework

LEAP =LLight EExtensible AAgent PPlatform

CORBA = CCommon OObject RRequest BBroker AArchitecture

Multi-layer software designMulti-layer software design

Dual Core Processor DesignDual Core Processor Design

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Hardware and software layer designHardware and software layer design

Dual Core Processor DesignDual Core Processor Design

LEON3 and JOP in FPGA:

• Reduce memory footprint• Increase FPGA utilization• Enable Java apps, such as

Agents, for real-time apps

RTEMS = RReal-TTime EExceutive for MMultiprocessor SSystems

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System-on-Chip Block DiagramSystem-on-Chip Block Diagram

Detailed System-on-Chip designDetailed System-on-Chip design

Dual Core Processor DesignDual Core Processor Design

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OutlineOutline

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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• Max Frequency of 37.398 MHz• WCET found between:

• LEON3 and AMBA memory controller• LEON3 and JOP AHB Master• JOP cache and JOP address bus

• Speed optimization is needed to satisfy IEEE 802.11 MAC. Trade-off between area and speed

Dual Core Processor ImplementationDual Core Processor Implementation

Timing ResultsTiming Results

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Dual Core Processor ImplementationDual Core Processor Implementation

• On-chip or off-chip memory?• Speed and power requirements• On-chip: fast but increase power consumption and area• Power consumption of SoC design: 2.33W (1.76W in

memory interfacing), using XPower from Xilinx

Memory Trade-offMemory Trade-off

Resource UtilizationResource Utilization

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OutlineOutline

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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ProcedureProcedure

Network Topology ReconfigurationNetwork Topology Reconfiguration

• HW & SW are discovered• Network topology can be reconfigured

• Stage 1: Startup FPGA Bus System & LEON3• LEON3 started, id and starting tasks discovered

• Stage 2: Startup JOP & JADE-LEAP• Start Java application with argument passing to main

host and services required• Stage 3: Network Topology Refresh

• Initialize, check or change the network topology

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OutlineOutline

• IntroductionIntroduction• Picosatellite Demonstrator DesignPicosatellite Demonstrator Design• Dual Core Processor DesignDual Core Processor Design• Dual Core Processor ImplementationDual Core Processor Implementation• Network Topology ReconfigurationNetwork Topology Reconfiguration• ConclusionsConclusions

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• A COTS solution for picosatellite including a SoC design that meets CubeSat platform was introduced.

• LEON3 IP and JOP IP cores were used to meet strict requirement of low memory footprint, Java functionality and real-time operation

• An Java agent software was proposed to support inter-satellite communication based on IEEE 802.11 wireless connectivity

ConclusionsConclusions

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ReferencesReferences

• http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273 http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4584273 • http://www.cubesat.org/ http://www.cubesat.org/ • http://en.wikipedia.org/wiki/CubeSat http://en.wikipedia.org/wiki/CubeSat • http://www.cubesatkit.com/index.html http://www.cubesatkit.com/index.html • http://www.derivation.com/products/pf5100.htmlhttp://www.derivation.com/products/pf5100.html • http://www.clyde-space.com/products/electrical_power_systems/cubesat_power http://www.clyde-space.com/products/electrical_power_systems/cubesat_power • http://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdf http://www.sstl.co.uk/assets/Downloads/SGR-05U%20v1_13.pdf • http://www.data-connect.com/Microhard_MHX-910.htm http://www.data-connect.com/Microhard_MHX-910.htm • http://www.gaisler.com/doc/leon3_product_sheet.pdf http://www.gaisler.com/doc/leon3_product_sheet.pdf

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Questions?Questions?