DS90UB913A-Q1 25MHz 100MHz 10および12 FPD-Link IIIDS90UB913A-Q1 JAJSG55F –MAY 2013–REVISED JANUARY 2020 参考資料 DS90UB913A-Q1 25MHz～100MHz、10および12ビットのFPD-Link

DSP, FPGA/

µ-Processor/

ECU

Deserializer

DS90UB913A-

Q1

Serializer

FPD-Link III

Bidirectional

Control Channel

DS90UB914A-

Q1

Bidirectional

Control BusBidirectional

Control Bus

Parallel

Data InParallel

Data Out

10 or 12

2 2

Megapixel

Imager/Sensor

10 or 12

GPO GPIO

4 4

2

HSYNC,VSYNC

2

HSYNC,VSYNC

Copyright © 2016, Texas Instruments Incorporated

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Folder

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英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SNLS443

DS90UB913A-Q1JAJSG55F –MAY 2013–REVISED JANUARY 2020

参参考考資資料料

DS90UB913A-Q1 25MHz～～100MHz、、10おおよよびび12ビビッットトののFPD-Link IIIシシリリアアラライイザザ

1

1 特特長長1• 車載アプリケーション用に AEC-Q100 認定済み

– デバイス温度グレード 2：動作時周囲温度　　　　-40°C～+105°C

• 25MHz～100MHz の入力ピクセル・クロックに対応

• データ・ペイロードをプログラム可能– 100MHz までの 10 ビット・ペイロード– 75MHz までの 12 ビット・ペイロード

• 継続的な低レイテンシの双方向制御インターフェイス・チャネル、400kHz の I2C をサポート

• 組み込みクロックと DC バランスされたコーディングにより AC カップリング相互接続に対応

• 15m までの同軸、または 20m までのシールド・ツイストペア・ケーブルを駆動可能

• 堅牢な同軸ケーブル給電 (PoC) 動作• 4 つの専用汎用入出力• シリアライザへの 1.8V、2.8V、3.3V 互換のパラ

レル入力• 1.8V の単一電源• ISO 10605 および IEC 61000-4-2 ESD に準拠• シリアライザの小さな占有面積 (5mm × 5mm)

2 アアププリリケケーーシショョンン• 車載用

– サラウンド・ビュー・システム (SVS)– フロント・カメラ (FC)– リアビュー・カメラ (RVC)– センサ・フュージョン– ドライバ・モニタ・カメラ (DMS)– リモート衛星レーダー、ToF、LIDAR センサ

• セキュリティと監視• マシン・ビジョン・アプリケーション

3 概概要要DS90UB913A-Q1デバイスはFPD-Link IIIインターフェイスを搭載しており、1本の同軸ケーブルまたは差動ペア・ケーブルで、高速順方向チャネルおよび双方向制御用

チャネルのデータを転送します。DS90UB913A-Q1デバイスには高速の順方向チャネルと、双方向制御チャネル・

データ・パスの両方の差動信号処理回路が組み込まれて

います。シリアライザ/デシリアライザのペアは、電子制御ユニット(ECU)内のイメージャとビデオ・プロセッサ間の接続を目的としています。このデバイスは、ピクセル深度12ビットまでのビデオ・データと、2つの同期信号とともに、双方向の制御チャネル・バスを駆動する場合に理想的です。

製製品品情情報報(1)型型番番パパッッケケーージジ本本体体ササイイズズ（（公公称称））

DS90UB913A-Q1 WQFN（32） 5.00mm×5.00mm

(1) 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

概概略略回回路路図図

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2

DS90UB913A-Q1JAJSG55F –MAY 2013–REVISED JANUARY 2020 www.tij.co.jp

Copyright © 2013–2020, Texas Instruments Incorporated

目目次次1 特特長長.......................................................................... 12 アアププリリケケーーシショョンン ......................................................... 13 概概要要.......................................................................... 14 改改訂訂履履歴歴................................................................... 25 概概要要（（続続きき））................................................................ 46 Device Comparison Table ..................................... 57 Pin Configuration and Functions ......................... 58 Specifications......................................................... 7

8.1 Absolute Maximum Ratings ...................................... 78.2 ESD Ratings.............................................................. 78.3 Recommended Operating Conditions....................... 78.4 Thermal Information .................................................. 88.5 Electrical Characteristics........................................... 88.6 Recommended Serializer Timing For PCLK .......... 118.7 AC Timing Specifications (SCL, SDA) - I2C-

Compatible ............................................................... 128.8 Bidirectional Control Bus DC Timing Specifications

(SCL, SDA) - I2C-Compatible ................................. 128.9 Timing Diagrams..................................................... 138.10 Serializer Switching Characteristics...................... 158.11 Typical Characteristics .......................................... 16

9 Detailed Description ............................................ 17

9.1 Overview ................................................................. 179.2 Functional Block Diagram ....................................... 179.3 Feature Description................................................. 189.4 Device Functional Modes........................................ 219.5 Programming .......................................................... 269.6 Register Maps ......................................................... 30

10 Application and Implementation........................ 3710.1 Application Information.......................................... 3710.2 Typical Applications .............................................. 39

11 Power Supply Recommendations ..................... 4312 Layout................................................................... 44

12.1 Layout Guidelines ................................................. 4412.2 Layout Example .................................................... 45

13 デデババイイススおおよよびびドドキキュュメメンントトののササポポーートト ....................... 4713.1 ドキュメントのサポート .............................................. 4713.2 ドキュメントの更新通知を受け取る方法..................... 4713.3 サポート・リソース..................................................... 4713.4 商標 ....................................................................... 4713.5 静電気放電に関する注意事項 ................................ 4713.6 Glossary ................................................................ 47

14 メメカカニニカカルル、、パパッッケケーージジ、、おおよよびび注注文文情情報報 ................. 48

4 改改訂訂履履歴歴

Revision E (September 2018) かからら Revision F にに変変更更 Page

• Clarified GPO2 description by removing statement about leaving pin open if unused ......................................................... 6• Added register 0x27[5] to register map ............................................................................................................................... 35• Fixed missing register 0x29 typo ......................................................................................................................................... 36• Added maximum power up timing constraint between VDD_n and PDB ........................................................................... 37• Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint can not

be met .................................................................................................................................................................................. 38

Revision D (October 2016) かからら Revision E にに変変更更 Page

• Added recommendation to ensure GPO2 is low when PDB goes high ................................................................................ 6• Added Power Over Coax supply noise to the recommended operating conditions table ...................................................... 8• Clarified PCLK clock frequency range and added external clock input frequency range ...................................................... 8• Added strap pin input current specification for MODE and IDX pins .................................................................................... 9• Updated TJIT1 PCLK input jitter in the external oscillator mode ........................................................................................... 11• Added clarification on MODE pin description in PCLK from imager mode ......................................................................... 22• Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram ................................................... 22• Updated the MODE setting values to ratio ........................................................................................................................... 23• Updated pullup and pulldown resistor for IDX to R3 and R4 in the diagram......................................................................... 28• Updated IDX setting values to ratio ..................................................................................................................................... 28• Updated register "TYPE" column per legend ...................................................................................................................... 30• Added type and default value to the reserved register bits that were missing this information .......................................... 30• Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................................... 30• Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ............................................................... 32

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3

DS90UB913A-Q1www.tij.co.jp JAJSG55F –MAY 2013–REVISED JANUARY 2020


• Clarified description on PDB pin usage during power up .................................................................................................... 37• Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............................... 37• Added GPO2 to suggested power-up sequencing diagram ................................................................................................ 37• Added timing constraint for PDB to GPO2 delay ................................................................................................................ 38• Revised coax connection diagram to include pulldown resistor for GPO2 ......................................................................... 40• Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................................... 42

Revision C (April 2016) かからら Revision D にに変変更更 Page

• Added back channel line rate = 5.5 MHz as test condition; also added footnote for clarification between MHz andMbps distinction. ................................................................................................................................................................... 10

• Removed 'ns' unit from specifications referencing period in units of T. ............................................................................... 11• Updated test condition specs for jitter bandwidth regarding tJIT0, tJIT1, and tJIT2. .................................................................. 11• Added input external oscillator frequency range for pin/freq. .............................................................................................. 11• Added parameter for typical external oscillator frequency stability. ..................................................................................... 11• Added test conditions to tJIND, tJINR, and tJINT. ....................................................................................................................... 15• Added DOUT± as measured output pins for jitter parameters. ............................................................................................ 15• Added note (6) for "Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter

transfer from serializer input". .............................................................................................................................................. 15• Added jitter tolerance curve for typical system IJT configuration with DS90UB913A linked to DS90UB914A. .................. 16• Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. ............................ 21

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4

DS90UB913A-Q1JAJSG55F –MAY 2013–REVISED JANUARY 2020 www.ti.com


5 概概要要（（続続きき））TIの組み込みクロック・テクノロジにより、単一の差動ペア上で透過的な全二重通信が行え、非対称の双方向制御チャネル情報を伝送できます。この単一のシリアル・ストリームにより、パラレル・データ・パスとクロック・パスの間でスキューの問題が

排除されるため、PCB上の配線およびケーブルで広いデータ・バスを簡単に転送できます。これによって、データ・パスを狭くでき、PCBレイヤ、ケーブル幅、コネクタのサイズとピン数のすべてを削減できるため、大幅にシステムコストを低減できます。内部のDCバランスされたエンコード/デコードを使用して、ACカップリング相互接続に対応できます。

http://www.ti.com/product/ds90ub913a-q1?qgpn=ds90ub913a-q1http://www.ti.com

32

31

30

29

28

27

26

25

1 2 3 4 5 6 7 8

91

01

11

21

31

41

51

6

24 23 22 21 20 19 18 17

DS90UB913A-Q1

Serializer

VDDIO

DIN[8]

DIN[9]

DIN[10]

DIN[11]

DIN[7]

DIN[6]

DIN

[5]

DIN

[4]

DIN

[3]

DIN

[2]

DIN

[1]

DIN

[0]

VDDCML

VDDT

VDDPLL

PDB

DOUT-

DOUT+

HS

YN

C

VS

YN

C

PC

LK

SC

L

SD

A

ID[x

]

RE

S

MO

DE

GP

O[2

]/

CL

KO

UT

GPO[1]

GPO[0]

VDDDG

PO

[3]/

CL

KIN

DAP = GND

5

DS90UB913A-Q1www.ti.com JAJSG55F –MAY 2013–REVISED JANUARY 2020


6 Device Comparison Table

PART NUMBER FPD-III FUNCTION PACKAGE TRANSMISSION MEDIA PCLK FREQUENCYDS90UB913Q-Q1 Serializer WQFN RTV (32) STP 10 to 100 MHzDS90UB913A-Q1 Serializer WQFN RTV (32) Coax or STP 25 to 100 MHz

7 Pin Configuration and Functions

32-Pin WQFNPackage RTV

Top View

Pin Functions: DS90UB913A-Q1 SerializerPIN

I/O DESCRIPTIONNAME NO.LVCMOS PARALLEL INTERFACE

DIN[0:11]19,20,21,22,23,24,26,27,29,30,31,32

Inputs,LVCMOS

w/ pulldown

Parallel Data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] areinactive and should not be used. Any unused inputs (including DIN[10:11]) should be NoConnect. For 12-bit MODE (HF or LF), parallel inputs DIN[0:11] are active. Any unusedinputs should be No Connect.

HSYNC 1Input,

LVCMOSw/ pulldown

Horizontal SYNC Input. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: NoHS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bitmode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open ifunused.

VSYNC 2Input,

LVCMOSw/ pulldown

Vertical SYNC Input. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VSrestrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit High-Frequency mode: VS restricted to no more than one transition per 10 PCLK cycles. Leaveopen if unused.

PCLK 3Input,

LVCMOSw/ pulldown

Pixel Clock Input Pin. Strobe edge set by TRFB control register 0x03[0].


6



Pin Functions: DS90UB913A-Q1 Serializer (continued)PIN

I/O DESCRIPTIONNAME NO.

(1) See Power-Up Requirements and PDB Pin.

GENERAL PURPOSE OUTPUT (GPO)

GPO[1:0] 16,15 Output,LVCMOS

General-purpose output pins can be configured as outputs; used to control and respond tovarious commands. GPO[1:0] can be configured to be the outputs for input signals comingfrom GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the localregister on the Serializer. Leave open if unused.

GPO[2]/CLKOUT 17

Output,LVCMOS

GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pinon the Deserializer or can be configured to be the output of the local register on theSerializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1device is used in the External Oscillator mode. See Device Functional Modes section for adetailed description of External Oscillator Mode. It is recommended to pull GPO2 to GNDwith a minimum 40-kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW toHIGH.

GPO[3]/CLKIN 18

Input/Output,LVCMOS

GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin onthe Deserializer or can be configured to be the output of the local register setting on theSerializer. It can also be configured to be the input clock pin when the DS90UB913A-Q1Serializer is working with an external oscillator. See Device Functional Modes section for adetailed description of External Oscillator Mode. Leave open if unused.

BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE

SCL 4 Input/Output,Open DrainClock line for the bidirectional control bus communicationSCL requires an external pullup resistor to VDDIO.

SDA 5 Input/Output,Open DrainData line for the bidirectional control bus communicationSDA requires an external pullup resistor to VDDIO.

MODE 8 Input, analog

Device Mode SelectResistor (Rmode) to Ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the Serializer canbe used to select whether the system is running off the PCLK from the imager or an externaloscillator. See details in Table 2.

ID[x] 6 Input, analogDevice ID Address SelectThe ID[x] pin on the Serializer is used to assign the I2C device address. Resistor (RID) toGround and 10-kΩ pullup to 1.8 V rail. See Table 6.

CONTROL AND CONFIGURATION

PDB 9Input,

LVCMOSw/ pulldown

Power Down Mode Input PinPDB = H, Serializer is enabled and is ON.PDB = L, Serializer is in Power Down mode. When the Serializer is in Power Down, the PLLis shutdown, and IDD is minimized. Programmed control register data is NOT retained andreset to default values.

RES 7Input,

LVCMOSw/ pulldown

ReservedThis pin MUST be tied LOW.

FPD–Link III INTERFACE

DOUT+ 13 Input/Output,CMLNon-inverting differential output, bidirectional control channel input. The interconnect must beAC Coupled with a 0.1-µF capacitor.

DOUT- 12 Input/Output,CML

Inverting differential output, bidirectional control channel input. The interconnect must be ACCoupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a0.047-µF AC coupling capacitor should be placed in series with a 50Ω resistor beforeterminating to GND.

POWER AND GROUND (1)

VDDPLL 10 Power,Analog PLL Power, 1.8 V ±5%.

VDDT 11 Power,Analog Tx Analog Power, 1.8 V ±5%.

VDDCML 14 Power,Analog CML & Bidirectional Channel Driver Power, 1.8 V ±5%.

VDDD 28 Power,Digital Digital Power, 1.8 V ±5%.

VDDIO 25 Power,DigitalPower for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.


7



Pin Functions: DS90UB913A-Q1 Serializer (continued)PIN

I/O DESCRIPTIONNAME NO.

VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at thecenter of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8 Specifications

8.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply Voltage – VDD_n (VDDPLL, VDDT, VDDCML, VDDD) −0.3 2.5 VSupply Voltage – VDDIO −0.3 4.0 VLVCMOS Input Voltage −0.3 VDDIO + 0.3 VCML Driver I/O Voltage – (VDD_n) -0.3 VDD_n + 0.3 VJunction Temperature 150 °CStorage temperature range, Tstg −65 150 °C

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human body model (HBM), per AEC Q100-002 (1)

HBM ESD Classification Level 3B ±8000

V

Charged device model (CDM), per AECQ100-011CDM ESD Classification Level C6

Corner pins (1, 8, 9, 16, 17, 24,25, 32) ±1000Other pins

(IEC 61000-4-2)RD = 330 Ω, Cs = 150pF

Air Discharge(DOUT+, DOUT-, RIN+, RIN-)

±25000

Contact Discharge(DOUT+, DOUT-, RIN+, RIN-)

±7000

(ISO10605)RD = 330 Ω, Cs = 150/330 pFRD = 2 KΩ, Cs = 150/330 pF

Air Discharge(DOUT+, DOUT-, RIN+, RIN-)

±15000

Contact Discharge(DOUT+, DOUT-, RIN+, RIN-)

±8000

(1) Supply noise testing was done with minimum capacitors (as shown on Figure 36, Figure 32 on the PCB. A sinusoidal signal is ACcoupled to the VDD_n (1.8 V) supply with amplitude = 25 mVp-p measured at the device VDD_n pins. Bit error rate testing of input to theSer and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on theother hand shows no error when the noise frequency is less than 750 kHz.

8.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITSupply Voltage (VDD_n) 1.71 1.8 1.89 V

LVCMOS Supply VoltageVDDIO= 1.8 V 1.71 1.8 1.89

VVDDIO= 3.3 V 3 3.3 3.6VDDIO= 2.8 V 2.52 2.8 3.08

Supply Noise (1)VDD_n = 1.8 V 25

mVp-pVDDIO = 1.8 V 25VDDIO = 3.3 V 50


8



Recommended Operating Conditions (continued)over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Power-Over-Coax SupplyNoise

ƒ = 30 Hz - 1 KHz, trise > 100 µsMeasured differentially between DOUT+ and DOUT–(coax mode only)

10 mVp-p

ƒ = 1 KHz - 50 MHzMeasured differentially between DOUT+ and DOUT-(coax mode only)

10 mVp-p

Operating Free Air Temperature (TA) –40 25 105 °C

PCLK Clock Frequency10-bit mode 50 100 MHz12-bit HF mode 37.5 75 MHz12-bit LF mode 25 50 MHz

External Clock InputFrequency to GPO3

10-bit mode 25 50 MHz12-bit HF mode 25 50 MHz12-bit LF mode 25 50 MHz

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport (SPRA953).

8.4 Thermal Information

THERMAL METRIC (1)DS90UB913A-Q1

UNITRTV (WQFN)32 PINS

RθJA Junction-to-ambient thermal resistance 34.9 °C/WRθJC(top) Junction-to-case (top) thermal resistance 8.8 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 °C/WRθJB Junction-to-board thermal resistance 23.4 °C/WψJT Junction-to-top characterization parameter 0.3 °C/WψJB Junction-to-board characterization parameter 8.8 °C/W

(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwisemodified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are notverified.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to groundexcept VOD and ΔVOD which are differential voltages.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions atthe time of product characterization and are not verified.

8.5 Electrical Characteristics (1) (2) (3)Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITLVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)

VIHHigh Level InputVoltage VIN = 3 V to 3.6 V 2 VIN V

VILLow Level InputVoltage VIN = 3 V to 3.6 V GND 0.8 V

IIN Input Current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V –20 ±1 20 µA

VOHHigh Level OutputVoltage VDDIO = 3 V to 3.6 V, IOH = −4 mA 2.4 VDDIO V

VOLLow Level OutputVoltage VDDIO = 3 V to 3.6 V, IOL = 4 mA GND 0.4 V

IOSOutput Short CircuitCurrent VOUT = 0 V

SerializerGPO Outputs –15 mA

IOZTRI-STATE OutputCurrent

PDB = 0 V,VOUT = 0 V or VDDIO

SerializerGPO Outputs –20 20 µA

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9



Electrical Characteristics(1)(2)(3) (continued)Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCGPO Pin Capacitance GPO [3:0] 1.5 pFLVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)

VIHHigh Level InputVoltage VIN = 1.71 V to 1.89 V 0.65 VIN VIN

VVIL

Low Level InputVoltage VIN = 1.71 V to 1.89 V GND 0.35 VIN

IIN Input Current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V –20 ±1 20 µA

VOHHigh Level OutputVoltage VDDIO = 1.71 V to 1.89 V, IOH = −4 mA VDDIO - 0.45 VDDIO V

VOLLow Level OutputVoltage VDDIO = 1.71 V to 1.89 V IOL = 4 mA GND 0.45 V





SerializerGPO Outputs -20 20 µA

CGPO Pin Capacitance GPO [3:0] 1.5 pFIIN-STRAP Strap pin input current VIN = 0 V to VDD_n -1 1 µALVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)

VIHHigh Level InputVoltage VIN = 2.52 V to 3.08 V 0.7 VIN VIN

VVIL

Low Level InputVoltage VIN = 2.52 V to 3.08 V GND 0.3 VIN

IIN Input Current VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V –20 ±1 20 µA

VOHHigh Level OutputVoltage VDDIO = 2.52 V to 3.08 V, IOH = −4 mA VDDIO - 0.4 VDDIO V

VOLLow Level OutputVoltage VDDIO =2.52 V to 3.08V IOL = 4 mA GND 0.4 V





SerializerGPO Outputs –20 20 µA

CGPO Pin Capacitance GPO [3:0] 1.5 pFCML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)

VODDifferential OutputVoltage RL = 100 Ω (Figure 6), Back Channel Disabled 640 824

mVVOUT

Single-Ended OutputVoltage RL = 50 Ω (Figure 6), Back Channel Disabled 320 412

ΔVODDifferential OutputVoltage Unbalance RL = 100 Ω 1 50 mV

VOS Output Offset Voltage RL = 100 Ω (Figure 6)VDD_n -

VOD/2V

ΔVOSOffset VoltageUnbalance RL = 100 Ω 1 50 mV

IOSOutput Short CircuitCurrent DOUT+ = 0 V or DOUT– = 0 V –26 mA

RT

Differential InternalTerminationResistance

Differential across DOUT+ and DOUT– 80 100 120

ΩSingle-endedTerminationResistance

DOUT+ or DOUT– 40 50 60


10



Electrical Characteristics(1)(2)(3) (continued)Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(4) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream.The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.

VID-BCBack ChannelDifferential InputVoltage Back Channel Frequency = 5.5 MHz (4)

260 mV

VIN-BCBack Channel Single-Ended Input Voltage 130 mV

SERIALIZER SUPPLY CURRENT

IDDTSerializer (Tx)VDD_n Supply Current(includes load current)

RL = 100 ΩWORST CASE pattern(Figure 2)

VDD_n = 1.89 VVDDIO = 3.6 Vf = 100 MHz, 10-bitmodeDefault Registers

61 80 mA

VDD_n = 1.89 VVDDIO = 3.6 Vf = 75 MHz, 12-bithigh frequency modeDefault Registers

61 80

mAVDD_n = 1.89 VVDDIO = 3.6 Vf = 50 MHz, 12-bitlow frequency modeDefault Registers

61 80

IDDTSerializer (Tx)VDD_n Supply Current(includes load current)

RL = 100 ΩRANDOM PRBS-7pattern

VDD_n = 1.89 VVDDIO = 3.6 Vf = 100 MHz, 10-bitmodeDefault Registers

65

mA

VDD_n = 1.89 VVDDIO = 3.6 Vf = 75 MHz, 12-bithigh frequency modeDefault Registers

64

VDD_n = 1.89 VVDDIO = 3.6 Vf = 50 MHz, 12-bitlow frequency modeDefault Registers

63

IDDIOTSerializer (Tx)VDDIO Supply Current(includes load current)

RL = 100 ΩWORST CASE pattern(Figure 2)

VDDIO = 1.89 Vf = 75 MHz, 12-bithigh frequency modeDefault Registers

1.5 3

mAVDDIO = 3.6 Vf = 75 MHz, 12-bithigh frequencymode DefaultRegisters

5 8

IDDTZSerializer (Tx) SupplyCurrent Power Down

PDB = 0V; All otherLVCMOS Inputs = 0 V

VDDIO=1.89 VDefault Registers 300 1000 µA

VDDIO = 3.6 VDefault Registers 300 1000 µA

IDDIOTZSerializer (Tx) VDDIOSupply Current PowerDown

PDB = 0V; All otherLVCMOS Inputs = 0 V




11



(1) Recommended Input Timing Requirements are input specifications and not tested in production.(2) T is the period of the PCLK.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not verified.(4) ƒPCLK denotes input PCLK frequency to the device.(5) ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).

8.6 Recommended Serializer Timing For PCLK (1) (2)Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN / FREQ MIN NOM MAX UNIT

tTCP Transmit Clock Period

10-bit mode50 MHz – 100 MHz 10 T 20 ns

12-bit high frequency mode37.5 MHz - 75MHz 13.33 T 26.67 ns

12-bit low frequency mode25 MHz - 50MHz 20 T 40 ns

tTCIHTransmit ClockInput High Time 0.4T 0.5T 0.6T

tTCILTransmit ClockInput Low Time 0.4T 0.5T 0.6T

tCLKTPCLK Input Transition Time(Figure 7)

10-bit mode50 MHz – 100 MHz 0.05T 0.25T 0.3T

12-bit high frequency mode37.5 MHz - 75MHz 0.05T 0.25T 0.3T

12-bit low frequency mode25 MHz - 50MHz 0.05T 0.25T 0.3T

tJIT0PCLK Input Jitter(PCLK from imagermode) (3)

LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10

ƒPCLK = 25 –100 MHz (4) 0.3 UI

tJIT1PCLK Input Jitter(External Oscillatormode) (3)

LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10

ƒPCLK = 25 –100 MHz (4) 1T

tJIT2 External Oscillator Jitter (3)LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10

ƒOSC = 25 –50 MHz (5) 0.3 UI

ΔOSCExternal OscillatorFrequency Stability

ƒOSC = 25 –50 MHz (5) ±50 ppm


12



8.7 AC Timing Specifications (SCL, SDA) - I2C-CompatibleOver recommended supply and temperature ranges unless otherwise specified. (Figure 1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNITRECOMMENDED INPUT TIMING REQUIREMENTS

fSCL SCL Clock FrequencyStandard Mode 100 kHzFast Mode 400 kHz

tLOW SCL Low PeriodStandard Mode 4.7 µsFast Mode 1.3 µs

tHIGH SCL High PeriodStandard Mode 4.0 µsFast Mode 0.6 µs

tHD:STAHold time for a start or a repeated startcondition

Standard Mode 4.0 µsFast Mode 0.6 µs

tSU:STASet Up time for a start or a repeatedstart condition

Standard Mode 4.7 µsFast Mode 0.6 µs

tHD:DAT Data Hold TimeStandard Mode 0 3.45 µsFast Mode 0 900 ns

tSU:DAT Data Set Up TimeStandard Mode 250 nsFast Mode 100 ns

tSU:STO Set Up Time for STOP ConditionStandard Mode 4.0 µsFast Mode 0.6 µs

tBUF Bus Free time between Stop and StartStandard Mode 4.7 µsFast Mode 1.3 µs

tr SCL & SDA Rise TimeStandard Mode 1000 nsFast Mode 300 ns

tf SCL & SDA Fall TimeStandard Mode 300 nsFast Mode 300 ns

(1) Specification is verified by design.(2) FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the

Minimum IOL pullup current is targeted to lower value than the minimum IOL in the I2C specification.

8.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible (1)Over recommended supply and temperature ranges unless otherwise specified

PARAMETER TEST CONDITIONS MIN NOM MAX UNITRECOMMENDED INPUT TIMING REQUIREMENTSVIH Input High Level SDA and SCL 0.7*VDDIO VDDIO VVIL Input Low Level SDA and SCL GND 0.3*VDDIO VVHY Input Hysteresis >50 mV

VOL Output Low Level (2)SDA, VDDIO = 1.8 V, IOL= 0.9 mA 0 0.36 VSDA, VDDIO = 3.3 V, IOL= 1.6 mA 0 0.4

IIN Input Current SDA or SCL, VIN= VDDIO OR GND −10 10 µAtR SDA Rise Time-READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF

(Figure 1)430 ns

tF SDA Fall Time-READ 20 nsCIN SDA or SCL


PA

RA

LL

EL

-TO

-SE

RIA

L

DOUT+

DOUT-

10/12,

HS,VS

DIN RL

PCLK


ZDiff = 100 : 100 :

DOUT+

DOUT-

100 nF

100 nF

SCOPE

BW 8 4.0 GHz

50 :

50 :

PCLK

(RFB = H)

DIN/ROUT

Signal PatternDevice Pin Name

T

80%

20%

80%

20%Vdiff = 0V

tLHT tHLT

Vdiff

Vdiff = (DOUT+) - (DOUT-)

SCL

SDA

tHD;STA

tLOW

tr

tHD;DAT

tHIGH

tf

tSU;DAT

tSU;STA tSU;STO

tf

START REPEATED

START

STOP

tHD;STA

START

tr

tBUF

13



8.9 Timing Diagrams

Figure 1. Bi-directional Control Bus Timing

Figure 2. “Worst Case” Test Pattern for PowerConsumption

Figure 3. Serializer CML Output Load andTransition Times

Figure 4. Serializer CML Output Load and Transition Times

Figure 5. Serializer VOD Setup


||

SYMBOL N

||

SYMBOL N-1

||

SYMBOL N-2

||

SYMBOL N-3SYMBOL N-4

||

DOUT+-

|PCLK

tSD

DIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3

||

|||

||

||

||

VDDIO/2

0V

VDDIO/2

PCLK

DOUT± Output Active

tPLD

PDB

TRI-STATE TRI-STATE

SetupVDDIO/2 Hold

tDIHtDIS

PCLK

DINn

tTCP

0V

VDDIO/2

VDDIO/2 VDDIO/2VDDIO/2

VDDIO

80%

20%

80%

20%

tCLKT tCLKT

PCLK

VDD

0V

0V

VOUT

VOUT

Single-Ended

Differential

VOS

(DOUT+) - (DOUT-)

|

VOD

DOUT+ or DOUT-

14



Timing Diagrams (continued)

Figure 6. Serializer VOD Diagram

Figure 7. Serializer Input Clock Transition Times Figure 8. Serializer Setup/Hold Times

Figure 9. Serializer PLL Lock Time

Figure 10. Serializer Delay


15



(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.(2) Specification is verified by design.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not verified.(4) Specification is verified by characterization and is not tested in production.(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 x 28 )12-bit HF mode: 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 )12-bit LF mode: 1 UI = 1 / ( PCLK_Freq. x 28 )

(6) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.

8.10 Serializer Switching CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

tLHTCML Low-to-HighTransition Time RL = 100 Ω (Figure 3) 150 330 ps

tHLTCML High-to-LowTransition Time RL = 100 Ω (Figure 3) 150 330 ps

tDISData InputSetup to PCLK

Serializer Data Inputs (Figure 8)2 ns

tDIHData InputHold from PCLK 2 ns

tPLDSerializer PLLLock Time (1) (2) RL = 100 Ω (Figure 9) 1 2 ms

tSD Serializer Delay (2)RT = 100 Ω, 10–bit modeRegister 0x03h b[0] (TRFB = 1) (Figure 10) 32.5T 38T 44T

RT = 100 Ω, 12–bit modeRegister 0x03h b[0] (TRFB = 1) (Figure 10) 11.75T 13T 15T

tJINDSerializer OutputDeterministic Jitter(3) (4) (5)

PRBS-7 test pattern, CDR PLL LoopBW = ƒ/15, BER = 1E-10 DOUT± 0.17 0.26 UI

tJINRSerializer OutputRandom Jitter(3) (4) (5)

PRBS-7 test pattern, CDR PLL LoopBW = ƒ/15, BER = 1E-10 DOUT± 0.016 UI

tJINTPeak-to-PeakSerializer OutputTotal Jitter (3) (5) (6)

PRBS-7 test pattern, CDR PLL LoopBW = ƒ/15, BER = 1E-10 DOUT± 0.4 0.52 UI

λSTXBW

Serializer JitterTransfer Function-3 dB Bandwidth

10–bit modePCLK = 100 MHz. Default Registers 2.20

MHz12–bit high frequency modePCLK = 75 MHz. Default Registers 2.20

12–bit low frequency modePCLK = 50 MHz. Default Registers 2.20

δSTXSerializer JitterTransfer Function(Peaking)

10–bit modePCLK = 100 MHz. Default Registers 1.06

dB12–bit high frequency modePCLK = 75 MHz. Default Registers 1.09

12–bit low frequency modePCLK = 50 MHz. Default Registers 1.16

δSTXf

Serializer JitterTransfer Function(PeakingFrequency)

10–bit modePCLK = 100 MHz. Default Registers 400

kHz12–bit high frequency modePCLK = 75 MHz. Default Registers 500

12–bit low frequency modePCLK = 50 MHz. Default Registers 600


Jitter Frequency (MHz)

Jitte

rA

mplit

ud

e(U

I)

0.1 1 100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

- 18

- 16

-14

-12

-10

- 8

- 6

- 4

- 2

0

2

4

MODULATION FREQUENCY ( Hz)

1.0E+04 1.0E+071.0E+061.0E+05

JIT

TE

RT

RA

NS

FE

R (

dB

)

16



8.11 Typical Characteristics

Figure 11. Typical Serializer Jitter Transfer Function Figure 12. Typical System Input Jitter Tolerance Curve -DS90UB913A Linked to DS90UB914A



DIN

10 or

12

DS90UB913AQ - SERIALIZER

Clock Gen

Timing and

Control

DOUT-

DOUT+

Inp

ut L

atc

h

FIF

O

De

co

de

r

En

co

de

r

Se

ria

lize

r

PLL

I2C

Co

ntr

olle

r

En

co

de

r

RT RT

PCLK

SDA

SCL

GPO[3:0]4

PDB

ID[x]

HSYNC

VSYNC

RIN0-

DS90UB914AQ - DESERIALIZER

RIN0+

Timing and

Control

FIF

O

En

co

de

r I2

C

Co

ntr

olle

r

De

co

de

rD

ese

ria

lize

r

De

co

de

r

Ou

tpu

t L

atc

h

Clock

GenCDR

RT RT

PDB

BISTEN

OEN

RIN1-

RIN1+

ROUT

HSYNC

VSYNC

GPIO[3:0]

PCLKLOCK

PASS

IDx[0]

SDA

SCL

2:1

4

10 or

12

SEL

MODE

MODE IDx[1]

Ad

ap

tive

Eq.

17



9 Detailed Description

9.1 OverviewThe DS90UB913A-Q1 is optimized to interface with the DS90UB914A-Q1 using a 50-Ω coax interface. TheDS90UB913A-Q1 will also work with the DS90UB914A-Q1 using an STP interface.

The DS90UB913A/914A FPD- Link III chipsets are intended to link mega-pixel camera imagers and videoprocessors in ECUs. The Serializer/Deserializer chipset can operate from 25 MHz to 100 MHz pixel clockfrequency. The DS90UB913A-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with abidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit streamcontains an embedded clock and DC-balanced information which enhances signal quality to support ACcoupling. The DS90UB914A-Q1 device receives the single serial data stream and converts it back into a 10/12-bit wide parallel data bus together with the control channel data bus. The DS90UB913A/914A chipsets canaccept up to:• 12-bits of DATA + 2 bits SYNC for an input PCLK range of 25 MHz to 50 MHz in the 12-bit low frequency

mode. Note: No HS/VS restrictions (raw).• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 75 MHz in the 12-bit high frequency

mode. Note: No HS/VS restrictions (raw).• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:

HS/VS restricted to no more than one transition per 10 PCLK cycles.

The DS90UB913A/914A chipset offer customers the choice to work with different clocking schemes. TheDS90UB913A/914A chipsets can use an external oscillator as the reference clock source for the PLL (seesection DS90UB913A/914A Operation with External Oscillator as Reference Clock) or PCLK from the imager asprimary reference clock to the PLL (see section DS90UB913A/914A Operation with Pixel Clock from Imager asReference Clock).

9.2 Functional Block Diagram


18



9.3 Feature Description

9.3.1 Serial Frame FormatThe High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C andparity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,balanced and scrambled. The 28-bit frame structure changes in the 12-bit low frequency mode, 12-bit highfrequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional controlchannel data is transferred over the single serial link along with the high-speed forward data. This architectureprovides a full duplex low speed forward and backward path across the serial link together with a high speedforward channel without the dependence on the video blanking phase.

9.3.2 Line Rate Calculations for the DS90UB913A/914AThe DS90UB913A-Q1 device divides the clock internally by divide-by-1 in the 12-bit low frequency mode, bydivide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, theDS90UB914A-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thusthe maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used tocalculate the maximum line rate in the different modes:• For the 12-bit low frequency mode, Line rate = fPCLK*28; for example, fPCLK = 50 MHz, line rate = 50*28 = 1.4

Gbps• For the 12-bit high frequency mode, Line rate = fPCLK*(2/3)*28; for example, fPCLK = 75 MHz, line rate =

(75)*(2/3)*28 = 1.4 Gbps• For the 10-bit mode, Line rate = fPCLK/2*28; for example, fPCLK = 100 MHz, line rate = (100/2)*28 = 1.4 Gbps

9.3.3 Error DetectionThe chipset provides error detection operations for validating data integrity in long distance transmission andreception. The data error detection function offers users flexibility and usability of performing bit-by-bit datatransmission error checking. The error detection operating modes support data validation of the following signals:• Bidirectional control channel data across the serial link• Parallel video/sync data across the serial link

The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the backchannel for error detection purposes. The DS90UB913A/914A chipset checks the forward and back channelserial links for errors and stores the number of detected errors in two 8-bit registers in the Serializer and theDeserializer respectively.

To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the DS90UB914A. If there isa loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error onthe forward channel, the PASS pin will go low.To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.


DES A

GPIO[n] Input

DES B

GPIO[n] Input

SER A

GPIO[n] Output

SER B

GPIO[n] Output

t1

||


ECU

Module

Deserializer ASerializer A

CMOS

Image

Sensor

I2C I2C

PC

Deserializer BSerializer B

CMOS

Image

Sensor

I2C I2C

Camera B

Camera A

DATAPCLK

DATAPCLK

FSYNC

FSYNC

GP

O

GP

IO FSYNCG

PO

GP

IO FSYNC

DATAPCLK

DATAPCLK

FS

OF

SO

FS

INF

SIN

19



Feature Description (continued)9.3.4 Synchronizing Multiple CamerasFor applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the GeneralPurpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. Tosynchronize the cameras properly, the system controller needs to provide a field sync output (such as a verticalor frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronizesignal corresponds to the start and end of a frame and the start and end of a field. Note this form ofsynchronization timing relationship has a non-deterministic latency. After the control data is reconstructed fromthe bidirectional control channel, there will be a time variation of the GPIO signals arriving at the different targetdevices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted acrossmultiple links is 25 µs.

NOTEThe user must verify that the timing variations between the different links are within theirsystem and timing specifications.

See Figure 13 for an example of this function.

The maximum time (t1) between the rising edge of GPIO (that is, sync signal) to the time the signal arrives atCamera A and Camera B is 25 µs.

Figure 13. Synchronizing Multiple Cameras

Figure 14. GPIO Delta Latency


DIN/

ROUT

PCLK

TRFB/RRFB: 0 TRFB/RRFB: 1

20



Feature Description (continued)9.3.5 General Purpose I/O (GPIO) DescriptionsThere are 4 GPOs on the Serializer and 4 GPIOs on the Deserializer when the DS90UB913A/914A chipsets arerun off the pixel clock from the imager as the reference clock source. The GPOs on the Serializer can beconfigured as outputs for the input signals that are fed into the Deserializer GPIOs. In addition, the GPOs on theSerializer can behave as outputs of the local register on the Serializer. The GPIOs on the Deserializer can beconfigured to be the input signals feeding the GPOs (configured as outputs) on the Serializer. In addition theGPIOs on the Deserializer can be configured to behave as outputs of the local register on the Deserializer. TheDS90UB913A Serializer GPOs cannot be configured as inputs for remote communication with Deserializer. If theDS90UB913A/914A chipsets are run off the external oscillator source as the reference clock, then GPO3 on theSerializer is automatically configured to be the input for the external clock and GPO2 is configured to be theoutput of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 andGPIO3 on the Deserializer can only behave as outputs of the local register on the Deserializer. The GPIOmaximum switching rate is up to 66 kHz when configured for communication between Deserializer GPIO toSerializer GPO.

9.3.6 LVCMOS VDDIO Option1.8 V/2.8 V/3.3 V Serializer inputs are user configurable to provide compatibility with 1.8 V, 2.8 V and 3.3 Vsystem interfaces.

9.3.7 Pixel Clock Edge Select (TRFB / RRFB)The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edgethat the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB registeris 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that thedata is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,data is strobed on the falling edge of the PCLK.

Figure 15. Programmable PCLK Strobe Select

9.3.8 Power DownThe SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER will disable thelink to save power. If PDB = HIGH, the SER will operate at its internal default oscillator frequency when the inputPCLK stops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to theDES. When PDB = LOW, the high-speed driver outputs are static HIGH. Please refer to Power-Up Requirementsand PDB Pin for power-up requirements.



FPD Link III-

High Speed

Bi-Directional

Control Channel

Image

Sensor

ECU Module

DIN[11:0] or DIN[9:0]HSYNC, VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0] or

ROUT[9:0] HSYNC, VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DeserializerSerializer

GPO[1:0]

GPO[1:0]2

GPO[3:0]

4GPIO[3:0]

Camera Data

External

Oscillator

PLL

÷2

GPO3

GPO2

Reference Clock (Ext. OSC/2)

21



9.4 Device Functional Modes

9.4.1 DS90UB913A/914A Operation with External Oscillator as Reference ClockIn some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance ofthe DS90UB913A/914A chipsets. In this case, the DS90UB913A-Q1 device should be operated by using anexternal clock source as the reference clock for the DS90UB913A/914A chipsets. This is the recommendedoperating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913A-Q1Serializer and this divided clock output is used as the reference clock for the imager. The output data and pixelclock from the imager are then fed into the DS90UB913A-Q1 device. Figure 16 shows the operation of theDS90UB13A/914A chipsets while using an external automotive grade oscillator.

Figure 16. DS90UB913A-Q1/914A-Q1 Operation in the External Oscillator Mode

When the DS90UB913A-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB913A-Q1 is the input pin for the external oscillator. In applications where the DS90UB913A-Q1 device is operated froman external oscillator, the divide-by-2 circuit in the DS90UB913A-Q1 device feeds back the divided clock outputto the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the12–bit high frequency mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided bythe external oscillator frequency must be 2. In the 12-bit high frequency mode, the pixel clock frequencydivided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is48 MHz in the 10–bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillatorfrequency, that is, 96 MHz. If the external oscillator frequency is 48MHz in the 12-bit high frequency mode, thepixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz.

When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB913A will switch from internal oscillator modeto an external PCLK. Upon removal of PCLK input, the device will switch back into internal oscillator mode. Inexternal oscillator mode, GPO2 and GPO3 on the Serializer cannot act as the output of the input signal comingfrom GPIO2 or GPIO3 on the Deserializer.

Table 1. Device Functional Mode w/ Example XCLKIN = 48 MHz

MODE GPIO3 XCLKIN GPIO2 XCLKOUT =XCLKIN / 2 RatioInput PCLK Frequency =

XLCKIN * Ratio10-bit 48 MHz 24 MHz 2 96 MHz

12-bit High Frequency (HF) 48 MHz 24 MHz 1.5 72 MHz12-bit Low Frequency (LF) 48 MHz 24 MHz 1 48 MHz



Serializer

R1

R2

MODE

1.8 V

VMODE


FPD-Link III

Bi-Directional

Back Channel

Image Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

FV,LV

SDA

SCL

DOUT- RIN0-

DOUT+ RIN0+

Camera Unit

10 or 12

YUV

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

or

ROUT[9:0] FV, LV

SDA

SCL

PCLK

10 or 12

YUV

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DeserializerSerializer

GPOGPO[3:0]

4

GPIO

4GPIO[3:0]

Camera Data

Ext. Oscillator

PLL RIN1-

RIN1+

22



9.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference ClockThe DS90UB913A/914A chipsets can be operated by using the pixel clock from the imager as the referenceclock. Figure 17 shows the operation of the DS90UB913A/914A chipsets using the pixel clock from the imager. Ifthe DS90UB913A-Q1 device is operated using the pixel clock from the imager as the reference clock, then theimager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK fromimager mode).

Figure 17. DS90UB913A-Q1/914A-Q1 Operation in PCLK mode

9.4.3 MODE Pin on SerializerThe MODE pin on the Serializer can be configured to select if the DS90UB913A-Q1 device is to be operatedfrom the external oscillator or the PCLK from the imager. The pin must be pulled to VDD_n(1.8 V, not VDDIO) with aresistor R1 and a pulldown resistor R2 for external oscillator mode to create the ratio shown in Figure 18. If thedevice is to be operated from PCLK from imager mode, MODE pin can be pulled up to VDD_n (1.8V) with a 10-kΩresistor directly or use the ratio shown in Figure 18 and Table 2. The recommended maximum resistor toleranceis 1%.

Figure 18. MODE Pin Configuration on DS90UB913A-Q1


23



Table 2. DS90UB913A-Q1 Serializer MODE Setting

MODE SELECT MINIMUM RATIO(VMODE/V(VDD_n))MAXIMUM RATIO(VMODE/V(VDD_n))

SUGGESTED R1RESISTOR VALUE (kΩ)

SUGGESTED R2 RESISTORVALUE (kΩ)

PCLK from Imagermode 0.750 1.000 10 100

External Oscillatormode 0.292 0.339 10 4.7

9.4.4 Internal OscillatorWhen a PCLK is not applied to the DS90UB913A, the serializer will establish the FPD-III link using an internaloscillator. During normal operation (not BIST) the frequency of the internal oscillator can be adjusted fromDS90UB913A register 0x14[2:1] according to Table 3. In BIST mode, the internal oscillator frequency should onlybe adjusted from the DS90UB914A. The BIST frequency can be set by either pin strapping (Table 4) or register(Table 5). In BIST DS90UB913A register 0x14[2:1] is automatically loaded from the DS90UB914A through the bi-directional control channel.

Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal OperationDS90UB913A-Q1

Reg 0x14 [2:1]10–BITMODE

12–BITHIGH-FREQUENCY MODE

12–BITLOW-FREQUENCY MODE

00 50 MHz 37.5 MHz 25 MHz01 100 MHz 75 MHz 50 MHz10 50 MHz 37.5 MHz 25 MHz11 Reserved Reserved Reserved

9.4.5 Built In Self TestAn optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link and low-speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also forsystem diagnostics.


24



9.4.6 BIST Configuration and StatusThe chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BISTconfiguration is controlled through pins. BIST can be configured via registers using BIST Control register (0x24).Pin-based configuration is defined as follows:• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs. various frequencies of internal

OSC)

Table 4. BIST Pin ConfigurationDESERIALIZER GPIO[0:1] OSCILLATOR SOURCE BIST FREQUENCY

00 External PCLK PCLK or External Oscillator01 Internal ~50 MHz10 Internal ~25 MHz

Table 5. BIST Register ConfigurationDS90UB914A-Q1

Reg 0x24 [2:1]10–BITMODE

12–BITHIGH-FREQUENCY MODE

12–BITLOW-FREQUENCY MODE

00 PCLK PCLK PCLK01 100 MHz 75 MHz 50 MHz10 50 MHz 37.5 MHz 25 MHz11 Reserved Reserved Reserved

BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registerscan be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 4 for pinsettings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASSpin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS will toggle twice to allowcounting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BISTrun only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BISTstatus register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST inexternal oscillator mode, both the external oscillator and PCLK need to be present. For all practical purposes, theBIST status can be monitored from the BIST Error Count register 0x25 on the DS90UB914A Deserializer.

9.4.7 Sample BIST Sequence

Step 1. For the DS90UB913A/914A FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin ofDS90UB914A-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializer GPIO0and GPIO1 pins as shown in Table 4.

Step 2. The DS90UB913A-Q1 Serializer BIST pattern is enabled through the back channel. The BIST pattern issent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode andthe deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking FPD-Link IIIserial stream. If an error in the payload is detected, the PASS pin will switch low for one half of the clock period.During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3. To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking thedata. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST ErrorCount register, 0x25 on the Deserializer.

Step 4. The link returns to normal operation after the deserializer BISTEN pin is low. Figure 20 shows thewaveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multipleerrors. In most cases, it is difficult to generate errors due to the robustness of the link (differential datatransmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,or by reducing signal condition enhancements (Rx equalization).


X XX

PCLK

(RFB = L)

BISTEN

(DES)

PASS

DATA

(internal)

PASS

BIST Duration

Prior Result

BIST

Result

Held

PASS

FAIL

X = bit error(s)

ROUT[0:11],

HS, VS

DATA

(internal)

Ca

se

1 -

Pa

ss

Ca

se

2 -

Fa

il

Prior Result

Normal BIST Test Normal

DE

S O

utp

utsLOCK

Normal

BIST

start

BIST

stop

BIST

Wait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal

Mode - check PASS

Step 4: DES/SER in Normal

25



Figure 19. AT-Speed BIST System Flow Diagram

Figure 20. BIST Timing Diagram


SCL

SDA

START STOP

1 2 6 7 8 9 1 2 8 9

MSB

7-bit Slave Address

R/W

Direction

BitAcknowledge

from the Device

MSB

Data Byte

*Acknowledge

or Not-ACK

ACK N/ACK

Repeated for the Lower Data Byte

and Additional Data Transfers

LSB LSB

Bus Activity:

Master

SDA Line

Bus Activity:

Slave

Sta

rt

Slave

Address

A

C

K

S

Address

A

C

K

S

Sta

rt

Slave

Address

A

C

K

N

A

C

K

P

Sto

p

Data

0 1

Register

7-bit Address 7-bit Address

A

C

K

A

C

K

A

C

K

S P

Sto

p

Bus Activity:

Slave

SDA Line

Bus Activity:

MasterSlave

Address Address Data

Sta

rt

0

Register

7-bit Address

26



9.5 Programming

9.5.1 Programmable ControllerAn integrated I2C slave controller is embedded in the DS90UB913A-Q1 Serializer. It must be used to configurethe extra features embedded within the programmable registers or it can be used to control the set ofprogrammable GPIOs.

9.5.2 Description of Bidirectional Control Bus and I2C ModesThe I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an externalremote device (such as image sensor) through the bidirectional control channel. Register programmingtransactions to/from the DS90UB913A-Q1/914A-Q1 chipset are employed through the clock (SCL) and data(SDA) lines. These two signals have open drain I/Os and both lines must be pulled-up to VDDIO by an externalresistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high whenthey are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted byreleasing the output and allowing it to be pulled-up externally. The appropriate pullup resistor values will dependupon the total bus capacitance and operating speed. The DS90UB913A I2C bus data rate supports up to 400kbps according to I2C fast mode specifications.

For further description of general I2C communication, please refer to application note Understanding the I2C Bus(SLVA704). For more information on choosing appropriate pullup resistor values, please refer to application noteI2C Bus Pullup Resistor Calculation (SLVA689).

Figure 21. Write Byte

Figure 22. Read Byte

Figure 23. Basic Operation

http://www.ti.com/product/ds90ub913a-q1?qgpn=ds90ub913a-q1http://www.ti.comhttp://www.ti.com/lit/pdf/SLVA704http://www.ti.com/lit/pdf/SLVA689


ECUModule

DS90UB914AQDS90UB913AQ

DIN[11:0],HS,VSPCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],HS,VS,PCLK

I2C

SDASCL

SDASCL

PC

DES B: I2C_SLAVELocal

I2C_PASS_THRU Disabled


DIN[11:0]

,HS,VSPCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],HS,VS,

PCLK

I2C

SDASCL

SDASCL

Camera B

Slave ID: (0xA0)

SER A: Remote I2C _MASTER Proxy

DES A: I2C_SLAVE Local

I2C_PASS_THRU Enabled

Camera ASlave ID: (0xA0)

MasterSER B:

Remote I2C_MASTER Proxy

SDA

SCL

S P

START condition, or

START repeat condition

STOP condition

27



Programming (continued)

Figure 24. Start and Stop Conditions

9.5.3 I2C Pass-ThroughI2C pass-through provides a way to access remote devices at the other end of the FPD-Link III interface. Thisoption is used to determine if an I2C instruction is transferred over to the remote I2C bus. For example, when theI2C master is connected to the deserializer and I2C pass-through is enabled on the deserializer, any I2C traffictargeted for the remote serializer or remote slave will be allowed to pass through the deserializer to reach thoserespective devices.

See Figure 25 for an example of this function and refer to application note I2C over DS90UB913/4 FPD-Link IIIwith Bidirectional Control Channel (SNLA222).

If master controller transmits I2C transaction for address 0xA0, the DES A with I2C pass-through enabled willtransfer I2C commands to remote Camera A. The DES B with I2C pass-through disabled, any I2C commandswill NOT be passed on the I2C bus to Camera B.

Figure 25. I2C Pass-Through

http://www.ti.com/product/ds90ub913a-q1?qgpn=ds90ub913a-q1http://www.ti.comhttp://www.ti.com/lit/pdf/SNLA222http://www.ti.com/lit/pdf/SNLA222


HOST Serializer

SCL

SDA

RPU RPU

R3

R4

SCL

SDA

To other Devices

ID[x]

1.8V

VDDIO

28



Programming (continued)9.5.4 Slave Clock StretchingThe I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an externalremote device (such as image sensor) through the bidirectional control. To communicate and synchronize withremote devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clockstretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line lowon the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock andonly stretches it until the remote peripheral has responded. The I2C master must support clock stretching tooperate with the DS90UB913A/914A chipset.

9.5.5 ID[x] Address Decoder on the SerializerThe ID[x] pin on the Serializer is used to decode and set the physical slave address of the Serializer (I2C only) toallow up to five devices on the bus connected to the Serializer using only a single pin. The pin sets one of the 6possible addresses for each Serializer device. The pin must be pulled to VDD_n (1.8 V, not VDDIO) with a 10-kΩresistor and a pull-down resistor (RID) of the recommended value to set the physical device address. Therecommended maximum resistor tolerance is 1%.

Figure 26. ID[x] Address Decoder on the Serializer

Table 6. IDX Setting for DS90UB913A-Q1 SerializerIDX Setting — DS90UB913A-Q1 SERIALIZER

MINIMUMRATIO

(VIDX/V(VDD_n))

MAXIMUMRATIO

(VIDX/V(VDD_n))

SUGGESTEDR3 RESISTORVALUE (kΩ)

SUGGESTEDR4 RESISTORVALUE (kΩ)

Address 7-bitAddress 8-bit0 appended(WRITE)

0 0 Open 0 0x58 0xB00.114 0.186 10 2 0x59 0xB20.297 0.347 10 4.7 0x5A 0xB40.436 0.464 10 8.2 0x5B 0xB60.564 0.608 10 14 0x5C 0xB80.742 1.0 10 100 0x5D 0xBA



ECU

Module


DIN[11:0]

, HS, VS,

PCLK

CMOSImageSensor

I2C I

2C

SDASCL

SDASCL

PC

DES B: ID[x](0xC2)

SLAVE_ID0_ALIAS(0xA4)

SLAVE_ID0_ID(0xA0)


SLAVE_ID1_ID(0xA2)


CMOSImageSensor

I2C I

2C

SDASCL

SDASCL

Camera BSlave ID: (0xA0)

SER A: ID[x](0xB0)DES A: ID[x](0xC0)


SLAVE_ID0_ID(0xA0)


SLAVE_ID1_ID(0xA2)

Camera ASlave ID: (0xA0)

MasterSER B: ID[x](0xB2)

Slave ID: (0xA2)

Slave ID: (0xA2)

ROUT[11:0], HS, VS,PCLK

DIN[11:0], HS, VS,

PCLK

ROUT[11:0],

HS, VS,PCLK

PC/EEPROM

PC/EEPROM

29



9.5.6 Multiple Device AddressingSome applications require multiple camera devices with the same fixed address to be accessed on the same I2Cbus. The DS90UB913A provides slave ID matching/aliasing to generate different target slave addresses whenconnecting more than two identical devices together on the same bus. This allows the slave devices to beindependently addressed. Each device connected to the bus is addressable through a unique ID by programmingof the Slave alias register on Deserializer. This will remap the Slave alias address to the target SLAVE_IDaddress; up to 8 ID Alias's are supported in sensor mode when slaves are attached to the DS90UB913Aserializer. In display mode, when the external slaves are at the deserializer the DS90UB913A supports one IDAlias. The ECU Controller must keep track of the list of I2C peripherals in order to properly address the targetdevice.

See Figure 27 for an example of this function.• ECU is the I2C master and has an I2C master interface• The I2C interfaces in DES A and DES B are both slave interfaces• The I2C protocol is bridged from DES A to SER A and from DES B to SER B• The I2C interfaces in SER A and SER B are both master interfaces

If master controller transmits I2C slave 0xA0, DES A (address 0xC0), with pass through enabled, will forward thetransaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognizethat 0xA4 is mapped to 0xA0 and will be transmitted to the remote Camera B. If controller sends command toaddress 0xA6, the DES B (address 0xC2), with pass through enabled, will forward the transaction to slave device0xA2.

Figure 27. Multiple Device Addressing


30



(1) To ensure optimum device functionality, It is recommended to NOT write to any RESERVED registers.

9.6 Register MapsIn the register definitions under the TYPE and DEFAULT heading, the following definitions apply:• R = Read only access• R/W = Read / Write access• R/RC = Read only access, Read to Clear• (R/W)/SC = Read / Write access, Self-Clearing bit• (R/W)/S = Read / Write access, Set based on strap pin configuration at startup• LL = Latched Low and held until read• LH = Latched High and held until read• S = Set based on strap pin configuration at startup

Table 7. DS90UB913A-Q1 Control Registers (1)

Addr(Hex) Name Bits Field TYPE Default Description

0x00 I2C Device ID7:1 DEVICE ID

R/W0xB0'h

(1011_0000'b)

7-bit address of Serializer (0x58'h default).This field does not auto update IDX strapped address.

0 Serializer ID SEL 0: Device ID is from ID[x].1: Register I2C Device ID overrides ID[x].

0x01 Power and Reset

7 RSVD R/W 0 Reserved.

6 RDS R/W 0Digital Output Drive Strength.1: High Drive Strength.0: Low Drive Strength.

5 VDDIO Control R/W 1Auto Voltage Control.1: Enable.0: Disable.

4 VDDIO MODE R/W 1VDDIO Voltage set.1: VDDIO = 3.3 V.0: VDDIO = 1.8 V.

3 ANAPWDN R/W 0

This register can be set only through local I2C access.1: Analog power down. Powers down the analog blockin the Serializer.0: No effect.


1 DIGITALRESET1 R/W 0

1: Resets the digital block except for register values.Does not affect device I2C Bus or Device ID. This bitis self-clearing.0: Normal Operation.

0 DIGITALRESET0 R/W 01: Digital Reset, resets the entire digital block includingall register values. This bit is self-clearing.0: Normal Operation.

0x02 Reserved


31



Register Maps (continued)Table 7. DS90UB913A-Q1 Control Registers(1) (continued)


0x03 GeneralConfiguration

7 RX CRC CheckerEnable R/W 1Back-channel CRC checker enable1: Enable0: Disable

6 TX ParityGenerator Enable R/W 1Forward channel parity generator enable.1: Enable0: Disable

5 CRC Error Reset R/W 0

Clear CRC error countersThis bit is NOT self-clearing.1: Clear counters0: Normal operation

4I2C Remote WriteAutoAcknowledge

R/W 0

Automatically acknowledge I2C remote writeThe mode works when the system is LOCKed.1: Enable: When enabled, I2C writes to thedeserializer (or any remote I2C Slave, if I2C PASSALL is enabled) are immediately acknowledgedwithout waiting for the deserializer to acknowledge thewrite. The accesses are then remapped to addressspecified in 0x06.0: Disable

3 I2C Pass-Through All R/W 0

1: Enable Forward Control Channel pass-through of allI2C accesses to I2C IDs that do not match theserializer I2C ID. The I2C accesses are thenremapped to address specified in register 0x06.0: Enable Forward Control Channel pass-through onlyof I2C accesses to I2C IDs matching either the remotedeserializer ID or the remote I2C IDs.

2 I2C Pass-Through R/W 1

I2C Pass-through mode1: Pass-through enabled. DES alias 0x07 and slavealias 0x090: Pass-through disabled

1 OV_CLK2PLL R/W 0

1:Enabled : When enabled this register overrides theclock to PLL mode (External Oscillator mode or DirectPCLK mode) defined through MODE pin and allowsselection through register 0x35 in the serializer.0: Disabled : When disabled, Clock to PLL mode(External Oscillator mode or Direct PCLK mode) isdefined through MODE pin on the Serializer.

0 TRFB R/W 1

Pixel clock edge select1: Parallel interface data is strobed on the rising clockedge0: Parallel interface data is strobed on the falling clockedge

0x04 Reserved.


32





0x05 Mode Select

7 RSVD R/W 0 Reserved.6 RSVD R/W 0 Reserved.

5 MODE_OVERRIDE R/W 0

Allows overriding mode select bits coming from back-channel.1: Overrides MODE select bits.0: Does not override MODE select bits.

4 MODE_UP_TO_DATE R 01: Status of mode select from Deserializer is up-to-date.0: Status is NOT up-to-date.

3Pin_MODE_12–bit HighFrequency

R 0 1: 12-bit high frequency mode is selected.0: 12-bit high frequency mode is not selected.

2 Pin_MODE_10–bit mode R 01: 10-bit mode is selected.0: 10-bit mode is not selected.

1 TX_MODE_12b R/W 0

Selects 12 bit data-bus. This bit changes the Tx modesettings if MODE_OVERRIDE is SET 0x05[5] = 1.1: Enables 12 bit HF mode0: Disables 12 bit HF modeNote: This bit changes mode settings on TX. WhenTX_MODE_12b is set TX_MODE_10b must becleared; 0x05[1:0] = 10.

0 TX_MODE_10b R/W 0

Selects 10 bit data-bus. This bit changes the Tx modesettings if MODE_OVERRIDE is SET 0x05[5] = 1.1: Enables 10b mode0: Disables 10b modeNote: This bit changes mode settings on TX. WhenTX_MODE_10b is set TX_MODE_12b must becleared; 0x05[1:0] = 01.

0x06 DES ID

7:1 DeserializerDevice ID R/W 0x00'h

7-bit Deserializer Device ID Configures the I2C SlaveID of the remote Deserializer. A value of 0 in this fielddisables I2C access to the remote Deserializer. Thisfield is automatically configured by the BidirectionalControl Channel once RX Lock has been detected.Software may overwrite this value, but should alsoassert the FREEZE DEVICE ID bit to preventoverwriting by the Bidirectional Control Channel.

0 Freeze Device ID R/W 0

1: Prevents auto-loading of the Deserializer Device IDby the bidirectional control channel. The ID will befrozen at the value written.0: Update.

0x07 DES Alias7:1 DeserializerALIAS ID R/W 0x00

7-bit remote deserializer device alias ID Configures thedecoder for detecting transactions designated for anI2C deserializer device. The transaction is remappedto the address specified in the DES ID register.A value of 0 in this field disables access to the remotedeserializer.

0 RSVD R/W 0 Reserved

0x08 SlaveID7:1 SLAVE ID R/W 0x00'h

7-bit Remote Slave Device ID Configures the physicalI2C address of the remote I2C Slave device attachedto the remote Deserializer. If an I2C transaction isaddressed to the Slave Alias ID, the transaction will beremapped to this address before passing thetransaction across the Bidirectional Control Channel tothe Deserializer and then to remote slave. A value of0 in this field disables access to the remote I2C slave.



33





0x09 Slave Alias7:1 SLAVE ALIAS ID R/W 0x00'h

7-bit Remote Slave Device Alias ID Configures thedecoder for detecting transactions designated for anI2C Slave device attached to the remote Deserializer.The transaction will be remapped to the addressspecified in the Slave ID register. A value of 0 in thisfield disables access to the remote I2C Slave.


0x0A CRC Errors 7:0 CRC Error Byte 0 R 0x00'h Number of back-channel CRC errors during normaloperation. Least Significant byte.

0x0B CRC Errors 7:0 CRC Error Byte 1 R 0x00'h Number of back-channel CRC errors during normaloperation. Most Significant byte.

0x0C General Status

7:5 Rev-ID R 0x0'h Revision ID.0x0: Production Revision ID.

4 RX Lock Detect R 0 1: RX LOCKED.0: RX not LOCKED.

3 BIST CRCError Status R 01: CRC errors in BIST mode.0: No CRC errors in BIST mode.

2 PCLK Detect R 0 1: Valid PCLK detected.0: Valid PCLK not detected.

1 DES Error R 0

1: CRC error is detected during communication withDeserializer.This bit is cleared upon loss of link or assertion ofCRC ERROR RESET in register 0x03[5].0: No effect.

0 LINK Detect R 0

1: Cable link detected.0: Cable link not detected.This includes any of the following faults:— Cable Open.— '+' and '-' shorted.— Short to GND.— Short to battery.

0x0DGPO[0]

and GPO[1]Configuration

7 GPO1 OutputValue R/W 0

Local GPIO Output Value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is Output, and remote GPIOcontrol is disabled.

6 GPO1 RemoteEnable R/W 1

Remote GPIO Control.1: Enable GPIO control from remote Deserializer. TheGPIO pin needs to be an output, and the value isreceived from the remote Deserializer.0: Disable GPIO control from remote Deserializer.


4 GPO1 Enable R/W 1 1: GPIO enable.0: Tri-state.

3 GPO0 OutputValue R/W 0

Local GPIO Output Value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is Output, and remote GPIOcontrol is disabled.

2 GPO0 RemoteEnable R/W 1

Remote GPIO Control.1: Enable GPIO control from remote Deserializer. TheGPIO pin needs to be an output, and the value isreceived from the remote Deserializer.0: Disable GPIO control from remote Deserializer.


0 GPO0 Enable R/W 1 1: GPIO enable.0: Tri-state.


34





0x0EGPO[2]

and GPO[