DS1 for ATM

8/3/2019 DS1 for ATM

1/29

DS1: ATM Physical Interface

Tuan Nguyen-viet


2/29

GENERAL

Part 1


3/29

ATM Cell


4/29

Header Error Control (HEC)

The header field HEC protects only the header (not the payload!).

Error control of the payloadis performed by higher layerprotocols and applications.

The integrity of the header is extremely important because a corrupted header can cause

delivery of cells to wrong addresses, or can interfere with network management.

This can bring the network in a catastrophic condition.


5/29

Header Error Control (HEC): contd

Among all errors in fiber-optic transmission media, 99.64% of them are single bit errors.

This means that two-bitor three-bit errors are not very likely.

However, it is also known from the experience that the large error bursts have also a

high probability (of course, far less than single bit errors, but far more than two, three or four bit errors).

This fact has influenced the design of the ATM error control mechanism and the

size of the HEC field.


6/29

BCH (8-bit CRC + Hamming code)

ATM layer uses the Bose-Chadhuri-Hocquenghem (BCH) algorithm which corrects single-bit

errors and detects multiple bit errors.

The algorithm is based on a combination of

the 8-bit CRC scheme (which can detect errors) and

Hamming code (which can correct single bit errors).

This combination is based on the redundancy of HEC, which has 8 bits and is used toprotect only 5x8 = 40 bits (5 header bytes).

The coding theory shows that only 6 bits are necessary to detect and correct a single bit error

in a message that has 40 bits.

Furthermore, an extended 8-bit HEC can correct single-bit errors and detect 84% of

other errors.


7/29

BCH (8-bit CRC + Hamming code): 2 of 3

The algorithm computes the HEC value by modulo-two division of the header bit pattern

(with the HEC field initialized to zeroes) by the CRC generator whose polynomial is x8 + x2 + x

+ 1.

The remainder of the modulo-two division is then OR-ed with 01010101 and placed into

the last octet of the cell header (HEC field).

Similar operation is performed at the receiver's side, where the entire header (including HEC

field) is modulo-two divided by the CRC generator.

The error correction capability greatly diminishes

the need for cell discarding, and consequently,

the need for cell retransmission.


8/29

BCH (8-bit CRC + Hamming code): 3 of 3

The working of the HEC algorithm (which uses BCH error coding) can be described by the

following two-state diagram:

The algorithm starts in "correction mode" state.

In detection mode the cells have an opportunity to be corrected (if the error is single-

bit). If any error happens, the state is changed to detection mode, and it stays there as long as

errors persist.

This is designed to handle error bursts.

It is assumed that the burst has stopped if a valid cell entered the switch - then the state ischanged back to the correction mode.


9/29

ATM Physical Layer

Physical Medium Dependent (PMD) Sub-layer:

Fiber, Twisted-Pair, Coax, etc.

SONET/SDH, DS3/DS1, E3/E1, etc.

Transmission convergence (TC) layer:

Convert bit stream to cell stream

Transmission frame adaptation: packing cells into frames

Cell delineation: scrambling and cell recovery after descrambling

HEC generation and verification

Cell rate decoupling: Insertion and suppression ofIdle cells.


10/29

FRAMING

Part 2


11/29

DS1 System


12/29

DS1 System (2)


13/29

E1 System


14/29

E1 System (2)


15/29

HDLC frame

In HDLC, we use a special octet, the string of bits 0111 1110, as a framing character. Inside

the frame, we suppress occurrences of this string with a technique known as zero bit

insertion.

And since HDLC frames can be variable length, we use another of these special characters as

an ending flag to show where the frame ends.


16/29

TRANSMISSION STRUCTURE

Part 3


17/29

Cell-Stream Physic

Continuous stream of cells.

No framing.

Hunt bit-by-bit for correct header.


18/29

Cell Alignment/Delineation

Since cells have no flags to indicate their beginning and theend,

there must be some "pattern recognition" algorithm to find the exact location of a cell ina stream of incoming bits.

To accomplish this, the receiver checks if a candidate header is valid:

it modulo-two divides the 40 bits of the supposed header with the CRC generator.

A zero remainder would indicate the possibility for a valid header.

If the remainder is not zero, the receiver moves one bit further and perform the

check again. This process continues, bit-by-bit, until a successful match occurs.

As seen, the HEC has two functions: error control and cell synchronization (alignment,

delineation).


19/29

Cell Alignment/Delineation (2)


20/29

Cell Scrambling

What happens if apayloadaccidentally contains a 40-bit sub-pattern which satisfies the

HEC?

This situation must be not permitted.

Therefore the ATM forum has proposed an optional capability of cell scrambling, which

looks for a bit pattern within the payload that satisfies the HEC.

If such bit pattern is found, it is modified so that the match cannot occur within the payload, and

that the payload can be easily unscrambled at the receiver's side.


21/29

Repetitive Checking

The HEC is not 100% accurate.

Therefore the check must be performed several times successfully on three consecutivecells before the receiver finally can decide that it has found the right header and is in

synchronism.

This is called repetitive checking.

A usual value of repetitions is three times.


22/29

Repetitive Checking (2)

The repetitive checking algorithm, which is performed at the receiver's side, can be

represented as a three-state diagram. The algorithm starts in "hunt mode" where it moves bit-by-bit in search for a valid header.

Then it goes to "presync mode" where it continues to move cell-by-cell, looking for

three (in general case ) successful header matches, which is a condition for

synchronism.

In "sync mode" the algorithm starts regular error checking based on the HEC field.

If there are more than unsuccessful HEC, the receiver considers itself to be out ofsynchronism, and goes back to "hunt mode".


23/29

MAPPING ATM OVER DS1

Part 4


24/29

Direct Mapping

When direct mapping framing mode is used, cell delineation is used to locate the cell

boundaries.

Cell delineation is the process of framing to ATM cell boundaries using the header error

checksum (HEC) field found in the ATM cell header.

The HEC is a CRC-8 calculation over the first 4 bytes of the ATM cell header.

When performing delineation, correctHEC calculations are assumed to indicate cell

boundaries.

An initial bit by bit search is made for a correct HEC sequence (HUNT state).

Once located, the particular cell boundary is noted (PRESYNC state) and the search

continues to determine whether the following pattern is correct.

Once noincorrectHECis received within a set number of cells, the SYNC state isdeclared.

In this state, synchronization is not relinquished until a set number of consecutive

incorrectHEC patterns are received.


25/29

Direct Mapping (2)

ATM cells shall be carried in the DS1 payload (bits 2 -193).

ATM cells are byte-aligned to the DS1 frame.

Cell delineation function shall be performed using the HEC mechanism.

af-phy-0016.000:

Payload scrambling shall not be used.

ITU-T G.804:

As an option, the ATM cell payload (48 bytes) can be scrambled before mapping

into the 1544 kbps signal.


26/29

Physical Layer Convergent Protocol (PLCP) Mapping

The PLCP frame is octet alignedto theframing bitin the DS1 frame.

There is no relationship between the start of the PLCP frame and the start of the DS1

frame.

A 6-byte trailer is inserted at the end of each PLCP frame.

The DS1 PLCP frame provides the transmission often ATM cells every 3 msec.

10 x 57 + 6 = 576 bytes,

576 bytes / 24 = 24 bytes => 24 x DS1 frames => 125us x 24 = 3000us = 3ms.

The network transmission rate is thus 160 Kbytes/sec.


27/29

PLCP Mapping (2)

A1/A2 bytes:

Framing pattern octet.

PLCP framing octets use the same framing pattern as used in the SDH.

These octets are defined as A1 = 11110110, A2 = 00101000

B1 byte:

Bit Interleaved Parity-8 (BIP-8) field supports path error monitoring (EM).

G1 byte:

PLCP path status.

The PLCP path status is allocated to convey the received PLCP status and performance

to the transmitting far-end.

Figure below illustrates the G1 octet subfields: a 4-bit Far-End Block Error (FEBE), a 1-bit

Remote Alarm Indication (RAI), and 3 X bits (X bits are set to all ones at the transmitter

and may be ignored at the receiver).

The use of the PLCP path status octet G1 for the Far-End Receive Failure (FERF) isforfurther study.


28/29

PLCP Mapping (3)

Px (0-9) Path overhead identifier:

Path Overhead Identifier indexes the adjacentPath Overhead (POH) octet of the PLCP.

C-byte:

Pad bit counter.

M-bytes:

Management information.

F-byte:

PLCP path user channel.

Z-byte:

For future use.


29/29

Thank You !

Documents

DS1 for ATM