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Dorothy Gordon. Digital Sub-System. Overview. Digital Subsystem Overview/Block Diagram Developments Since PDR Design/Implementation Status Next. 27 June 2006. Digital Engineering. 2. Digital Sub-System Data Flow. 27 June 2006. Digital Engineering. 3. Digital Sub-System Block Diagram. - PowerPoint PPT Presentation
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Cosmic RAy Telescope for the Effects of Radiation
Digital Sub-System
Dorothy Gordon
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006Digital Engineering 2
Overview
• Digital Subsystem Overview/Block Diagram
• Developments Since PDR
• Design/Implementation Status
• Next
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006Digital Engineering 3
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
AmptekPH300Peak Det.
MaximMAX14512 bit A/D
FPGARTSX72SU
1553 XCVRSide A
1553 XCVRSide B
1 Hz
RTD
8 bit DACTest Pulse Amplitude
Test Pulse Trigger (x2)
AnalogBoard S/C
Digital Sub-System Data Flow
Cosmic RAy Telescope for the Effects of Radiation
Digital Sub-System Block Diagram
225VN75VN
5VN VCC
225VP
5VP
75VP
5VN5VP
1553_A
1553_B
S/C1HZCLOCKAE
I/FS/CI/F
Crater Analog Housekeeping
28VDC +RETURN
to Analog Housekeeping
Also sent to AE Subystem: Vref (2.5 V.), Vcc (5V)and Digital Ground
tRTD
PWM to DC
Buffer
0 - 5 V. 8 bit
Test Pulse I/F
PCKOUT[1:0] PCK[1:0]
ECAL-DC ECALPWM
PWM to DC
~0 - 1.4V. 8 bit
PWM to DC
~0 - 1.4V. 8 bit
LLD Threshold
LLDTHIN-DC LLDTHINPWM
LLDTHKPWMLLDTHCK-DC
1553 BusProtocolController -Transceiver
Diff.Rcvr
SCLK
RESET
+-
Spacecraft Data Interface
1553Dat[15:0]
1553AdrCntl[22:0]
A-
A+
B+
B-
1PPS_+CLK1HZ
CLK16M
Reset
1PPS_-
Peak Detect/Hold ADC
VthresholdComparator
x6 x6
x6
Analog Signal Processing
DetSigIn[5:0] ADC-CntlDat[5:0]
DetTrig[5:0]
PDReset[5:0]
ThrThin
ThrThick
AnalogMux
ADC
PreconditionFilter/Scale
x2
x2
Housekeeping
HSKPIN[23:0]
MADRSEL[4:0]
ADC-CntlDat[1:0]
EMIFilter
DC to DC Conversion
5V
28VDC_+
28VDC_-
5V_+
5V_-
GND
ThickDetBiasEnb
ThinDetBiasEnb
225V_+
75V_+
BCLK[1:0]
CDM-FPGA
SRAM
Power-OnReset OSC
Crater Data Control
DetTrig[5:0]
1553Dat[15:0]ADC-CntlDat[5:0]
1553AdrCntl[22:0]
CLK16M
CLK1HZ
ECALPWM
HWReset
BiasVEnb[1:0]
ECAL-PCK[1:0]
HADRSEL[4:0]
HADC-CntllDat[1:0]
PDReset[5:0]LLDTHKPWMLLDTHNPWM
SngCnt[5:0]
BiasClk[1:0]
DetSig[5:0]
ThinDetBias
ThickDetBias
RT_P
RT_NSigGnd
AETemp[1:0]
5VP
5VN
TP-PCK[1:0]
P-LEVEL
SngCnt[5:0]
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006Digital Engineering 5
Developments since PDR
• Requirements – no significant changes
• Parts Selection– DDC BU-63705 for 1553 Bus, Actel SX72, Amptek PH300
– DC-DC Converter Modules (International Rectifier)
• Peak Stretcher (PH300): Performance Verified via Breadboard
• Functional Description/Specification– Details of FPGA operation (Drawing # 32-03010)
• Schematics – Board Schematics: released (Drawing # 32-03003)
– Chassis Schematics: released (Drawing # 32-03006)
– High Voltage Power Supply (Drawing #32-03003.01)• (subcontracted) design complete – prototype in house
Cosmic RAy Telescope for the Effects of Radiation
Since PDR (continued)
• Peer Review (GSFC, May 22, 2006)– Received/Answered 15 RFAs (for both analog and digital subsystems)
• No change to fundamental design of either subsystem
• Part type modification (to insure edge-rate compatibility)
• Actel Programming Socket exchanged (for “ESD Friendly” replacement)
• Actel Static Timing analysis to include asynchronous clocked path analysis
• Signal Integrity and Ground bounce concerns (especially relative to the SX72 FPGA)
• Analysis– Parts Stress Analysis: released (Drawing #32-03010.03)
– Worst Case Analysis: released (Drawing #32-04011.02)
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006Digital Engineering 7
Design/Implementation Status
• FPGA Design – VHDL Coding Complete (Drawing #32-03003.10)
– Top Level functional simulation complete
– Timing Verified (Static Timer and Dynamic Simulation)
• Engineering Board (ETU) Layout and Fabrication completed – Engineering layout is flight part footprint compatible
– High Voltage Supply, implemented on hand-wired breadboard, will be integrated during the second layout stage
• ETU Population – Completion expected by last week of June
8
Board Layout
27 June 2006Digital Engineering 9
Cosmic RAy Telescope for the Effects of Radiation
27 June 2006Digital Engineering 10
Cosmic RAy Telescope for the Effects of Radiation
Next
• Design Complete – ready for board level check-out
• Next– Test with GSE
– Verify basic functionality/operation
– Develop/run marathon diagnostics
– Integrate with analog board
• Flight Version– Incorporate any modifications resulting from ETU debug
– Add Bias (High Voltage) Supply