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CDA 3101 Spring 2016 Introduction to Computer Organization Digital Logic “102” 12 Jan 2016 Mark Schmalz http://www.cise.ufl.edu/~mssz/CompOrg/Top- Level.html

Digital Logic “102” 26 August 2013 Mark Schmalz

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CDA 3101 Fall 2013 Introduction to Computer Organization. Digital Logic “102” 26 August 2013 Mark Schmalz http://www.cise.ufl.edu/~mssz/CompOrg/Top-Level.html. Overview. Review of gates and truth tables Boolean algebra - PowerPoint PPT Presentation

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Page 1: Digital Logic “102” 26 August 2013 Mark Schmalz

CDA 3101 Spring 2016

Introduction to Computer Organization

Digital Logic “102”

12 Jan 2016Mark Schmalz

http://www.cise.ufl.edu/~mssz/CompOrg/Top-Level.html

Page 2: Digital Logic “102” 26 August 2013 Mark Schmalz

Overview

• Review of gates and truth tables

• Boolean algebra

• Complex logic circuits

• Combinational logic systems

• Clocking

• Memory elements

Page 3: Digital Logic “102” 26 August 2013 Mark Schmalz

Transistors

NOT gate (Inverter)

Symbol

Functional Behavior

Page 4: Digital Logic “102” 26 August 2013 Mark Schmalz

NOT Gate NAND Gate

Gate Symbol

Truth Table

Page 5: Digital Logic “102” 26 August 2013 Mark Schmalz

AND, OR, NOR Gates

NOR

Page 6: Digital Logic “102” 26 August 2013 Mark Schmalz

Boolean Algebra

• Basic operators: OR (sum), AND (product), NOT• Boolean laws:

Page 7: Digital Logic “102” 26 August 2013 Mark Schmalz

Circuit Equivalence

Page 8: Digital Logic “102” 26 August 2013 Mark Schmalz

The Majority Function

M = f (A, B, C)

M = ABC + ABC + ABC + ABC

Page 9: Digital Logic “102” 26 August 2013 Mark Schmalz

Step 3. a) Build SOP circuit using minterms (M=1);b) OR minterms

The Majority Function (cont’d)M = f (A, B, C)

Step 1. Build truth table for logic function f.

Step 2. Write logic equation in SOP form.

3a

3b

M = ABC + ABC + ABC + ABC1 1 0

Page 10: Digital Logic “102” 26 August 2013 Mark Schmalz

Combinatorial Logic

• Many inputs and many outputs

• Outputs are uniquely determined by inputs

• Absence of memory elements

• Basic combinatorial circuits– Multiplexers– Demultiplexers– Decoders– Comparators

Page 11: Digital Logic “102” 26 August 2013 Mark Schmalz

Multiplexer

2n data inputs

1 data output

n control inputs

Page 12: Digital Logic “102” 26 August 2013 Mark Schmalz

Decoder

n data inputs

2n data outputs

3-to-8 decoder

Page 13: Digital Logic “102” 26 August 2013 Mark Schmalz

Comparator

Page 14: Digital Logic “102” 26 August 2013 Mark Schmalz

Two-Level Logic

x

PLA 12 inputs 6 outputs

Page 15: Digital Logic “102” 26 August 2013 Mark Schmalz

Clocks

Clock period

Page 16: Digital Logic “102” 26 August 2013 Mark Schmalz

Edge-Triggered Clocking

StateElement

1

StateElement

2

Combinational logic

State

Element

Combinational logic

Page 17: Digital Logic “102” 26 August 2013 Mark Schmalz

NOR SR Latch

State 0 State 1

Inputs S - set

R - resetOutputs: Q and Q

Page 18: Digital Logic “102” 26 August 2013 Mark Schmalz

Clocked SR Latch

Page 19: Digital Logic “102” 26 August 2013 Mark Schmalz

Clocked D Latch

D

C

Q

Page 20: Digital Logic “102” 26 August 2013 Mark Schmalz

D flip-flop

D

C

Q

C

D QD

latchC

D QD

latch

C

D Q

QQ

Setup time

hold time

Page 21: Digital Logic “102” 26 August 2013 Mark Schmalz

Conclusions

• Digital logic – lowest level of CDA3101 worldview

• Digital logic circuits– Made from building blocks (AND,OR,NOT,…)– Simple or Complex, Combinatorial– Synchronous (clocked) or Asynchronous

• Know rules for Boolean Algebra

Enjoy your week!!