Digital Design

Haldun HadimiogluComputer and Information Science

3/30/2003

CS 2204 Laboratory

3/30/2003 Digital Design 2

CS 2204

Title : Digital Logic and State Machine Design

Credits : 4

Year : Sophomore

Format : Lectures and Laboratory 3-hour lectures

3-hour laboratory sessions

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CS 2204

Content : Digital circuit fundamentalsTheory, analysis, design

Digital clock Car alarm Traffic light controller Vending machine controller Four function calculator

Precursor to courses : Computer Architecture : computer design (junior) Advanced hardware design : chip design (senior)

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CS 2204 Laboratory

Emphasis on design

20 students per lab 2-student teams formed first week

Teams do lab projects and homework

How to approach a large design Problem analysis and solving

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CS 2204 Laboratory

Introduces current digital design techniques and tools

Team-oriented, top-down, core-based design

Modern hardware development environment

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CS 2204 Laboratory

Hardware development environment Computer Aided Design (CAD) Software : Xilinx Foundation (industry software)

Simulates hardware

Testing hardware : Digilent board FPGA Chip on Digilent board

FPGA : Field Programmable Gate Array

Emulates hardware

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CS 2204 Laboratory

Why CAD Design ? Circuit design and test before physical implementation

Shorter and cheaper developmentDesign objectives reached faster

Speed, cost, power consumption, size, weight, reliability,..

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CS 2204 Laboratory

Term Project Spring 2003 : Game playing circuit

Human vs machine play against each other

Derived from dominoes Chance and thinking determine winner

Pieces of circuit completed in 3 to 4 week experiments (deadlines)

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Historical Trend

Mechanical components replaced by Analog components and

Digital components

Analog components replaced by Digital components

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Digital Revolution

Computers (laptops to supercomputers)

Microprocessors (Sun Sparc to Intel Pentium 4)

Car engine controllersCalculators

Video games

CD Players

Digital cameras

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Benefits of Digital Circuits

Moore’s Law holds since the 1960s Every two years, number of transistors on chips doubles

Every two years memory size doubles

Smaller size devices

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Digital Chip

Electronic components are placed inDie area in center of the chip

There can be50 million components

transistors on a microprocessor die

A chipThe die

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Is It Always A Chip ?

NO !Design on computers kept as

Circuit diagrams : traditional Hardware Description Language (HDL) programs : since 1980s

Companies license their design as Intellectual Property (IP)

Circuit diagram/HDL program files Used as core circuits

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Digital Circuits

A digital circuit consists of Gates and Flip-Flops

on chips

All chips on Printed Circuit Boards (PCBs)

1 142

45

6

7

3

8

9

10111213

A 4

A 3

A 2

A 1

Y 4

Y 3

Y 2

Y 1

V cc

GND

B 4

B 3B 2

B 1

7408 AND gate Chip

Notch

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CS 2204 Digital Components

Gates

Flip-flops

ANDORNOTk

m k + m

OR gate

km

k.m k k

AND gate NOT gate (inverter)

D Q

C

D Flip-flop J-K Flip-flop

Q

Q

QC

J

K

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A Digital Circuit

Car seat-belt alarm Alarm sound if engine is running AND seat-belt is NOT fastened

Digitalcircuit

engine

Seat belt

alarm

AND

Seat belt

engine

AND

OR

NOT

alarm

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Another Digital Circuit

a

bAND

AND

OR

NOT

y(a, b, c)

p

q

rc

Digitalcircuit

a

by(a, b, c)

c

if a is 0 => y =aif a is 1 => y = c

CircuitDiagram(Traditional)

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The Same circuit

--MULTIPLEXER

--VHDL STRUCTURAL MODELING

entity multiplexer is

port (A, B, C : in BIT;

y : out BIT);

end multiplexer;

architecture structure of multiplexer is

signal p, q, r: BIT;

begin

p <= NOT a;

q <= p AND b;

r <= a AND c;

y <= p OR q;

end structure;

Digitalcircuit

a

by(a, b, c)

c

if a is 0 => y =aif a is 1 => y = c

VHDLProgram !

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1-bit Adder Design

A 1-bit Adder, Full Adder :

a

b

ci

s

co

1-bit

Adder

a ci b co s

0 0 0 1 1 0 1 1 0 0 0 . . . 1 0 0 0 1 0 1 1 1

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The 1-bit Adder

CircuitDiagram

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Designing the 1-bit Adder--FULL ADDER--STRUCTURAL MODELING

entity fulladder isport (A, B, CIN : in BIT;

SUM, COUT : out BIT);end fulladder;

architecture structure of fulladder issignal s1, s2, s3,s4,s5: BIT;begin

s1 <= A xor B;SUM <= s1 xor CIN;s2 <= A and B;s3 <= B and CIN;s4 <= A and CIN;s5 <= s2 or s3;COUT <= s4 or s5;

end structure;

VHDLProgram