? Digital Logic and State Machine Design Experiment 6 Labs 9, 10, 11, 12, 13 CS 2204 Appendices Spring 2014 Lab 10

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Digital Logic and

State Machine Design

Experiment 6

Labs 9, 10, 11, 12, 13

CS CS 22042204CS CS 22042204

Appendices

Spring Spring 20142014Spring Spring 20142014

Lab 10

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Experiment 6 Appendices Page 2CS 2204 Spring 2014

Appendices Labs 10 - 13 Outline Presentation

Machine Player Example 2 (Lab 10) Digital product development overview (Lab 11)

Component selection for a new chip• Xilinx component usage

Component selection for a new PCB• TTL LS SSI chip usage

Semiconductor technology overview (Lab 12) Submitting the term project

Submitting the term project (Lab 13)

Individual work Developing Ppm Block 6

Lab 10


Block 6, Machine Play Block Development1. Start with the black box view where the outputs are fixed and

the input/output relationshipa) Understand the game rules and how the machine player has to

interact with the rest of the Ppm digital systemb) Determine the playing strategy (intelligence)c) Determine the inputs

Play on the (rightmost)

largest regular reward position

(directly if equal)

(Action 0)

We know the game rules already !

Exam

ple

1

Block 6? ?

Lab 10


Block 6, Machine Play Block Development1. Start with the black box view where the outputs

are fixed and the input/output relationship b) Determine the playing strategy (intelligence)

Always plays (does not skip at all) Plays on the largest regular reward points position

directly or with an addition (choose direct playing if reward points are equal)

If two or more positions have the same regular reward, selects the rightmost one (can also select randomly, or round robin, etc.)

If playing directly on a left side position gives the same regular reward points as playing with an addition on the right side, playing directly on the left side is chosen



(directly if equal)

(Action 0)

Exam

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1Lab 10



are fixed and the input/output relationship c) Determine the inputs

We have to collect eight regular reward points for eight possibilities• Four regular reward points on four displays with direct

playing• Four regular reward points on four displays with additions

We will collect the eight regular reward points sequentially• This will take 8 clock periods !

Then, we will play on a position in the ninth clock period



(directly if equal)

(Action 0)

Exam

ple

1

Player 2 spends NINE P2clk periods to think

Lab 10


Block 6, Machine Play Block Development1. Start with the black box view where the outputs are fixed

and the input/output relationshipa) Understand the game rules and how the machine player has

to interact with the rest of the Ppm digital systemb) Determine the playing strategy (intelligence)c) Determine the inputs

Exam

ple

1

We need to collect the regular reward points : RWD

We will collect eight regular reward points sequentially

We have to input : P2sturn, Clearp2ffs, P2clk



(directly if equal)

(Action 0)

Block 6? ?

Lab 10





Exam

ple

1

Block 6

RWD8

P2sturn

P2clk

We input RWD

We input P2sturn, Clearp2ffs, P2clk Clearp2ffs

?



(directly if equal)(Action 0)

Lab 10





Exam

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1

The outputs are fixed !

Block 6

RWD8

P2sturn

P2clk

Clearp2ffs

We must connect 8 zeros to the P2CODE lines to avoid unnecessary warnings



(directly if equal)

(Action 0)

P2SEL

P2add

P2played

4

P2skip

P2CODE8

Lab 10



the input/output relationship

•Must generate the seven outputs for correct operation•The Ppm will stay in state 4 when the machine thinks : both P2played and P2skip are zero

•It stays in state 4 at least one Sysclk period•The selection of inputs depends on the strategy and the implementation

Exam

ple

1Lab 10


Block 6, Machine Play Block Development2. Get the black box view with the inputs

determined and convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations The goal is to develop an intelligent machine player

It gathers information about the current situation Decides how to play

Partition Block 6 into subblocks There are at least two major operations: gather reward

information and decide which position to play Therefore, Block 6 must have at least two subblocks

• Information Gathering SubblockThe information gathering subblock obtains the regular reward points with additions on the four positions and determines the largest regular reward position

• Decision Making Subblock The decision making subblock plays on the largest regular reward position

Exam

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1Lab 10



determined and convert the textual input/output relationship (including the playing strategy) to an operation diagram Partition Block 6 into subblocks

Do we need another major operation ? The information gathering subblock has to obtain the

regular reward points with addition How can we gather and compare the four regular reward

points and then decide ? ► Sequentially !

A sequencing circuit is needed to get the regular reward points for each position one by one !

► A new subblock is needed as the mini sequencer

Exam

ple

1Lab 10



determined and convert the textual input/output relationship (including the playing strategy) to an operation diagram Partition Block 6 into subblocks

The information gathering is done in several steps The machine player goes through steps taking

several clock periods• Another major operation, controlling major operation

is needed • A new subblock, a Sequencing Subblock is needed

Operation diagram is needed to describe what happens in each step• The operation diagram and the controller imply that the

Block 6 is a tiny digital system itself

Exam

ple

1Lab 10


Block 6, Machine Play Block Development2. Get the black box view with the inputs determined and

convert the textual input/output relationship (including the playing strategy) to an operation diagram We have sequential gather and sequential compare

A sequencing circuit is needed to get reward points, compare with the previous largest reward and update the reward The machine player takes several clock periods to make a decision

An operation diagram is needed• Convert the game rules and playing strategy to major operations• Partition Block 6 into subblocks• Block 6 is a tiny digital system itself

To get the operation diagram, check the playing strategy and determine what to do when :

All actions happen in the last state Some actions indicate which data to

collect All conditions indicate what to collect

Exam

ple

1Lab 10



determined and convert the textual input/output relationship (including the playing strategy) to an operation diagram How can we gather and compare the four regular

reward points and then decide sequentially ? The information gathering subblock has to obtain the

regular reward points with direct playing and additions• This is already done in Block 5 !

► Block 5 has the Regular Reward Calculation Subblock which uses

the Adjacency Subblock !► Block 5 receives the digit played

and the position tested from Block 4

Exam

ple

1

Adjacency

Regular RewardCalculation

DO NOT IMPLEMENT THIS INFORMATION GATHERING CIRCUITRY COMBINATIONALLY

Lab 10



convert the textual input/output relationship (including the playing strategy) to an operation diagram There is only one action and no condition The action indicates we have to

Collect regular reward points When the random digit is played with direct playing and addition on the

four displays• Determine which display has the largest regular reward points

Play on the largest regular reward position• Since the information gathering subblock determines which position has

the largest regular reward, decision making subblock is simple ! We can use Block 5 to get the regular reward points for each display

We indicate which position we are testing (collecting the regular reward points of) with direct playing and addition one by one and Block 5 determines the regular reward points for the position tested

Collecting eight regular reward points and comparing them takes eight clock periods

Then, in the next clock period, the ninth one, we decide where to play This strategy requires nine clock periods to play !

Exam

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1



(directly if equal)

(Action 0)

Lab 10



convert the textual input/output relationship (including the playing strategy) to an operation diagram In summary, we have

Eight clock periods of regular reward collection and comparison• By using the output of Block 5 : RWD

One clock period of decision making How do we handle the secondary strategy ?

If two or more displays have the same largest regular reward points, we play on the rightmost of these

If playing directly and with an addition give the same regular reward points, we play directly

If playing directly on a left side position gives the same regular reward points as playing with an addition on the right side, playing directly on the left side is chosen

Do we need separate hardware for this ?• NO as we will see on the next slide !

Exam

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1Lab 10



(directly )(Action 0)



convert the textual input/output relationship (including the playing strategy) to an operation diagram How do we convert the strategy to an operation diagram ?

Write down the steps to play1. Get the regular reward points for position 0 with a direct play2. Get the regular reward points for position 1 with a direct play and

compare with position 0 ► If position 1 has a larger regular reward than position 0, keep it !

3. Get the regular reward points for position 2 a direct play ► If position 2 has a larger regular reward than the previous two positions, keep it !

4. Get the regular reward points for position 3 with a direct play ► If position 3 has a larger regular reward than the previous three positions, keep it !

5. Get the regular reward points for position 0 with an addition ► If position 0 has a larger regular reward than the previous four cases,

keep it !

Exam

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1


Lab 10






convert the textual input/output relationship (including the playing strategy) to an operation diagram How do we convert the strategy to an operation diagram ?

Write down the steps to play6. Get the regular reward points for position 1 with an addition and

compare with position 0 ► If position 1 has a larger regular reward than previous five points, keep it !

7. Get the regular reward points for position 2 with an addition ► If position 2 has a larger regular reward than the previous six points, keep it !

8. Get the regular reward points for position 3 with an addition ► If position 3 has a larger regular reward than the previous seven points, keep it !

9. Play on the position that has the largest regular reward with an addition

Implementing the secondary strategy is done by checking positions • From right to left and • Keeping a position only if its regular reward is greater than those to

the right • Selecting direct playing if it has the same points as playing with an

addition

Exam

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1


Lab 10





Block 6, Machine Play Block Development2. Convert the textual input/output relationship (including the playing strategy) to an operation

diagram


Machine

Player

RWD

8

P2sturn

Clearp2ffs

P2clk

P2add

P2SEL

4

P2played

P2skip

Determine position 0 regular reward with direct playing & record the position number

4

Player 2 plays on a position

Based on the stored information select the position to play

P2s

t0P

2st1 Determine position 1 regular reward with direct playing, keep it if it is larger

& record the position number

P2s

t2P

2st3

Determine position 2 regular reward with direct playing, keep it if it is larger & record the position number

Determine position 3 regular reward with direct playing, keep it if it is larger & record the position number

P2s

t4 Determine position 0 regular reward with an addition, keep it if it is larger & record the position number

P2s


P2s


P2s


P2s

t8

IG

IG

IG

IG

D

IG

IG

IG

IG

Exam

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1

Sequential gather and Sequential compareAn operation diagram is needed

P2sturn = 1 in S4 Lab 10


Block 6, Machine Play Block Development3. Convert the operation diagram to a high-level state diagram

with microoperations with the same number of states How do we get the regular reward points without actually

playing ? How do we test each position without actually playing ?

1. Get the regular reward points for position 0 with a direct play• Indicate to Block 4 and Block 5 that position 0 is tested with a direct

play• P2SEL = 0001 ; P2add = 0 ; P2played = 0 ; P2skip = 0• Store RWD on register LRGRWD & store the position on register POS• LRGRWD RWD ; POS 00001

2. Get the regular reward points for position 1 with a direct play and compare with position 0• Indicate to Block 4 and Block 5 that position 1 is tested with a direct

play• P2SEL = 0010 ; P2add = 0 ; P2played = 0 ; P2skip = 0• If RWD is greater than LRGRWD, then store RWD on LRGRWD & store

the position on POS• If RWD > LRGRWD then LRGRWD RWD ; POS 00010Player 2 spends NINE P2clk periods to think

Exam

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1Lab 10





3. Get the regular reward points for position 2 with a direct play• Indicate to Block 4 and Block 5 that position 2 is tested with a direct

play• P2SEL = 0100 ; P2add = 0 ; P2played = 0 ; P2skip = 0• Store RWD on register LRGRWD & store the position on register POS• LRGRWD RWD ; POS 00100

4. Get the regular reward points for position 3 with a direct play and compare with position 0• Indicate to Block 4 and Block 5 that position 3 is tested with a direct

play• P2SEL = 1000 ; P2add = 0 ; P2played = 0 ; P2skip = 0• If RWD is greater than LRGRWD, then store RWD on LRGRWD & store


Exam

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1Lab 10





5. Get the regular reward points for position 0 with with an addition• Indicate to Block 4 and Block 5 that position 0 is tested with an

addition• P2SEL = 0001 ; P2add = 1 ; P2played = 0 ; P2skip = 0• Store RWD on register LRGRWD & store the position on register POS• LRGRWD RWD ; POS 10001

6. Get the regular reward points for position 1 with an addition and compare with position 0• Indicate to Block 4 and Block 5 that position 1 is tested with an

addition• P2SEL = 0010 ; P2add = 1 ; P2played = 0 ; P2skip = 0• If RWD is greater than LRGRWD, then store RWD on LRGRWD & store


Exam

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1Lab 10





7. Get the regular reward points for position 2 with a direct play• Indicate to Block 4 and Block 5 that position 2 is tested with an

addition• P2SEL = 0100 ; P2add = 1 ; P2played = 0 ; P2skip = 0• Store RWD on register LRGRWD & store the position on register POS• LRGRWD RWD ; POS 10100

8. Get the regular reward points for position 3 with a direct play and compare with position 0• Indicate to Block 4 and Block 5 that position 3 is tested with an

addition• P2SEL = 1000 ; P2add = 1 ; P2played = 0 ; P2skip = 0• If RWD is greater than LRGRWD, then store RWD on LRGRWD & store


Exam

ple

1Lab 10


Block 6, Machine Play Block Development3. Convert the operation diagram to a high-level state diagram with microoperations with the same

number of states


P2SEL = 0001 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; LRGRWD RWD ; POS 00001

4


P2SEL = 0010 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; If RWD > LRGRWD then LRGRWD RWD ; POS 00010

P2SEL = POS[3:0] ; P2add = POS[4] ; P2played =1 ; P2skip = 0

P2s

t0

RTL Notation used

P2s

t1

P2SEL = 0100 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; If RWD > LRGRWD then LRGRWD RWD ; POS 00100P

2st2


2st3


2st4


2st5


2st6


2st7

P2s

t8

Exam

ple

1

Machine

Player

RWD

8

P2sturn

Clearp2ffs

P2clk

P2add

P2SEL

4

P2played

P2skip

Sequential gather and Sequential compareA diagram with finite number of states

Lab 10



number of states


Machine

Player

RWD

8

P2sturn

Clearp2ffs

P2clk

P2add

P2SEL

4

P2played

P2skip

Exam

ple

1

Sequential gather and Sequential compareA diagram with finite number of states

Register ← Source

Wire/bus = Source

RTL Notation

Lab 10



number of states

Exam

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1

P2SEL = 0001

Test position 0

Regular reward points of Position 0

Blo

ck 4

Blo

ck 5

NSD

BR

WD

RWD

Lab 10


Block 6, Machine Play Block Development3. Convert the operation diagram to a high-level state diagram with

microoperations with the same number of states Sequential gather and Sequential compare

A diagram with finite number of states

Exam

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1Lab 10

Test0 is 1 if position 0 is tested : 0001Test1 is 1 if position 1 is tested : 0010Test2 is 1 if position 2 is tested : 0100Test3 is 1 if position 3 is tested : 1000

The control unit generates four Test signals one for each position and a direct/add signal : Test3, Test2, Test1 and Test0 and Testadd

Testadd is 0 the first four clock periodsTestadd is 1 the next four clock periods

How can we generate position selection and direct/add signals ?


Block 6, Machine Play Block Development4. From the high-level state diagram, obtain the datapath

• Sequential gather and Sequential compare• Continue to partition the datapath into subblocks• Design each (sub)block• Implement microperations in datapath hardware

P2skip

Lab 10

A

8-bitComparator

8RWD

8

LRGRWD B

A>B

Gt

8-bitRegister

8RWD

Store

D

CE

P2clk

C

CLRClr

8

LRGRWD

Q

LRGRWDPOS0

POS1

POS2

POS3

P2clk

5-bitRegister

StoreCE

C

CLR

Test0 D0

Test1 D1

Test2 D2

Test3 D3

Q0

Q1

Q2

Q3

Clr

D4TestAdd P2AQ4

POS

DatapathInformationGathering



• Sequential gather and Sequential compare• Continue to partition the datapath into subblocks• Design each (sub)block• Implement microperations in datapath hardware

Lab 10

P2playedPlay

P2skip0

Exam

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1

P2SEL0Test0

P2SEL1Test1

P2SEL2Test2

P2SEL3Test3

POS0

POS1

POS2

POS3

P2A

P2addTestAdd

Datapath

Play

Decision Making

In Information Gathering


Block 6, Machine Play Block Development5. From the high-level state diagram and the datapath, obtain the low-level state

diagram

P2SEL = 0001 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; LRGRWD RWD ; POS 00001

4



P2SEL = POS ; P2add = POS[4] ; P2played =1 ; P2skip = 0

P2s

t0P

2st1


P2s

t2


2st3

P2SEL = 0001 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; If RWD > LRGRWD then LRGRWD RWD ; POS 1 0001

P2s

t4


P2s

t5


P2s

t6


2st7

P2s

t8

Test0 = 1; TestAdd = 0 ; Store = 1

Test1 = 1 ; TestAdd = 0 ; If Gt == 1 then Store = 1

4

Play = 1








P2s

t0

P2s

t1P

2st2

P2s

t3P

2st4

P2s

t5P

2st6

P2s

t7

P2s

t8

Exam

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1Lab 10


Block 6, Machine Play Block Development6. Decide about how to implement the control unit (sequencer)

Sequential gather and Sequential compare Hardwiring or microprogramming ?

• Hardwiring is acceptable if it is not a complex digital system : It is the case with the Ppm term project

RWD8

Control UnitClearp2ffs

P2clk

Test2 Test1ClrStoreGt Test0Test3

P2clk

Play

Eight control signals

One status signal

• Always plays on a position : It does not skip• Plays on the position with the largest regular reward by trying directly or with an addition• If two or more positions have the same reward, plays on the rightmost position

P2sturn

P2add

P2SEL4

P2played

P2skip

TestAdd

Exam

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1

Gather reward points & compare them

Select one ≡ Make a decision

Datapath

Lab 10


Block 6, Machine Play Block Development6. Decide about how to implement the control unit

(sequencer) Sequential gather and Sequential compare

Hardwiring or microprogramming ?• Hardwiring is acceptable if it is not a complex digital system : It is the

case with the Ppm term projectT

est0 = 1; T

estAdd =

0 ; Store =

1

Test1 =

1 ; TestA

dd = 0 ;

If Gt =

= 1 then S

tore = 1

4

Play =

1

Test2 =

1 ; TestA

dd = 0 ;

If Gt =

= 1 then S

tore = 1

Test3 =

1 ; TestA

dd = 0 ;

If Gt =

= 1 then S

tore = 1

Test0 =

1 ; TestA

dd = 1 ;

If Gt =

= 1 then S

tore = 1

Test1 =

1 ; TestA

dd = 1 ;

If Gt =

= 1 then S

tore = 1

Test2 =

1 ; TestA

dd = 1 ;

If Gt =

= 1 then S

tore = 1

Test3 =

1 ; TestA

dd = 1 ;

If Gt =

= 1 then S

tore = 1

Player 2 p

lays on a p

osition

P2st0

P2st1P2st2P2st3P2st4P2st5P2st6P2st7

P2st8

Exam

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1Lab 10


Block 6, Machine Play Block Development7. Implement the sequencer which is treated as a state machine

Sequential gather and Sequential compare Design the hardwired sequencer

Exam

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1

We need a counter (not a register) to keep track of the states

How do we implement the roundrobin trace of the states ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 80 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8

…

A counter + decoder combination is needed to keep track of the states

We need a combination of ► 4-bit Up counter ► 3-to-8 DecoderTo keep track of the current state

Lab 10




Exam

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1

We start counting when it is PPm state 4 (P2sturn =1)

How do we stop counting when we reach state 8 ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8When we reach state 8, P2s8 is 1 since we play in state 8

We count up (enable counting) if we are in Ppm state 4 and P2s8 is 0

How do we know when we have to count up ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8

Counter enable input = P2sturn P2s8

Lab 10




A counter + decoder combination is needed to keep track of the statesE

xam

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1


When it is state 8, P2s8 is 1


Lab 10

4-b

it u

p c

oun

terCE

C

CLR

Q0

Q1

Q2

P2s8

P2sturn

P2clk

Clearp2ffs

P2streg0

P2streg1

P2streg2

A0

E1

P2s

treg

A2

Q3

P2streg3

A1

3-to

-8 D

ecod

er

E0P2sturn

D0

D1

D2

D3

D4

D5

D6

D7

P2s1

P2s2

P2s3

P2s4

P2s5

P2s6

P2s7

P2s0

P2s8





Clearp2ffs is 1 after Player 2 plays

Exam

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1


Lab 10

4-b

it u

p c

oun

terCE

C

CLR

Q0

Q1

Q2

P2s8

P2sturn

P2clk

Clearp2ffs

P2streg0

P2streg1

P2streg2

A0

E1

P2s

treg

A2

Q3

P2streg3

A1

3-to

-8 D

ecod

er

E0P2sturn

D0

D1

D2

D3

D4

D5

D6

D7

P2s1

P2s2

P2s3

P2s4

P2s5

P2s6

P2s7

P2s0

P2s8




Exam

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1 Obtain Expressions

Test0 = P2s0 + P2s4Test0 is 1 when it is state 0 or state 4



Test3 = P2s3 + P2s7Test3 is1 when it is state 3 or state 7

Play = P2s8Play is 1 when it is state 8

Obtain gate networks for the control signals

Lab 10




Exam

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1

Store is 1 when it is • State 0 or • State 1 and Gt is 1 or • State 2 and Gt is 1 or • State 3 and Gt is 1 or• State 4 and Gt is 1 or • State 5 and Gt is 1 or • State 6 and Gt is 1 or• State 7 and Gt is 1

Store is 1 when it is • Not state 8 and

• It is either state 0 or• Gt is 1

Obtain Expressions

Store = P2s8 (P2s0 + Gt)

Obtain gate networks for the control signals

Lab 10




Exam

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1

Store = P2s8 (P2s0 + Gt)

Store is 1 when it is not state 8 and it is either state 0 or Gt is 1

Lab 10

4-b

it u

p c

oun

terCE

C

CLR

Q0

Q1

Q2

P2s8

P2sturn

P2clk

Clearp2ffs

P2streg0

P2streg1

P2streg2

A0

E1

P2s

treg

A2

Q3

P2streg3

A1

3-to

-8 D

ecod

er

E0P2sturn

D0

D1

D2

D3

D4

D5

D6

D7

P2s1

P2s2

P2s3

P2s4

P2s5

P2s6

P2s7

P2s0

P2s8




Exam

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1Lab 10

TestAdd is 1 when it is state 4 or 5 or 6 or state 7

TestAdd = P2s4 + P2s5 + P2s6 + P2s7

TestAdd = P2streg2




Exam

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1

Clr is 1 when Clearp2ffs is 1

Clr = Clearp2ffs

Clearp2ffs is 1 after Player 2 plays

Lab 10


Block 6, Machine Play Block Development7. Implement the sequencer which is treated as a state

machine Sequential gather and Sequential compare Design the hardwired sequencer

Use this counter+decoder circuit if your machine player does not skip and has nine states

Exam

ple

1

Control Unit

Lab 10

Gt

Clr StoreTest0 Test1 Test2 Test3

P2s8Clearp2ffs

P2s0

Play

P2s8

TestAdd

P2streg2

4-b

it u

p c

oun

terCE

C

CLR

Q0

Q1

Q2

P2s8

P2sturn

P2clk

Clearp2ffs

P2streg0

P2streg1

P2streg2

A0

E1

P2s

treg

A2

Q3

P2streg3

A1

3-to

-8 D

ecod

er

E0P2sturn

D0

D1

D2

D3

D4

D5

D6

D7

P2s1

P2s2

P2s3

P2s4

P2s5

P2s6

P2s7

P2s0

P2s8


Block 6, Machine Play Block Development Start implementing the circuits of Block 6 on computer

• Sequential gather and Sequential compare Final digital system design on paper

Datapath

Control Unit

Exam

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1Lab 10



• Sequential gather and Sequential compare Copy the termproject folder and paste it as exp6 Start drawing the schematics by using the design on paper Perform simulations

Exam

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1Lab 10





Exam

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2Lab 10

There is an adjacency ?

N

Play on the(rightmost)largest regular reward position (directly if equal)(Action 0)

Y

Play on the(rightmost)largest adjacency position (directly if equal)(Action 1)

Decision making is more complex !

Block 6? ?





Exam

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2Lab 10

There is an adjacency ?

N

Play on the(rightmost)largest regular reward position (directly if equal)(Action 0)

Y

Play on the(rightmost)largest adjacency position (directly if equal)(Action 1)

Block 6? ?

We know the game rules already !



are fixed and the input/output relationship b) Determine the playing strategy (intelligence)

Always plays (does not skip at all) If there is no adjacency, it plays on the largest regular

reward points position directly or with an addition (chooses direct playing if the two reward points are equal).

Otherwise, it plays on the largest regular adjacency position directly or with an addition (chooses direct playing if adjacencies are equal)

In either case, if two or more positions equally playable, selects the rightmost one

If playing on the left side directly has the same adjacency/regular reward points as playing on the right side with addition, select playing on the left side directly

Exam

ple

2Lab 10


Exam

ple

2



and the input/output relationship c) Determine the inputs

We have to collect eight regular reward points for eight possibilities• Four regular reward points on four displays with direct playing• Four regular reward points on four displays with additions

We have to collect eight adjacencies for eight possibilities• Four adjacencies on four displays with direct playing• Four adjacencies on four displays with additions

We will collect the eight regular reward points and eight adjacencies sequentially• This will take 8 clock periods !

Then, we will play on a position in the ninth clock period

Lab 10





Exam

ple

2

We need to collect the regular reward points : RWD

We will collect eight regular reward points sequentially

We have to input : P2sturn, Clearp2ffs, P2clk Block 6

? ?

We need to collect the adjacencies : NSD

Lab 10





Exam

ple

2

Block 6

RWD8

P2sturn

P2clk

We input RWD, NSDWe input P2sturn, Clearp2ffs, P2clk

Clearp2ffs

?

NSD2

Lab 10





Exam

ple

2

The outputs are fixed !

Block 6

We must connect 8 zeros to the P2CODE lines to avoid unnecessary warnings

P2SEL

P2add

P2played

4

P2skip

P2CODE8

RWD8

P2sturn

P2clk

NSD2

Clearp2ffs

Lab 10



the input/output relationship

•Must generate the seven outputs for correct operation•The Ppm will stay in state 4 when the machine thinks : both P2played and P2skip are zero

•It stays in state 4 at least one Sysclk period•The selection of inputs depends on the strategy and the implementation

Exam

ple

2Lab 10



determined and convert the textual input/output relationship (including the playing strategy) to an operation diagram Sequential gather and Sequential compare

An operation diagram is needed• Convert the playing strategy to major operations• Partition Block 6 into subblocks• Block 6 is a tiny digital system itself The machine player takes several clock periods to make a

decision

To get the operation diagram, check the playing strategy and determine what to do when :

All actions happen in the last state Some actions indicate which data to

collect All conditions indicate what to collect

Exam

ple

2Lab 10


Block 6, Machine Play Block Development

2. Convert the textual input/output relationship (including the playing strategy) to an operation diagram


Determine position 0 regular reward and adjacency with direct playing & record the position number

4


Based on the stored information select the position to play

P2s

t0P

2st1 Determine position 1 regular reward and adjacency with direct playing, keep

each if it is larger & record the position number

P2s

t2P

2st3

Determine position 2 regular reward and adjacency with direct playing, keep each if it is larger & record the position number

Determine position 3 regular reward and adjacency with direct playing, keep each if it is larger & record the position number

P2s

t4 Determine position 0 regular reward and adjacency with an addition, keep each if it is larger & record the position number

P2s


P2s


P2s


P2s

t8

IG

IG

IG

IG

D

IG

IG

IG

IG

Machine

Player

RWD

8

P2sturn

Clearp2ffs

P2clk

P2add

P2SEL

4

P2played

P2skip

NSD 2

Exam

ple

2Lab 10


Block 6, Machine Play Block Development3. Convert the operation

diagram to a high-level state diagram with microoperations with the same number of states


RTL Notation used

Machine

Player

RWD

8

P2sturn

Clearp2ffs

P2clk

P2add

P2SEL

4

P2played

P2skip

NSD 2

Exam

ple

2Lab 10

P2SEL = 0001 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; LRGRWD RWD ; LRGADJ NSD ; POSRWD 00001 ; POSNSD 00001

4


P2SEL = 0010 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; If RWD > LRGRWD then LRGRWD RWD ; POSRWD 00010If NSD > LRGNSD then LRGNSD NSD ; POSNSD 00010

P2played = 1 ; P2skip = 0If LRGNSD >0 then P2SEL = POSNSD[3:0] ; P2add = POSNSD[4] ; else P2SEL = POSRWD[3:0] ; P2add = POSRWD[4]

P2s

t0P

2st1

P2SEL = 0100 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; If RWD > LRGRWD then LRGRWD RWD ; POSRWD 0100If NSD > LRGNSD then LRGNSD NSD ; POSNSD 0100P

2st2

P2SEL = 1000 ; P2played = 0 ; P2skip = 0 ; P2add = 0 ; If RWD > LRGRWD then LRGRWD RWD ; POSRWD 01000If NSD > LRGNSD then LRGNSD NSD ; POSNSD 01000P

2st3


P2s

t4


P2s

t5P2SEL = 0100 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; If RWD > LRGRWD then LRGRWD RWD ; POSRWD 10100If NSD > LRGNSD then LRGNSD NSD ; POSNSD 10100

P2s

t6

P2SEL = 1000 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; If RWD > LRGRWD then LRGRWD RWD ; POS 11000If NSD > LRGNSD then LRGNSD NSD ; POSNSD 11000P

2st7

P2s

t8



Exam

ple

2Lab 10

A

8-b

itC

omp

arat

or

8

RWD

8

LRGRWD

B

A>B

Gtrwd

POSRWD0

POSRWD1

POSRWD2

POSRWD3

P2clk

5-b

itR

egis

ter

Storerwd CE

C

CLR

Test0 D0

Test1 D1

Test2 D2

Test3 D3

Q0

Q1

Q2

Q3

Clr

D4TestAdd

P2AQ4

PO

SR

WD

Datapath

Information Gathering

8-b

itR

egis

ter

8

RWD

Storerwd

D

CE

P2clk C

CLRClr

8

LRGRWD

Q

LR

GR

WD

POSNSD0

POSNSD1

POSNSD2

POSNSD3

P2clk

5-b

itR

egis

ter

Storensd CE

C

CLR

Test0 D0

Test1 D1

Test2 D2

Test3 D3

Q0

Q1

Q2

Q3

Clr

D4TestAdd

P2BQ4

PO

SN

SD

2-b

itR

egis

ter

2

NSD

Storensd

D

CE

P2clk C

CLRClr

2

LRGNSD

QLR

GN

SD

A

2-b

itC

omp

arat

or

2

NSD

2

LRGNSD

B

A>B

Gtnsd

AdjLRGNSD1

LRGNSD0



Decision Making

Exam

ple

2Lab 10

P2SEL0Test0

P2SEL1Test1

P2SEL2Test2

P2SEL3Test3

P2add

P2playedPlay

P2skip0

TestAdd

5-b

it2-

to-1

MU

X

E

A0

B0

A1

B1

Y0

Y1

Y2

Y3

Play

A2

Y4

B2

A3

B3

Sel

A4

B4

POSNSD0

POSNSD1

POSNSD2

POSNSD3

P2B

POSRWD0

POSRWD1

POSRWD2

POSRWD3

P2A

Datapath

Adj



Exam

ple

2Lab 10

Decision Making

Datapath



Block 6, Machine Play Block Development5. From the high-level state diagram and the datapath, obtain the low-level state

diagramTest0 = 1; TestAdd = 0 ; Storerwd = 1 ; Storensd = 1

Test1 = 1 ; TestAdd = 0 ; If Gtrwd == 1 then Storerwd = 1 ;If Gtnsd == 1 then Storensd = 1

4

Play = 1






Test3 = 1 ; TestAdd = 1 ; If Gtrwd == 1 then Storerwd = 1If Gtnsd == 1 then Storensd = 1

Player 2 plays on a positionP

2st0

P2s

t1P

2st2

P2s

t3P

2st4

P2s

t5P

2st6

P2s

t7

P2s

t8

Exam

ple

2Lab 10


Block 6, Machine Play Block Development6. Decide about how to implement the control unit (sequencer)

Sequential gather and Sequential compare Hardwiring or microprogramming ?

• Hardwiring is acceptable if it is not a complex digital system : It is the case with the Ppm term project

RWD

8

Clearp2ffs

P2clk

Test2Test1

ClrStorerwd

Gtrwd Test0Test3

P2clk

Play

Nine control signals

Two status signals

P2sturn

P2add

P2SEL

4

P2played

P2skip

TestAdd

NSD

2

GtnsdStorensd

Control Unit

Datapath

Gather reward points & adjacencies & compare them

Select one based on the adjacency ≡ Make a decision

Exam

ple

2Lab 10


Block 6, Machine Play Block Development6. Decide about how to implement the control unit

(sequencer) Sequential gather and Sequential compare

Hardwiring or microprogramming ?• Hardwiring is acceptable if it is not a complex digital system : It is the

case with the Ppm term projectT

est0 = 1; T

estAdd =

0 ; S

torerwd =

1 ; Storensd =

1

Test1 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

4

Play =

1

Test2 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test3 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test0 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test1 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test2 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test3 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1

If Gtnsd =

= 1 then S

torensd = 1

Player 2 p

lays on a p

osition

P2st0P2st1P2st2P2st3P2st4P2st5P2st6P2st7

P2st8

Exam

ple

2Lab 10





Test0 =

1; TestA

dd = 0 ;

Storerw

d = 1 ; S

torensd = 1

Test1 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

4

Play =

1

Test2 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test3 =

1 ; TestA

dd = 0 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test0 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test1 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test2 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1 ;

If Gtnsd =

= 1 then S

torensd = 1

Test3 =

1 ; TestA

dd = 1 ;

If Gtrw

d ==

1 then Storerw

d = 1

If Gtnsd =

= 1 then S

torensd = 1

Player 2 p

lays on a p

osition

P2st0P2st1P2st2P2st3P2st4P2st5P2st6P2st7

P2st8

Exam

ple

2Lab 10




Use this counter+decoder circuit if your machine player does not skip and has nine states

Exam

ple

2Lab 10

Gtrwd

Clr StorerwdTest0 Test1 Test2 Test3

P2s8

Cle

arp2

ffs

P2s0

Play

P2s8

TestAdd

P2streg2

Gtnsd

Storensd

P2s8

P2s0

4-b

it u

p c

oun

terCE

C

CLR

Q0

Q1

Q2

P2s8

P2sturn

P2clk

Clearp2ffs

P2streg0

P2streg1

P2streg2

A0

E1

P2s

treg

A2

Q3

P2streg3

A1

3-to

-8 D

ecod

er

E0P2sturn

D0

D1

D2

D3

D4

D5

D6

D7

P2s1

P2s2

P2s3

P2s4

P2s5

P2s6

P2s7

P2s0

P2s8



• Sequential gather and Sequential compare Final digital system design on paper

Exam

ple

2Lab 10

Control Unit


Datapath

Decision Making



• Sequential gather and Sequential compare Copy the termproject folder and paste it as exp6 Start drawing the schematics by using the design on paper Perform simulations

Exam

ple

2Lab 10


Analysis of the Term Project Polytechnic Playing Machine, Ppm

The term project is human vs. machine

The black-box view

From page 2 of the Term Project Handout

Figure 1. The Ppm black box view.

Ppm13 19

From the input devices To the output devices

Lab 10


Block 6, Machine Play Block Development Plays as the machine player

On paper1. Start with the black box view where the outputs are fixed and



2. Convert the black box view with the inputs determined and the textual input/output relationship (including the playing strategy) to an operation diagram• Convert the playing strategy to major operations• Partition Block 6 into subblocks• Operation diagram implies the machine player goes through steps

taking several clock periods• The operation diagram also implies that the Block 6 is a tiny digital

system itself

3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states• A diagram with finite number of states• Distribute microoperations to states

Lab 9

/10

Lab 10

How can we implement the block ?


Block 6, Machine Play Block Development On paper

4. From the high-level state diagram, obtain the datapath• Continue to partition the datapath into subblocks• Design each (sub)block• Implement microperations in datapath hardware

5. From the high-level state diagram and the datapath, obtain the low-level state diagram

6. Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming Hardwiring is acceptable if it is not a complex digital system : It

is the case with the Ppm term project

7. Implement the sequencer which is treated as a state machine Design the sequencer

Start moving the circuits of Block 6 to the computer Copy the termproject folder and paste it as exp6 Start drawing the schematics by using the design on paper

Label the components

Lab 9

/10

Lab 1

1-1

3Lab 10



the input/output relationship a) Understand the game rules and how the machine player has to

interact with the rest of the Ppm digital systemb) Determine the playing strategy (intelligence)

• How to determine of the machine player strategy is acceptable ?

At least 3 (three)

different complex conditionsAt least 4 (four)

different complex actions

Lab 9

-10

Lab 10


Block 6, Machine Play Block Development1. Start with the black box view where the outputs are fixed and the

input/output relationship a) Understand the game rules and how the machine player has to interact

with the rest of the Ppm digital systemb) Determine the playing strategy (intelligence)


Lab 9

-10

Lab 10

At least 3 (three) different complex conditions

Player 1 has more points than Player 2 ?

There is an adjacency & RD is not zero ?

There is a position with a 0 & RD is not zero & next RD not equal to RD ?

Player 1 does not have (64)10 or more points & there is a position with a zero and RD is not zero

Player 1 does not have (64)10 or more points & the largest regular reward is less than (64)10

Other complex conditions are possible






Lab 9

-10

Lab 10

At least 4 (four) different complex actions

Play on the (rightmost if equal) largest regular reward position (directly if equal)

Play on the (rightmost if equal) largest adjacency position (directly if equal)

Play on the (rightmost if equal) largest display position with an addition

Play on the(rightmost)zero position directly

Play on the (rightmost if equal) adjacency position that results in the most regular reward points (directly if equal)

Other complex actions are possible



and the input/output relationship b) Determine the playing strategy (intelligence) Non-intelligent machine player strategies

1. Play in a permanently fixed way : always play on the rightmost position which does not have a display overflow. If all positions result in display overflows, skips

2. Play randomly : when it is time to play, stop a freely running 2-bit counter and play on that position

3. Play in a fixed way-round robin fashion : every time it is the turn, increment a 2-bit counter and play on that position

Lab 9

-10

Lab 10

Do not implement these strategies



the input/output relationship b) Determine the playing strategy (intelligence)


Lab 9

-10

Lab 10

If you do not specify the secondary strategy for even a single action, it means the machine player does not work and so you will lose 30 points


Block 6, Machine Play Block Development2. Convert the textual input/output relationship (including

the playing strategy) to an operation diagram Decide about the parallel/sequential implementation issue Get the subblocks Convert the playing strategy to major operations

3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states If sequential gather and Sequential compare+decide is

decided A diagram with finite number of states Distribute microoperations to states

Lab 9

-10

Lab 10



Sequential gather and Sequential compare+decide Design each (sub)block Implement microperations in datapath hardware

5. From the high-level state diagram and the datapath, obtain the low-level state diagram If Sequential gather and Sequential compare+decide is

chosen

6. Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming ? Choose hardwiring

7. Implement the sequencer which is treated as a state machine Design the sequencer Use the 5-state or 9-state counter+decoder combinations

given on previous slides

Lab

9-1

0Lab 10

Make sure the machine player takes at least 9 clock periods to play


Block 6, Machine Play Block Development Move the design to the computer ≡ Implement

Block 6 on computer Plan where to place the subblocks on the screen Delete your Block 6 circuits if they are not needed Start drawing the schematics

First place the components, then their outputs and then their inputs

Label the components Save schematic 6, ppm6.sch

Lab 10La

b 1

1-1

3



Block 6 on computer Start drawing the schematics

Lab 10

Make sure your circuits in Block 6 follow the Term Project Check List handout

DO NOT IMPLEMENT INFORMATION GATHERING CIRCUITRY COMBINATIONALLY

USE available circuits in Blocks 1, 2, 3, 4 and 5

Lab

11

-13




Lab

11

-13

Lab 10

Your machine player would not work completely because of three reasons

It does not follow the game rules

It does not follow your playing strategy

Your playing strategy is not complete



Block 6 on computer Remember also the following

• Follow all the suggestions and warnings, including the timetable !

• Follow the 7-step procedure to design Block 6 !• Start debugging Block 6 starting with the

outputs, proceeding backward• Make sure everybody has everything related to

Block 6 all the time• Do not have black boxes (macros)• Only six schematics in the projects• TAs and I will not answer design related

questions !• Experiment 6 is like an exam : It must be your

work !• No communication with other teams !

Lab 1

1-1

3Lab 10


Block 6, Machine Play Block Development Implementing the machine player, Block 6

Every member of a team must do the schematic design to remember better for the final exam

The timetable for the rest of the semester Students will submit the Experiment 6 project which will

include the implementation of • Block 6

The deadline : 6:50 PM, Friday, May 2, 2014

Lab 10La

b 1

1-1

3

When it is 6:50 on Friday, May 2, 2014We will ask students to stop designing the circuits

Then, we will collect the projects

Submit your Experiment 6 during a lab session !

QUESTIONS ?


DigitalLogic and


Read slides at the end to learn about the software, Project Manager, Schematic design and other related topics

Continue reading the Term Project handout

Think about the machine player strategy

Do not leave the lab before your partners finish► Help your partners

Make sure you have the LABS account and see the S driveMake sure you have installed WebPACK 12.4 on your laptop

Make sure you create a CS2204 folder on both

??

Digital Logic and


Experiment 6

Labs 9, 10, 11, 12, 13

CS CS 22042204CS CS 22042204

Appendices


Lab 11










Lab 11


Developing a new chipTEST : Apply input combinations, test vectors, and simulateDuring testing If you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errorsMount : FPGAs are mounted on bread/boards, wired and programmedTest : apply test vectors to FPGAsModify : either FPGA mounting/wiring is changed or a simple design change is made on computers, simulated, then FPGAs are programmed and testedFabricate chip by sending a GDSII file to a fabrication facility : tape outApply test vectors to the chip

Which components and how many ?

Chip

1) Development Cycle on Computers

DESIGNTESTMODIFY

2) Development Cycle with FPGA chips

MountTestModify

Major error : Redesign or terminate the project due to TTM

3) Development Cycle on prototype chip

FabricateTest


Major error : Redesign

Lab 11


Developing a digital product A new chip

Which gates/FFs and how many is determined by

The application (major operations) Available components of the technology chosen Besides speed, cost, power, etc. : design goals

Lab 11


CS2204 Components Available components for a new chip

Generic componentsLectures, homework, exams

Xilinx components Labs

Gates Flip-flopsPopular digital circuits Gates Flip-flops Popular digital circuits

ANDORNOTNANDNOR…

DJKTSR…

ADDerComparatorMultiplexerDeMuxDecoderEncoderALUCounterRegister…

ANDORNOTNANDNOR…

DTJK


Use these as much as possible

To save time,space, power.weight,… H

igh

-den

sit

y

com

pon

en

ts

Lab 11


Implementing a Combinational Circuit on a New Chip By using generic components that are AND, OR, NOT,…

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a

cy(a, b, c) =y(a, b, c) = a.b + a.ca.b + a.c

1 generic inverter2 generic 2-input AND gates1 generic 2-input OR gate

Total : 4 generic components used

Which generic components ?

Lab 11


Implementing a Combinational Circuit on a New Chip By using generic components that are AND, OR,

NOT

The 2-to-1 MUXUse a generic 2-to-1 MUX already designed

AND

AND

OR

NOTa

b

a


Do not design your own 2-to-1 MUX

Lab 11


Implementing a Combinational Circuit on a New Chip The 2-to-1 MUX

Use a generic 2-to-1 MUX already designed

AND

AND

OR

NOTa

b

a


1 generic 2-to-1 MUX

Total : 1 generic component used


2-to-1MUX

a

bc

y

Sel

0

1

Lab 11



a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

2-bit Unsigned Binary ComparatorFrom Handout 3

ab + ad + ac + c d + bc


2 generic inverters5 generic 2-input AND gates1 generic 5-input OR gate


Output z = 1 if (a,b) > (c, d)

Lab 11



Use a generic comparator already designed

You need an extra NOT gate besides the comparator

2-bit Unsigned Binary Comparator

a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

Do not design your own Comparator

Lab 11


Implementing a Combinational Circuit on a New Chip 2-bit Unsigned Binary Comparator

By using a generic comparator already designed

1 generic 2-bit Unsigned Comparator1 generic NOT gate




a

A1

b

A0

c

B1

d

B0

AGTB AEQB ALTB

z


Lab 11


Implementing a Sequential Circuit on a New Chip By using generic components that are D, J-K, AND, OR,

NOT,… The sequence detector from Handout 17

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0

Least significant FF

J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x


1 generic inverter4 generic 2-input AND gates6 generic 3-input AND gates1 generic 4-input AND gate4 generic 2-input OR gates2 generic 3-input OR gates3 generic positive-edge triggered J-K FFs

Whic

h g

eneri

c co

mponents

?

Try to convert the problem to a problem with registers, counters and shift registers

Lab 11


Implementing a Combinational Circuit on a New Chip By using generic components that are D, J-K, AND, OR,

NOT,…? The sequence detector from Handout 17There is no such generic sequence detector

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

We have to design our own sequence detector

The design with21 components is implemented

But still, try to use registers/counters/shift registers with a few gates

Lab 11


CS2204 Components Available components for a new chip

Generic componentsLectures, homework, exams

Xilinx componentsLabs

Gates Flip-flopsPopular digital circuits Gates Flip-flopsPopular digital circuits

ANDORNOTNANDNOR…

DJKTSR



Lab design

Use Xilinx macros as much as possible

ANDORNOTNANDNOR…

DTJK

Try not to use these components

Hig

h-d

en

sit

y

com

pon

en

ts

Lab 11


Implementing a Combinational Circuit on a New Chip By using Xilinx components that are AND, OR, NOT,…

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a


1 inverter, INV2 2-input AND gates, AND21 2-input OR gate, OR2

Total : 4 Xilinx components used

Which Xilinx components ?

Lab 11


Implementing a Combinational Circuit on a New Chip By using Xilinx components that are AND, OR,

NOT,…

The 2-to-1 MUXXilinx already has 2-to-1 MUXes Use them

AND

AND

OR

NOTa

b

a


Do not design your own 2-to-1 MUX

Lab 11


Implementing a Combinational Circuit on a New Chip The 2-to-1 MUX

Xilinx already has 2-to-1 MUX macros M2_1

AND

AND

OR

NOTa

b

a



1 Xilinx M2_1 MUX

Total : 1 Xilinx component used

Lab 11



a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc



2 inverters, INV5 2-input AND gates, AND21 5-input OR gate, OR5




Lab 11

Experiment 6 Appendices Page 100

CS 2204 Spring 2014


Xilinx already has Comparators Use them

You need an extra NOT gate besides the comparator


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

Do not design your own Comparator

Lab 11


CS 2204 Spring 2014

Implementing a Combinational Circuit on a New Chip 2-bit Unsigned Binary Comparator

By using Xilinx comparators

1 2-bit Comparator, COMPM21 NOT gate, INV




Lab 11


CS 2204 Spring 2014

Implementing a Sequential Circuit on a New Chip By using Xilinx components that are D, J-K, AND, OR, NOT,

… The sequence detector from Handout 17

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x


1 inverter, INV4 2-input AND gates, AND26 3-input AND gates, AND31 4-input AND gate, AND44 2-input OR gates, OR22 3-input OR gates, OR33 positive-edge triggered J-K FFs, FJKC

Whic

h X

ilin

x c

om

ponents

?

Lab 11


CS 2204 Spring 2014

Implementing a Combinational Circuit on a New Chip By using Xilinx components that are D, J-K, AND, OR, NOT,

… The sequence detector from Handout 17Xilinx does not have this sequence detector

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

We have to design our own sequence detector

The design with21 components is implemented

But still, try to use registers/counters/shift registers with a few gates

Lab 11


CS 2204 Spring 2014

Developing a new PCB

1) Development Cycle on Computers

DESIGNTESTMODIFY

During testing if you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors

2) Dev. Cycle with off-the-shelf chips

MountTestModify


Mount : Chips are mounted on bread/boards and wired

TEST : Simulating by applying input combinations, test vectors, may not be possible. It may be coarse grain simulation

Modify : chip mounting/wiring is changed and tested or a simple design change is made on computers, simulated, then chip mounting/wiring is changed and tested

Test : apply test vectors to the chips

3) Dev. Cycle on prototype PCB

FabricateTestModify

Fabricate PCB at a fabrication facility, mount chips and other componentsApply test vectors to the PCB


Modify means chip mounting/wiring is changed and tested

Major error : Redesign

Which chips and how many ?

PCB

Lab 11


CS 2204 Spring 2014

Developing a digital product A new PCB

Which chips and how many is determined by The application (major operations) Available chips of the technology chosen Besides speed, cost, power, etc. : design goals

Lab 11


CS 2204 Spring 2014

CS2204 components Available chips for a new PCB

Generic chipsLectures, homework, examsTTL LS chips

Lectures, homework, exams

Gates Flip-flopsPopular digital circuitsGates Flip-flops Popular digital circuits

ANDORNOTNANDNOR…

DJKTSR…


ANDORNOTNANDNOR…

DJK


Use these as much as possible

To save time,space, power.weight,… H

igh

-den

sit

y

ch

ips

Lab 11

CS2204 components Available chips for a new PCB


CS 2204 Spring 2014

Generic chipsLectures, homework, exams

TTL LS chipsLectures, homework, exams

Gates Flip-flopsPopular digital circuitsGates Flip-flops Popular digital circuits

ANDORNOTNANDNOR…

DJKTSR…


ANDORNOTNANDNOR…

DJK


Use higher density chips (MSI, LSI) as much as possible

Try not to use these SSI chips

Hig

h-d

en

sit

y

ch

ips

MS

I, L

SI

ch

ips

Lab 11


CS 2204 Spring 2014

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A Brief Look

at Semiconductor Technology handout

NAND-Gate Chips

74LS00 4 2-input NAND gates74LS10 3 3-input NAND gates74LS20 2 4-input NAND gates74LS30 1 8-input NAND gate

From ON Semiconductor LS TTL Data Manual

From Texas Instruments Digital Logic Data Book

Try not to use SSI chips

Lab 11


CS 2204 Spring 2014



74LS02 4 2-input NOR gates74LS27 3 3-input NOR gates


NOR-Gate Chips


Lab 11


CS 2204 Spring 2014



74LS04 6 inverters

Inverter-Gate Chips



Lab 11


CS 2204 Spring 2014




74LS08 4 2-input AND gates74LS11 3 3-input AND gates74LS21 2 4-input AND gates

AND-Gate Chips



Lab 11


CS 2204 Spring 2014



74LS32 4 2-input OR gates

OR-Gate Chips



Lab 11


CS 2204 Spring 2014



74LS86 4 2-input EX-OR gates


EX-OR-Gate Chips


Lab 11


CS 2204 Spring 2014

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A

Brief Look at Semiconductor Technology handout

74LS266 4 2-input EX-NOR gates

EX-NOR-Gate Chips



Lab 11


CS 2204 Spring 2014



74LS51 Dual AOI Network


AND-OR-Invert-Gate Chips


Lab 11


CS 2204 Spring 2014

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A Brief Look at

Semiconductor Technology handout

74LS74 2 positive-edge triggered D Fs

D-FF Chips


Try not to use SSI chips Lab 11


CS 2204 Spring 2014



74LS109 2 positive-edge triggered J-K Fs

J-K-FF Chips


From Texas Instruments Digital Logic Data BookK

Lab 11


CS 2204 Spring 2014



74LS112 2 negative-edge triggered J-K Fs

J-K-FF Chips


Try not to use SSI chipsLab 11


CS 2204 Spring 2014

Implementing a Combinational Circuit on a New PCB By using TTL LS SSI chips with AND, OR, NOT,… gates

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a


1 inverter2 2-input AND gates1 2-input OR gate

We need :

1 74LS04 with 6 inverters, 5 inverters unused1 74LS08 with 4 2-input AND gates, 2 gates unused1 74LS32 with 4 2-input OR gates, 3 gates unused

Total : 3 chips used, 10 gates unused

Which TTL components ?

TTL LS SSI Chip Usage ?


Lab 11


CS 2204 Spring 2014


The 2-to-1 MUX

NAND

NAND

a

b

a


4 2-input NAND gatesWe need :

1 74LS00 with 4 2-input NAND gates, 0 gates unused

Total : 1 chip used, 0 gates unused




NAND

NAND

Lab 11


CS 2204 Spring 2014

Implementing a Combinational Circuit on a New PCB The 2-to-1 MUX

Try not to use SSI chips to implement combinational circuits Use higher density chips : 74LS157 TTL LS MSI chip : 4 2-to-1

MUXes• One chip has four 2-to-1 MUXes !


a

b c

y

00 00 0 00

1 74LS157 4-bit 2-to-1 MUX

Total : 1 chip used, 0 gates unused


Lab 11


CS 2204 Spring 2014


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc



2 inverters5 2-input AND gates1 5-input OR gate

We need :

OR

OR

OROR


No TTL chip with 5-input OR gates

Implement it with 4 2-input OR gates



2 inverters5 2-input AND gates4 2-input OR gates

We need :

Lab 11

Experiment 6 AppendicesPage 123CS 2204 Spring 2014


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc



1 74LS04 with 6 inverters, 4 inverters unused2 74LS08 with 4 2-input AND gates, 3 gates unused1 74LS32 with 4 2-input OR gates, 0 gates unused





2 inverters5 2-input AND gates4 2-input OR gates

We need :

Lab 11


CS 2204 Spring 2014

Implementing a Combinational Circuit on a New PCB 2-bit Unsigned Binary Comparator

Try not to use SSI chips to implement combinational circuits Use higher density chips : 74LS85 TTL MSI chip : a 4-bit Unsigned

Binary comparator• We also need a 74LS32 OR-gate SSI chip !• Two chips used !

a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

Lab 11


CS 2204 Spring 2014


Try not to use SSI chips to implement combinational circuits

ab cd00 00

001

1 74LS85 4-bit Unsigned Comparator1 74LS32 with 4 2-input OR gates, 3 gates unused


74LS85 zOR

Lab 11


CS 2204 Spring 2014


Try not to use SSI chips to implement combinational circuits

ab cd00 00

001

1 74LS85 4-bit Unsigned Comparator1 74LS06 with 6 inverters, 5 inverters unused


74LS85z

NOT

Lab 11


CS 2204 Spring 2014

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,…

gates

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

Whic

h c

om

ponents

?


1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 positive-edge triggered J-K FFs

We need :


Lab 11


CS 2204 Spring 2014

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,…

gatesTTL LS SSI Chip Usage ?

Which components ?1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 positive-edge triggered J-K FFs

We need :

There is no positive-edgetriggered J-K FF chip ! We need one more inverter to invert the clock

There is no 3-input OR-gate chip ! We implement it with 2-input OR gates

OR

OR

OR


2 inverters4 2-input AND gates6 3-input AND gates1 4-input AND gate8 2-input OR gates3 negative-edge triggered J-K FFs

We need :

Lab 11


CS 2204 Spring 2014

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,… gates

1 74LS04 with 6 inverters, 4 inverters unused1 74LS08 with 4 2-input AND gates, 0 gates unused2 74LS11 with 3 3-input AND gates, 0 gates unused1 74LS21 with 2 4-input AND gates, 1 gate unused2 74LS32 with 4 2-input OR gates, 0 gates unused2 74LS112 with 2 negative-edge triggered J-K FFs, 1 FF unused

Total : 9 chips used, 5 gates and 1 FF unused


1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 positive-edge triggered J-K FFs

We need : Here there is no choice !We have to use SSI chips !

But still, try to use a register/counter/shift register with a few gates

Lab 11


CS 2204 Spring 2014

Block 6, Machine Play Block Development Plays as the machine player

On paper1. Start with the black box view where the outputs are fixed and



2. Convert the black box view with the inputs determined and the textual input/output relationship (including the playing strategy) to an operation diagram• Convert the playing strategy to major operations• Partition Block 6 into subblocks• Operation diagram implies the machine player goes through steps

taking several clock periods• The operation diagram also implies that the Block 6 is a tiny digital

system itself

3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states• A diagram with finite number of states• Distribute microoperations to states

Lab 9

/10

How can we implement the block ?

Lab 11


CS 2204 Spring 2014

Block 6, Machine Play Block Development On paper

4. From the high-level state diagram, obtain the datapath• Continue to partition the datapath into subblocks• Design each (sub)block• Implement microperations in datapath hardware

5. From the high-level state diagram and the datapath, obtain the low-level state diagram

6. Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming Hardwiring is acceptable if it is not a complex digital system : It

is the case with the Ppm term project

7. Implement the sequencer which is treated as a state machine Design the sequencer

Start moving the circuits of Block 6 to the computer Copy the termproject folder and paste it as exp6 Start drawing the schematics by using the design on paper

Label the components

Lab 9

/10

Lab 1

1-1

3Lab 11


CS 2204 Spring 2014





At least 3 (three)



Lab 9

-10

Lab 11


CS 2204 Spring 2014





Lab 9

-10








Lab 11


CS 2204 Spring 2014





Lab 9

-10








Lab 11


CS 2204 Spring 2014





3. Play in a fixed way - round robin fashion : every time it is the turn, increment a 2-bit counter and play on that position

Lab 9

-10

Lab 11



CS 2204 Spring 2014




Lab 9

-10


Lab 11


CS 2204 Spring 2014





Lab 9

-10

Lab 11


CS 2204 Spring 2014




chosen




Lab

9-1

0


Lab 11


CS 2204 Spring 2014





Lab

11-1

3Lab 11


CS 2204 Spring 2014






Lab

11

-13

Lab 11


CS 2204 Spring 2014



Lab

11

-13 Your machine player would not work completely

because of three reasons




Lab 11


CS 2204 Spring 2014









Lab 1

1-1

3Lab 11


CS 2204 Spring 2014






Lab 1

1-1

3


Then, we will collect the projects

Lab 11

Submit your Experiment 6 during a lab session !

QUESTIONS ?


CS 2204 Spring 2014

DigitalLogic and








??

Digital Logic and


Experiment 6

Labs 9, 10, 11, 12, 13

CS CS 22042204CS CS 22042204

Appendices


Lab 12



CS 2204 Spring 2014








Lab 12


CS 2204 Spring 2014

Silicon Technology Today

f) Today : Multi-chip module, MCM (>1 die on chip), Giga Scale, etc.

(200M–3B transistors)

a)

b)c)

d)

e)

Intel Poulson (Itanium) 8 cores,32 Mbyte L3 Cache3.1 Billion transistors 170 Watts

Will there be an end to shrinking the silicon transistor size ?

Lab 12

Silicon transistors are used as switches


CS 2204 Spring 2014

Digital Hardware Evolution Switches since 1920s

1) Electromechanical : Relays2) Electronic switches

i. Vacuum tubes

4cm x 3cm x 1cm5cm x 1.5 cm

Lab 12


CS 2204 Spring 2014

Digital Hardware Evolution Switches since 1920s2) Electronic switches

ii. Discrete transistors

iii. Integrated circuit transistors : Die contains transistorsTransistor size determined by process lengtha) Small Scale Integration (SSI) (< 64 transistors on chip), 1960s

AND gates (7408), OR gates (7432), NOT gates (7404) chips

b) Medium SI (MSI) (< 2K transistors), 1960s Decoder, encoder, multiplexer, counter chips

c) Large SI (LSI) (< 64K transistors), 1970s Micro-controller, special-function chips (calculator chips), microprocessor chips

d) Very Large SI (VLSI) (< 2M transistors), 1980s Memory, special-function chips, microprocessor chips

e) Ultra Large SI (ULSI) (> 2M transistors), 1990s Memory, microprocessor chips, graphics processor chips, networking chips

1.5 cm x 0.25 cm

Lab 12


CS 2204 Spring 2014


2) Electronic switchesiii. Integrated circuit transistors : Die contains

transistorsf) Today : Multi-chip module, MCM (>1 die on chip), Giga

Scale, etc. (200M–2B transistors) Memory, microprocessor chips The Intel Phi processor : 6 Billion transistors

AMD Tahiti 7970 GPU : 4.313 Billion transistors The Intel Dual-core Itanium processor : 1.72 Billion transistors

Intel Dual-CoreItanium 2 die

Intel dual-core Itanium waferAMD Tahiti 7970 GPU

chip

Lab 12


CS 2204 Spring 2014


f) Today : Multi-chip module, MCM (>1 die on chip), Giga Scale, etc. (200M–2B transistors)

The size of transistors depends on the process length Process length : 22nm

2-input XOR gate

A transistornano size

8 transistors implement 2 bits on SRAM memory

Sun Niagara T2 dieAMD Opteron die IBM Power 6 dieMIPS R10000 die

Lab 12


CS 2204 Spring 2014

Silicon Technology Today

The Intel Xeon E7 10-core die with 2.6 Billion transistors, 32 nm

Intel Xeon E7 wafer

Lab 12

FPGA chips are CMOS

Microprocessor chips are CMOSDRAM chips are CMOS

GPU chips are CMOS


CS 2204 Spring 2014

Semiconductor Technology Today Moore’s Law holds since the 1960s :

Every two years the number of transistors on a chip doubles

Transistors become smaller ≡ Process length becomes smaller

• We have been able to reduce the process length The process is 22nm now

• There are chips with shorter process length now

~3*PL

~5*PL Lab 12

Micron 128Gbit Flash memory die with 64 Billion+

transistors

Samsung 3-D Vertical NAND 128Gbit Flash

EPROM memory with 45 Billion+ transistors

using 19nm process


CS 2204 Spring 2014

Semiconductor Technology Today The transistor size depends on process length

Chips with shorter process length later this year

Xilinx Virtex UltraScale, VU 440 : 20nm (20x10-9 meter)

• A 3-D chip : Multiple dice stacked up containing > 20 Billion transistors

Xilinx Virtex UltraScale : 16nm (16x10-9 meter)

Lab 12

Xilinx VU 440

A 3-D chip with 3-D transistors : FinFet transistors !


CS 2204 Spring 2014


Chips with shorter process length this year Altere Arria 10 FPGA chip : 20nm (20x10-9 meter)

• A 3-D chip with multiple dice stacked up Altera Stratix 10 FPGA chip : 14nm (14x10-9 meter)

Lab 12

A chip with 3-D transistors : Intel FinFet transistors !

Experiment 6 AppendicesPage 156CS 2204 Spring 2014


The densest chips

Lab 12

World’s densest chip 7.1 Billion transistors

NVIDIA TESLA K40 GPU chip

28 nm process

First multi-dimensional chip

World’s 2nd densest chip 6.8 Billion transistors

Xilinx Virtex-7 2000T FPGA chip

28 nm process


CS 2204 Spring 2014

Moore’s Law An observation made by Gordon Moore holding true since

1965 One of the two founders of Intel

Robert Noyce is the other founder

Number of transistors on a chip doubles every two years Because transistors are becoming smaller !

We will continue to shrink size of transistors ! We will continue to double the number of transistors

Lab 12

Transistors are now nano size

IBM Power 78 cores

1.2 Billion transistors

3-D transistors increase the transistor density per chip

3-D chips increase the transistor density per chip


CS 2204 Spring 2014

Silicon Technology and Moore’s Law Number of transistors on chips doubles every two

years Micron Automata Processor : Processor & memory are one

chip ! For high speed search and analysis across massive, complex,

unstructured data Intel Knights landing microprocessor : 2015 !

72 cores !

Lab 12

Micron Automata Processor die

Intel Knights Landing die

3-D chip with DRAM dice stacked up on the processor chip

14 nm process

A 3-D chip with 3-D (FinFet) transistors


CS 2204 Spring 2014


years 3-D chips ?

Monolithic 3-d chips• One die but with layers on top of each other• Many connections between the layers

Die-on-die• Dice stacked up• Less number of connections via Through-Silicon Vias

(TSVs)

Lab 12

Samsung 3-D Vertical 128Gbit Flash EPROM with 24 layers

Xilinx Virtex-7 2000T FPGA

IBM’s conception


CS 2204 Spring 2014


years 3-D chips ?

Hybrid Memory Cube (HMC) !• Multiple dice stacked up• There are logic and memory dice stacked up : Hybrid Micron has 2GByte DRAM chips : 4 stacks of 4 Gbit DRAMs Micron will have 4GByte DRAM chips this year !

Lab 12

TSVs

Samsung model

HMCHybrid memory

Cube

TSVs


CS 2204 Spring 2014

Watt

s/cm

2

1

10

100

1000

1.5m 1m 0.7m 0.5m 0.35m 0.25m 0.18m 0.13m 0.1m 0.07m

i386i486

Pentium®

Pentium® Pro

Pentium® IIPentium® IIIHot plate

RocketRocketNozzleNozzleRocketRocketNozzleNozzle

Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note - 1999. Courtesy :Avi Mendelson, Intel.

Nuclear Reactor

Pentium® 4

Power was doubling every 4 years

Power Density was Increasing Exponentially !

Process Length

Lab 12


CS 2204 Spring 2014

Multi-Core Microprocessors Since 2005 microprocessor speed increase depends on

Number of operations in the code (the quality of the code) Number of parallel operations performed

Multi-core microprocessors with reduced frequency consume less power (generate less heat)

• 2/4/8/16/32/64/128… cores perform operations in parallel The speed increase continues into the future with more cores on chip

Clock frequency

Number of cores per chip doubles every two years The memory can become a bottleneck

The memory speed still increases 10% a year More cores increase the pressure on the memory The memory wall problem

Multiple cores are not used efficiently Parallel Programming must improve

• Major concern now• The parallel Programming wall !

Intel Phi microprocessor 62

cores (2012)

Lab 12


CS 2204 Spring 2014

Multi-Core Microprocessors Intel Phi microprocessor (2012) : 62 cores 1 TFLOPS

1997 : Intel supercomputer with 9298 microprocessors (cores) 1 TFLOPS (1 Tera FLOPS)

1 TFLOPS = 1 x 1012 FLOPS 1,000,000,000,000 floating-point operations a second, FLOPS 1,000,000,000,000 real-number calculations a second

Number of cores per chip likely to double every two years Microprocessor speed is NOT increasing 50% a year any

more ! Microprocessor speed is increasing 30% a year Memory is becoming a bottleneck

• More cores create more pressure on the memory• The memory speed has been increasing 10% a year• Memory wall !

Multiple cores are not used efficiently !• Parallel Programming must improve• Parallel Programming Wall !

Lab 12

A multi-core microprocessorwith 4 cores

L1, L2, L3 Caches

Bu

s

Inte

rface

Core Core CoreCoreMemory(DRAMs) Buses


CS 2204 Spring 2014

Next 8-10 Years

Make sure to handle

errors due toAlpha particles, neutrons

Defective transistors

Parallel programming Wall

Make sure to handle

Memory Wall

DoubleDouble thethe number ofnumber of corescores everyevery twotwo yearsyears

More on future projections next week

Power Wall

Lab 12


CS 2204 Spring 2014


2) Electronic switches

f) Today : Multi-chip module, MCM (>1 die on chip), Giga Scale, etc. (200M–2B transistors)

b)c)

d)

e)

NVIDIA Tesla KEPLER K407.1 Billion

transistors 300 Watts

Lab 12

Will there be an end to shrinking the silicon transistor size ?


CS 2204 Spring 2014

Next 8-10 Years Reconfigurable chips ?

FPGAs are becoming cost competitive with microprocessors FPGAs are becoming speed competitive with custom chips Latest FPGAs also have microprocessor cores to run software

as well FPGAs are now used for applications where speed and

programmability matter

Lab 12

Xilinx Virtex-II Pro XC2VP4 FPGA die

From : Wei Wang, University of Albany

IBM PowerPC 405 core to run software

Hardware programmable areas to perform operations in hardware

Xilinx Virtex-7 H580TFirst 3-D heterogeneous FPGA chip

CMOS chips

FPGA chips are on Mars !


CS 2204 Spring 2014


3) Carbon nanotubes4) Optical switches ?5) Molecular switches ?

Biological ?

6) ??? Life after electronic (silic

on) switches ?

Lab 12

Only carbon nanotube transistors used

From : Nature, September 25, 2013

The first carbon nanotube computer has been built


CS 2204 Spring 2014



Biological ?

6) ???

Life after electronic (silic

on) switches ?

Lab 12


CS 2204 Spring 2014

What are we looking for ? Self-healing, adaptive, self managing,

trustworthy, dependable hardware and software

Efficient parallel processing New computational models New programming languages

Hardware and software reliability

So that we have Many interconnected varying-size computing

elements using each other’s results autonomously

Ubiquitous computing with little human intervention

• Cloud computing to nano computing Personal agents Intelligent spaces• Nano medicine Smart drugs Smart diagnosis

Lab 12


CS 2204 Spring 2014



Biological ?

6) ???

Life after electronic (silic

on) switches ?

To be continued…

Lab 12


CS 2204 Spring 2014

Today’s Xilinx Lab Work Submitting the term project

After drawing the schematics, simulating circuits separately and testing them on the FPGA board, make sure that1) The components are labeled2) The subsubblocks and the subblocks are separated

by lines and labelled3) The circuit is beautified 4) The schematic is saved again5) Functional simulations of the subblocks are done

again6) A Xilinx IMPLEMENTATION is done again7) Downloading to the FPGA board and testing are

done again8) Your experiment 6 folder from the S drive is copied

to your laptop

Lab 12


CS 2204 Spring 2014


After drawing the schematics, simulating circuits separately and testing them on the FPGA board9) Determine whose project will be submitted and

then signal to a TA to submit your project10)Fill out a Term Project Check List Handout11)The team project will be copied by the TA12) Once copied, open the project and download to

the FPGA board to make sure it is copied correctly13) Print all schematics to prepare for the final exam14) If you have any files on the local drive, delete

them

Lab 12


CS 2204 Spring 2014





At least 3 (three)



Lab 9

-10

Lab 12


CS 2204 Spring 2014





Lab 9

-10








Lab 12


CS 2204 Spring 2014





Lab 9

-10








Lab 12


CS 2204 Spring 2014





3. Play in a fixed way - round robin fashion : every time it is the turn, increment a 2-bit counter and play on that position

Lab 9

-10

Lab 12



CS 2204 Spring 2014




Lab 9

-10


Lab 12


CS 2204 Spring 2014





Lab 9

-10

Lab 12


CS 2204 Spring 2014




chosen




Lab

9-1

0


Lab 12


CS 2204 Spring 2014





Lab

11-1

3Lab 12


CS 2204 Spring 2014






Lab

11

-13

Lab 12


CS 2204 Spring 2014



Lab

11






Lab 12


CS 2204 Spring 2014









Lab 1

1-1

3Lab 12


CS 2204 Spring 2014







All members of a team except one will log outThe remaining student will close his/her project and wait

Then, we will collect the project from that project

Lab 12

QUESTIONS ?


CS 2204 Spring 2014

DigitalLogic and








??

Digital Logic and


Experiment 6

Labs 9, 10, 11, 12, 13

CS CS 22042204CS CS 22042204

Appendices


Lab 13



CS 2204 Spring 2014








Lab 13


CS 2204 Spring 2014






When it is 6:50 on Friday, May 2, 2014 We will ask students to stop designing the circuits

All members of a team except one will log outThe remaining student will close his/her project and wait

Then, we will collect the project from that project

Lab 13


CS 2204 Spring 2014



Lab

11






Lab 13


CS 2204 Spring 2014


After drawing the schematics, simulating circuits separately and testing them on the FPGA board, make sure that1) The components are labeled2) The subsubblocks and the subblocks are separated

by lines and labelled3) The circuit is beautified 4) The schematic is saved again5) Functional simulations of the subblocks are done

again6) A Xilinx IMPLEMENTATION is done again7) Downloading to the FPGA board and testing are

done again8) Your experiment 6 folder from the S drive is copied

to your laptop

Lab 13


CS 2204 Spring 2014


After drawing the schematics, simulating circuits separately and testing them on the FPGA board9) Determine whose project will be submitted and

then signal to a TA to submit your project10)Fill out a Term Project Check List Handout11)The team project will be copied by the TA12) Once copied, open the project and download to

the FPGA board to make sure it is copied correctly13) Print all schematics to prepare for the final exam14) If you have any files on the local drive, delete

them

Lab 13


CS 2204 Spring 2014

DigitalLogic and


HAVE A GOOD SUMMER

GOOD LUCK ON YOUR EXAMS

Documents

? Digital Logic and State Machine Design Experiment 6 Labs 9, 10, 11, 12, 13 CS 2204 Appendices Spring 2014 Lab 10