CS 2204 Spring 2008 Digital Logic and State Machine Design Lab 8 Experiment 4 - 5

CS 2204CS 2204

Spring Spring 20082008Spring Spring 20082008

DigitalLogic and

State Machine Design

Lab 8Lab 8

Experiment 4 - Experiment 4 - 55

Lab 8 Experiment 4 - 5

CS 2204 Spring 2008

Page 2

Lab 8 Outline Presentation

Digital product development overview Digital Product Development

• Component selection for a PCB TTL LS SSI chip usage

• Component selection for a chip Xilinx component usage

Analysis of Block 1 of the term project A machine playing strategy Xilinx sequential circuit components

Individual work Experiment 4

Develop the Rightmost Largest Display circuit of the Ppm term project

Experiment 5 Develop the BCD up counter in the Random Digit

Generation Subsubblock of the Ppm term project


CS 2204 Spring 2008

Page 3

Developing a new PCB

1) Development Cycle on Computers

DESIGNTESTMODIFY

During testing if you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors

2) Dev. Cycle with off-the-shelf chips

MountTestModify

Major error : Redesign or terminate the project due to TTM

Mount : Chips are mounted on bread/boards and wired

TEST : Simulating by applying input combinations, test vectors, may not be possible. It may be coarse grain simulation

Modify : chip mounting/wiring is changed and tested or a simple design change is made on computers, simulated, then FPGAs are programmed and tested

Test : apply test vectors to the chips

3) Dev. Cycle on prototype PCB

FabricateTestModify

Fabricate PCB at a fabrication facility, mount chips and other componentsApply test vectors to the PCB


Modify means chip mounting/wiring is changed and tested

Major error : Redesign

Which chips and how many ?

PCB


CS 2204 Spring 2008

Page 4

Developing a digital product A new PCB

Which chips and how many is determined by The application (major operations) Available chips of the technology chosen Besides speed, cost, power, etc. : design goals


CS 2204 Spring 2008

Page 5

CS2204 components Available chips for a new PCB

Generic chipsLectures, homework, exams

TTL LS chipsLectures, homework, exams

Gates Flip-flopsPopular digital circuits Gates Flip-flops Popular digital circuits

ANDORNOTNANDNOR…

DJKTSR…

ADDerComparatorMultiplexerDeMuxDecoderEncoderALUCounterRegister…

ANDORNOTNANDNOR…

DJK


Use these as much as possible

To save time,space, power.weight,… H

igh

-den

sit

y

ch

ips


CS 2204 Spring 2008

Page 6

CS2204 components Available chips for a new PCB

Generic chipsLectures, homework, exams

TTL LS chipsLectures, homework, exams


ANDORNOTNANDNOR…

DJKTSR…


ANDORNOTNANDNOR…

DJK


Use higher density chips as much as possible

Try not to use these SSI chips

Hig

h-d

en

sit

y

ch

ips


CS 2204 Spring 2008

Page 7

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A Brief Look

at Semiconductor Technology handout

NAND-Gate Chips

74LS00 4 2-input NAND gates74LS10 3 3-input NAND gates74LS20 2 4-input NAND gates74LS30 1 8-input NAND gate

From ON Semiconductor LS TTL Data Manual

From Texas Instruments Digital Logic Data Book

Try not to use SSI chips


CS 2204 Spring 2008

Page 8



74LS02 4 2-input NOR gates74LS27 3 3-input NOR gates


NOR-Gate Chips



CS 2204 Spring 2008

Page 9



74LS04 6 inverters

Inverter-Gate Chips




CS 2204 Spring 2008

Page 10



74LS08 4 2-input AND gates74LS11 3 3-input AND gates74LS21 2 4-input AND gates

AND-Gate Chips





CS 2204 Spring 2008

Page 11



74LS32 4 2-input OR gates

OR-Gate Chips




CS 2204 Spring 2008

Page 12



74LS86 4 2-input EX-OR gates


EX-OR-Gate Chips



CS 2204 Spring 2008

Page 13



74LS51 Dual AOI Network


AND-OR-Invert-Gate Chips



CS 2204 Spring 2008

Page 14

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A

Brief Look at Semiconductor Technology handout

74LS266 4 2-input EX-NOR gates

EX-NOR-Gate Chips



CS 2204 Spring 2008

Page 15

TTL LS SSI Chips Used This Semester They have less than 10 gates according to the A Brief Look at

Semiconductor Technology handout

74LS74 2 positive-edge triggered D Fs

D-FF Chips




CS 2204 Spring 2008

Page 16



74LS112 2 negative-edge triggered J-K Fs

J-K-FF Chips



CS 2204 Spring 2008

Page 17

Implementing a Combinational Circuit on a New PCB By using TTL LS SSI chips with AND, OR, NOT,… gates

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a

cy(a, b, c) =y(a, b, c) = a.b + a.ca.b + a.c

1 inverter2 2-input AND gates1 2-input OR gate

We need :

1 74LS04 with 6 inverters, 5 inverters unused1 74LS08 with 4 2-input AND gates, 2 gates unused1 74LS32 with 4 2-input OR gates, 3 gates unused

Total : 3 chips used, 10 gates unused

Which TTL components ?

TTL LS SSI Chip Usage ?



CS 2204 Spring 2008

Page 18

Implementing a Combinational Circuit on a New PCB The 2-to-1 MUX

Try not to use SSI chips to implement combinational circuits Use higher density chips : 74LS157 TTL LS MSI chip : 4 2-to-1

MUXes• One chip has four 2-to-1 MUXes !


a

b c

y

00 00 0 00

1 74LS157 4-bit 2-to-1 MUX

Total : 1 chip used, 0 gates unused



CS 2204 Spring 2008

Page 19


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

2-bit Unsigned Binary ComparatorFrom Handout 5

ab + ad + ac + c d + bc

2 inverters5 2-input AND gates1 5-input OR gate

We need :

OR

OR

OROR


No TTL chip with 5-input OR gates

Implement it with 4 2-input OR gates



2 inverters5 2-input AND gates4 2-input OR gates

We need :


CS 2204 Spring 2008

Page 20


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc


ab + ad + ac + c d + bc

1 74LS04 with 6 inverters, 4 inverters unused2 74LS08 with 4 2-input AND gates, 3 gates unused1 74LS32 with 4 2-input OR gates, 0 gates unused





2 inverters5 2-input AND gates4 2-input OR gates

We need :


CS 2204 Spring 2008

Page 21

Implementing a Combinational Circuit on a New PCB 2-bit Unsigned Binary Comparator

Try not to use SSI chips to implement combinational circuits Use higher density chips : 74LS85 TTL MSI chip : a 4-bit Unsigned

Binary comparator• We also need a 74LS32 OR-gate SSI chip !• Two chips used !

a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc


CS 2204 Spring 2008

Page 22

Implementing a Combinational Circuit on a New PCB 2-bit Unsigned Binary Comparator

Try not to use SSI chips to implement combinational circuits

ab cd00 00

001

1 74LS85 4-bit Unsigned Comparator1 74LS32 with 4 2-input OR gates, 3 gates unused


74LS85z


CS 2204 Spring 2008

Page 23

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,…

gates

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0

Least significant FF

J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

Whic

h c

om

ponents

?


1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 J-K FFs

We need :



CS 2204 Spring 2008

Page 24

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,…

gatesTTL LS SSI Chip Usage ?

Which components ?1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 positive-edge triggered J-K FFs

We need :

There is no positive-edgetriggered J-K FF chip ! We need one more inverter to invert the clock

There is no 3-input OR-gate chip ! We implement it with 2-input OR gates

OR

OR

OR


2 inverters4 2-input AND gates6 3-input AND gates1 4-input AND gate8 2-input OR gates3 negative-edge triggered J-K FFs

We need :


CS 2204 Spring 2008

Page 25

Implementing a Sequential Circuit on a New PCB By using TTL LS SSI chips with D, J-K, AND, OR, NOT,… gates

1 74LS04 with 6 inverters, 4 inverters unused1 74LS08 with 4 2-input AND gates, 0 gates unused2 74LS11 with 3 3-input AND gates, 0 gates unused1 74LS21 with 2 4-input AND gates, 1 gate unused2 74LS32 with 4 2-input OR gates, 0 gates unused2 74LS112 with 2 negative-edge triggered J-K FFs, 1 FF unused

Total : 9 chips used, 5 gates and 1 FF unused


1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 positive-edge triggered J-K FFs

We need :

Here there is no choice !We have to use SSI chips !


CS 2204 Spring 2008

Page 26

Developing a new chip

1) Development Cycle on Computers

DESIGNTESTMODIFY

During testing If you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors

2) Development Cycle with FPGA chips

MountTestModify


Mount : FPGAs are mounted on bread/boards, wired and programmed

TEST : applying input combinations, test vectors, and simulating

Modify : either FPGA mounting/wiring is changed or a simple design change is made on computers, simulated, then FPGAs are programmed and tested

Test : apply test vectors to FPGAs

3) Development Cycle on prototype chip

FabricateTest

Fabricate chip by sending a GDSII file to a fabrication facility : tape outApply test vectors to the chip


Major error : Redesign

Which components and how many ?

Chip


CS 2204 Spring 2008

Page 27

Developing a digital product A new chip

Which gates/FFs and how many is determined by

The application (major operations) Available components of the technology chosen Besides speed, cost, power, etc. : design goals


CS 2204 Spring 2008

Page 28

CS2204 Components Available components for a new chip

Generic componentsLectures, homework, exams

Xilinx components Labs


ANDORNOTNANDNOR…

DJKTSR…


ANDORNOTNANDNOR…

DJK


Use these as much as possible

To save time,space, power.weight,… H

igh

-den

sit

y

cir

cu

its


CS 2204 Spring 2008

Page 29

Implementing a Combinational Circuit on a New Chip By using generic components that are AND, OR, NOT,…

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a


1 inverter2 2-input AND gates1 2-input OR gate

Total : 4 gates used

Which components ?


CS 2204 Spring 2008

Page 30

Implementing a Combinational Circuit on a New Chip By using generic components that are AND, OR, NOT,…a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc


ab + ad + ac + c d + bc Total : 8 gates used

2 inverters5 2-input AND gates1 5-input OR gate

Which components ?


CS 2204 Spring 2008

Page 31

Implementing a Sequential Circuit on a New Chip By using generic components that are D, J-K, AND, OR,

NOT,… The sequence detector from Handout 9

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

Total : 21 components used

1 inverter4 2-input AND gates6 3-input AND gates1 4-input AND gate4 2-input OR gates2 3-input OR gates3 J-K FFs

Whic

h c

om

ponents

?


CS 2204 Spring 2008

Page 32

CS2204 Components Available components for a new chip

Generic componentsLectures, homework, exams

Xilinx componentsLabs

Gates Flip-flopsPopular digital circuitsGates Flip-flopsPopular digital circuits

ANDORNOTNANDNOR…

DJKTSR


ANDORNOTNANDNOR…

DTJK


Lab design

Use Xilinx macros as much as possible

Try not to use these components

Hig

h-d

en

sit

y

ch

ips


CS 2204 Spring 2008

Page 33

Implementing a Combinational Circuit on a New Chip By using Xilinx components that are AND, OR, NOT,…

The 2-to-1 MUX

AND

AND

OR

NOTa

b

a


1 inverter, INV2 2-input AND gates, AND21 2-input OR gate, OR2

Total : 4 gates used

Which Xilinx components ?


CS 2204 Spring 2008

Page 34

Implementing a Combinational Circuit on a New Chip By using Xilinx components that are AND, OR,

NOT,… The 2-to-1 MUX

Xilinx already has 2-to-1 MUXes Use them

AND

AND

OR

NOTa

b

a


Do not design your own 2-to-1 MUX


CS 2204 Spring 2008

Page 35

Implementing a Combinational Circuit on a New Chip The 2-to-1 MUX

Xilinx already has 2-to-1 MUX macros M2_1

AND

AND

OR

NOTa

b

a


1 Xilinx M2_1 MUX

Total : 1 component used



CS 2204 Spring 2008

Page 36


a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

ab + ad + ac + c d + bc Total : 8 gates used

2 inverters, INV5 2-input AND gates, AND21 5-input OR gate, OR2




CS 2204 Spring 2008

Page 37


Xilinx already has Comparators Use them

You need an extra OR gate besides the comparator

2-bit Unsigned Binary Comparator

a

b

d

a

ca

c

d

z

bc

d

c

ab

ad

ac

c d

bc

Do not design your own Comparator


CS 2204 Spring 2008

Page 38

Implementing a Combinational Circuit on a New Chip 2-bit Unsigned Binary Comparator

By using Xilinx comparators

1 Xilinx 74_L85 Comparator, X74_L851 Xilinx 2-input OR gate, OR2




CS 2204 Spring 2008

Page 39

Implementing a Sequential Circuit on a New Chip By using Xilinx components that are D, J-K, AND, OR, NOT,

… The sequence detector from Handout 9

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x


1 inverter, INV4 2-input AND gates, AND26 3-input AND gates, AND31 4-input AND gate, AND44 2-input OR gates, OR22 3-input OR gates, OR33 positive-edge triggered J-K FFs, FJKC

Whic

h c

om

ponents

?


CS 2204 Spring 2008

Page 40

Implementing a Combinational Circuit on a New Chip By using Xilinx components that are D, J-K, AND, OR, NOT,

… The sequence detector from Handout 9Xilinx does not have this sequence detector

J

K C

Q

Q

y2

y1

xy0

y1y

0

clock

most significant FF

J

K C

Q

Q

xy2

y2y1

y2y1clock

x

x

y0


J

K C

Q

Q

y2

xy0

xy

0

xy

2y0x

y2y

0

clock

y1

y2y1

y2y0

y2y1

y0

z

x

x

x

We have to design our own sequence detector

The design with21 components is implemented


CS 2204 Spring 2008

Page 41

Analysis of the Term Project The term project black-box view The term project operation diagram The term project black box partitioning


CS 2204 Spring 2008

Page 42

The Term Project, Ppm The black-box view

Ppm is sequential (not combinational) A large number of FFs are used !

Ppm is a digital system We need to partition the Ppm based on major operations

• We have to obtain the operation diagram

From page 2 of the Term Project Handout

Figure 1. The Ppm black box view.

Ppm13 19

From the input devices To the output devices


CS 2204 Spring 2008

Page 43

PpmInput/outputrelationship

Ppmoperationdiagram

Fro

m p

ag

e 8

of

the T

erm

Pro

ject

Han

dou

t

LD6-LD8 on the FPGA board show the current state


CS 2204 Spring 2008

Page 44

The Ppm Term Project Ppm is a digital system !

The Ppm term project partitioning First partitioning of the digital system

Control Unit Data Unit

Second partitioning (Data Unit partitioning) Interfacing to the input/output devices Handling human player’s play Controlling display operations based on game rules Calculating new player points Determining the machine player play

core

corecore

corecore

non-core

Figure 1. The Ppm black box view.

Ppm10 19

From the input devices To the output devices


CS 2204 Spring 2008

Page 45

The Ppm Digital System Partitioning

M1M2

From page 9 of the Term Project Handout


CS 2204 Spring 2008

Page 46

The term project black box partitioning• Six schematics for six blocks

• Block 1 : Control Unit : ppm1.sch schematic file• Block 2 : Input/Output : ppm2.sch schematic file• Block 3 : Human Play : ppm3.sch schematic file• Block 4 : Play Check : ppm4.sch schematic file

• Experiment 1 is on a circuit in this block

• Block 5 : Points Calculation : ppm5.sch schematic file

• Block 6 : Machine Play : ppm6.sch schematic file• The Machine Play Block uses all other blocks except the

Human Play Block


CS 2204 Spring 2008

Page 47

Digital Systems A digital system performs microoperations A digital system consists of digital circuits

A digital system consists of A data unit (datapath)

It performs microoperations

A control unit It controls the datapath


CS 2204 Spring 2008

Page 48

Digital Systems This first partitioning of a digital system is

universal

A microprocessor is a digital system An iPhone is a digital system A computer is a collection of digital systems

control signalsstatus signals

Sequencer

Registers ALUs buses Data Unit

Control Unit

Figure 7. A large scale view of a digital system.

Other digital systems/Input/Output devices (Datapath)


CS 2204 Spring 2008

Page 49

Digital Systems The data unit has registers, ALUs and

buses to perform microoperationsRegisters keep (store) data (operands and

results)Arithmetic Logic Units (ALUs) perform

additions, subtractions, multiplications, ANDS, ORs, etc.

Buses interconnect registers and ALUs


CS 2204 Spring 2008

Page 50

Digital Systems The Control Unit (Sequencer)

The control unit determines the sequence of microoperations based on the status signals

The control unit goes through states• In each state, it enables the microoperations of that

state to happen in the data unit based on the status signals ► Microoperations must start at the right time with correct inputs and end at the right time with correct outputs

We should not lose data and we should not use old data

► Glitches, gate delays must be accounted for When we design it, we account for every possible gate delay


CS 2204 Spring 2008

Page 51

Digital Systems The Control Unit (Sequencer)

The state register indicates the current state Logic to generate the control signals and the next state

more irregular than the Data Unit


CS 2204 Spring 2008

Page 52

Digital Systems The Control Unit (Sequencer) design

Hardwiring vs microprogramming

Gate/FF networks = random logic = irregular

Highlyregularbut slower

Memory bits generate control signals and NS

Not as regularas the datapath


CS 2204 Spring 2008

Page 53

Digital Systems The Control Unit (Sequencer) design

First partitioning on the Control Unit Control Signal generation Subblock Next State Generation Subblock

Often a counter is used instead of a register since we trace the states sequentially

Often a decoder is used to generate the control and next state signals


CS 2204 Spring 2008

Page 54

The Ppm Control Unit Block 1, the Control Unit (the sequencer)

It controls the Data Unit It determines the sequence of microoperations

Which microoperation happens when

Block 116 18

How can we implement the block ?


CS 2204 Spring 2008

Page 55


The control unit determines the sequence of microoperations based on the status signals Implemented by using the FSM technique Uses hardwiring

• Gate networks generate control signals Partitioned into

• Control Signal generation Subblock • Next State Generation Subblock


CS 2204 Spring 2008

Page 56


ControlSignalGenerationSubblock

Counter-Decodercombinationto keep trackof the currentstate

Controlsignals

NextStateGenerationSubblock


CS 2204 Spring 2008

Page 57

A Machine Player Strategy

N Y

Largest reward = 0 ?

Skip

Play on the (rightmost)largestreward

if equal)(directlyposition

Player 1 does not have (64)10 or morepoints & there is a position with a zero

Y

Play on the

directlyzero position (rightmost)

(if equal)

N

& RD is not zero

Player 1 does not have (64)10 or morepoints & the largest reward is less than (64)10

N

(Action 0)

(Action 2)Play on the (rightmost)largest


(Action 1)

Y


CS 2204 Spring 2008

Page 58

A Machine Player Strategy Its Implementation

N Y

Largest reward = 0 ?

Skip

Play on the (rightmost)largestreward


Player 1 does not have (64)10 or morepoints & there is a position with a zero

Y

Play on the

directlyzero position (rightmost)

(if equal)

N

& RD is not zero

Player 1 does not have (64)10 or morepoints & the largest reward is less than (64)10

N

(Action 0)

(Action 2)Play on the (rightmost)largest


(Action 1)

Y


CS 2204 Spring 2008

Page 59

Xilinx FFs, Registers, Counters Many do not have direct set and direct

clear inputs togetherTo avoid cases where both are active

They have either A direct set input

OrA direct clear input


CS 2204 Spring 2008

Page 60

Xilinx FFs, Registers, Counters Direct set and direct clear inputs

Asynchronous As we studied in class

• If the direct input is active, it affects the output immediately The name of the FF, register, counter has a

• “C” near the end if it is the direct clear input ► FDC : a D FF with an asynchronous direct clear input

• “P” near the end if it is the direct set (preset) input

► FDP : a D FF with an asynchronous direct set input


CS 2204 Spring 2008

Page 61

Xilinx FFs, Registers, Counters Direct set and direct clear inputs

Synchronous If the direct input is active, it affect the output when there

is the active clock edge The name of the FF, register, counter has an

• “R” near the end if it is the direct clear input ► FDR : a D FF with a synchronous direct clear input

• “S” near the end if it is the direct clear input

► FDS : a D FF with a synchronous set input


CS 2204 Spring 2008

Page 62

Xilinx FFs, Registers, Counters Some of them have an additional input

Clock Enable (CE) The name of the FF, register, counter ends with an

“E” It controls the clock input

• If it is 1, the clock input gets the clock signal► It can be clocked (stored)

• If it is 0, the clock input gets 0► It cannot be clocked (cannot be

stored)

FDCE : A D FF with an asynchronous direct clear input and a clock enable input


CS 2204 Spring 2008

Page 63

Xilinx FFs, Registers, Counters Clock Enable (CE)

FDCE : A D FF with an asynchronous direct clear input and a clock enable input

CLR CE D C Q1 X X X 0 (Store 0)0 1 0 0 (Store 0)

0 1 1 1 (Store 1)

0 1 X 0 NS0 0 X X NS


CS 2204 Spring 2008

Page 64

Xilinx FFs, Registers, Counters Clock Enable (CE)

The clock enable is often connected the “Store” signal

a

Storey0

Clock

Reset

y0D

C

CLR

Qa

Reset

y0

CE is equivalent to

Storey0

Clock


CS 2204 Spring 2008

Page 65

Q/A

Do not leave the lab before your partners finish► Help your partners complete today’s project

Continue reading the Term Project handout

Think about the machine player strategy

Read slides starting at the end on term project, Project Manager, schematic design and other related topics


CS 2204 Spring 2008

Page 66

Today’s Individual Xilinx Work We will continue to study (analyze) the term

project We will use discussions in class Lab 7 notes to implement

Macro 2 (M2) of Block 6 : Experiment 4 We will use our knowledge of counters to modify a portion

of a term project schematic We will replace a 4-bit Xilinx BCD up counter (Divide-by-10

or Modulo-10 counter) with our own circuits : Experiment 5

Help your partners complete today’s project We will continue reading the Term Project handout

Relate each term project (sub)block in the Term Project handout to the Ppm schematic

Study Ppm (sub)blocks by performing simulations

Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics


CS 2204 Spring 2008

Page 67

Today’s Individual Xilinx Lab Work1. Copy the exp3 folder and paste it in the

cs2204 folder as the exp4 folder We will experiment with the Ppm schematics

2. Open the Ppm project in exp43. Look at the six Ppm schematics

If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project

Therefore, close all these schematics and close the schematics window

Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side

4. Place your team info on the schematics on schematic 1 : ppm1.sch


CS 2204 Spring 2008

Page 68

Today’s Individual Xilinx Lab Work5. Save schematic 16. Switch to schematic 67. Zoom into the lower right area,

containing M28. There is a custom macro designed by

the professor It has two outputs that indicate the number

of the rightmost largest display position See ppm6.sch on the next slide


CS 2204 Spring 2008

Page 69

Today’s Individual Xilinx Lab Work Ppm Schematic 6

Macro 2M2


CS 2204 Spring 2008

Page 70

Today’s Individual Xilinx Lab Work9. Analyze the macro to determine how it is

used See the correspondence between the classroom

discussion and M2 inputs and outputs Determine which inputs are for display 0, which inputs

are for display 1, etc. Determine which output is “Y1” and which output is

“Y0” Do a Hierarchy Push and notice that its

implementation cannot be shown by Xilinx A comment on the bottom of the schematic sheet

reads “Symbol is a primitive cell”

10.Perform functional simulations on this macro

Use also your notes that cover the discussion in the classroom


CS 2204 Spring 2008

Page 71

Today’s Individual Xilinx Lab Work11.Search for the inputs and outputs of the

macro by clicking on the Query window button on top of the schematic sheet

In the Signal/Bus mode of the SC Query/Find window that will pop up

Determine which components generate the inputs DISP0, DISP1, DISP2, DISP3,…, DISP15

Determine which components use outputs LRGDISPPOS1 and LRGDISPPOS0

12.Delete the macro : M2 in schematic 6 Do not delete the wires Save schematic 6, ppm6.sch

See modified ppm6.sch on the next slide


CS 2204 Spring 2008

Page 72


Macro 2, M2deleted


CS 2204 Spring 2008

Page 73

Today’s Individual Xilinx Lab Work13. Switch to the Human Play Block, Block 3 or ppm3.sch14. Draw the schematic of the macro on the lower right side in

schematic 3 by using classroom and Lab 7 discussions and your design

You will implement the LRGDISPPOS1 and LRGDISPPOS0 outputs by using as many Xilinx design blocks as possible and as few gates as possible Note that what is discussed in the presentation must be followd where we

try to use as many available components as possible M2 uses three Xilinx comparators, two Xilinx multiplexers and a few

gates Note that what is learned in designing M1 can be used for M2

You will use the Symbols toolbox button on the leftmost side (or F3) to get the component list

You will use the Draw wires button on the leftmost side (or F4) to draw wires

To rotate components right press ctrl-r To rotate components left, press ctrl-l Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated ! Label the wires (inputs and outputs) based on your analysis in part

(9) Label the gates starting at U324


CS 2204 Spring 2008

Page 74

Today’s Individual Xilinx Lab Work14.Draw the schematic of the macro on the

lower right side in schematic 3 by using classroom discussions and your design

In the Instance mode of the SC Query/Find window that will pop up

Determine that there is no component labeled U324 and aboveLabel the components starting at U324Save schematic 6, ppm6.sch


CS 2204 Spring 2008

Page 75

Today’s Individual Xilinx Lab Work15.Perform an Integrity Test to check for

errors Integrity tests do not catch all the errors

That is why after the Integrity tests we have to perform• Functional simulations• Xilinx IMPLEMENTATIONs• Timing simulations

16.Perform functional simulations on this macro in schematic 3 to verify that it is working

Use the truth table you have developed to test a portion of M2Make sure the circuit is beautified and the schematic is saved again


CS 2204 Spring 2008

Page 76

Today’s Individual Xilinx Lab Work17.Do a Xilinx IMPLEMENTATION

Make sure there are no errors Make sure the IMPLEMENTATION options are

changed so that a better IMPLEMENTATION is done Read the Implementation Log File to confirm

that The number of warnings 26

• These warning are OK, we can continue• Note that there are 26 warnings not 25 as it

was the case in the previous experiment since a wire in Block 5 is not used

• This wire is the wire that connected the unused data inputs of the Xilinx 4-bit ADDer to GND in Block 5

WARNING:NgdBuild:454 - logical net '$Net00202_' has no load


CS 2204 Spring 2008

Page 77

Today’s Individual Xilinx Lab Work17.Do a Xilinx IMPLEMENTATION

Read the Implementation Log File to see that The FPGA chip utilization is 98%

• The Xilinx IMPLEMENTATION maps the design to 191 to 193 CLBs, hence 97% to 98% utilization, after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass

produce it to test the design one more time to make sure the design is correct Nevertheless, the utilization is high since two gate networks implement a full adder and this implementation is worse than the Xilinx implementation That is why it is better that we use Xilinx components if they are available


CS 2204 Spring 2008

Page 78

Today’s Individual Xilinx Lab Work

17. Do a Xilinx IMPLEMENTATION The Project Manager window looks like this after the

IMPLEMENTATION is completed successfully :

The checkmark forIMPLEMENTATIONcan be delayed a few minutes sometimes

Make sure the options for IMPLEMENTATION are “High Effort” “50” and “5”


CS 2204 Spring 2008

Page 79

Today’s Individual Xilinx Lab Work18.Do you think there is a possibility of a

glitch by the full adder circuit ? If yes, which output(s) would have the

glitch ? Which input combination pairs would

generate the glitch ? Observe the glitch and show it to the TA

19.Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 3 and correct your circuit


CS 2204 Spring 2008

Page 80

Today’s Individual Xilinx Lab Work1. Copy the termproject folder and paste it in

the cs2204 folder as the exp5 folder We will experiment with the Ppm schematics

2. Open the Ppm project in exp53. Look at the six Ppm schematics

If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project

Therefore, close all these schematics and close the schematics window

Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side

4. Place your team info on the schematics on schematic 1 : ppm1.sch


CS 2204 Spring 2008

Page 81

Today’s Individual Xilinx Lab Work5. Save schematic 16. Switch to schematic 47. Zoom into the upper right area, containing the

Random Digit Generation Subsubblock8. There is a Xilinx macro (a Xilinx Design Block,

XDB) with U117 A BCD Up Counter, CD4CE, in the subsubblock

It counts up 0 to 9, inclusive• Its clock is always enabled (CE = 1)• Its direct clear input is always inactive (CLR = 0)

It implements the BCD Up counter similar to the modulo-12 counter implemented in class• We used a TTL LS chip : 74LS169

See ppm4.sch on the next slide See the subsubblock in more detail on the slide that

follows


CS 2204 Spring 2008

Page 82


Xilinx BCD UpCounter


CS 2204 Spring 2008

Page 83


Xilinx BCDUp Counter

Xilinx 4-bit registers which are stored 3 random digits when Grd (Get RandomDigit) is raised to1 by the controlunit when BTN1or BTN2 is pressed

RDP1RDP2RD


CS 2204 Spring 2008

Page 84

Today’s Individual Xilinx Lab Work9. Analyze the BCD up counter to determine how

its inputs and outputs are used It counts up at the rate of Rdclk (Random digit clock)

Rdclk is generated in the Timing Subblock of schematic 2 It is derived from Q0 which is one of the outputs of a

16-bit Xilinx binary counter, CB16CE, U64 Q0 has the frequency of 192 Hz

Three outputs of the counter are stored on a Xilinx 4-bit register The counter value is stored as the random digit when

Grd (Get random digit) is 1 The rightmost output of the counter is not stored on

the register ! If this output is connected to the register, the

random digit is always odd (1, 3, 5, 7 and 9) It is a problem of the Xilinx software and so to get

around it the register is connected Q7 from U64 in schematic 2


CS 2204 Spring 2008

Page 85

Today’s Individual Xilinx Lab Work9. Analyze the BCD up counter to

determine how its inputs and outputs are used

See the correspondence between this circuit and your class notes The Xilinx counter is an Up counter and so does not

have the U/D input Its internal design is for BCD counting and so no

external gate is needed• Do a Hierarchy Push and see how it is

implemented by Xilinx• Do a Hierarchy Pop to close the internal circuit

schematic


CS 2204 Spring 2008

Page 86

Today’s Individual Xilinx Lab Work10.Perform functional simulations on the

Xilinx BCD counter In order to simulate, we need to name the

outputs of the Xilinx counter Output Q0 does not have a wire connected

• Connect a short wire to the output and name it RDC0 where RDC stands for “Random Digit Counter”

Name the other three output as RDC1, RDC2 and RDC3

See the next slide for the outputs of the counter


CS 2204 Spring 2008

Page 87



CS 2204 Spring 2008

Page 88

Today’s Individual Xilinx Lab Work10.Perform functional simulations on the

Xilinx BCD counter When you do the simulations

See slide 129 to learn how to supply the periodic clock signal

You can start with any initial value (initial count), since it is a counter,

Apply at least 13-14 clock cycles to observe the outputs so that they cycle around

See the next slide that shows the simulation for 14 clock periods


CS 2204 Spring 2008

Page 89

Today’s Individual Xilinx Lab Work The simulation window for the Xilinx BCD

Counter


CS 2204 Spring 2008

Page 90

Today’s Individual Xilinx Lab Work11. Search for the inputs and outputs of the

Counter by clicking on the Query window button on top of the schematic sheet to confirm your findings in part (9)

In the Signal/Bus mode of the SC Query/Find window that will pop up

Determine the component that generates the input Rdclk

Determine the components that use outputs RDC1, RDC2 and RDC3

12. Delete the Xilinx BCD Up Counter in schematic 4

Do not delete the wires Save schematic 4, ppm4.sch

See modified ppm4.sch on the next slide


CS 2204 Spring 2008

Page 91


XilinxBCD Counterdeleted


CS 2204 Spring 2008

Page 92

Today’s Individual Xilinx Lab Work13. Switch to the Human Play Block, Block 3 or

ppm3.sch14. Draw the gate network of the BCD Up Counter

by using your class notes in the upper mid area in schematic 3

On paper, design the circuit by using your class notes You will use a NAND gate to detect number 9 in Unsigned

binary (1001)• In class, number 12 in Unsigned Binary (1100) is detected

You will load (0000) to the counter• In class, we loaded (0001) to the counter

Xilinx does not have the equivalent of the 74LS169 chip used in class• Use, the closest one, X74_161 which is equivalent to the TTL

74LS161 4-bit Up counter chip ► It is an Up Counter and so does not have the U/D input ► It has an extra input : asynchronous direct clear It is not needed and so connect 1 permanently ► Its ENP and ENT inputs allow counting up They are not needed and so connect 1 to them permanently


CS 2204 Spring 2008

Page 93

Today’s Individual Xilinx Lab Work14. Draw the gate network of the BCD Up Counter

by using your class notes in the upper mid area in schematic 3

After the paper design is complete, move the design to the computer Place the components on the screen based on your paper

design Wire the components based on your paper design Label the wires (inputs and outputs)

• Name the components of the BCD Up Counter from left to right and top to bottom starting at U332

► The last component label is U333

Save schematic 3, ppm3.sch See modified ppm3.sch on the next two slides

First the BCD counter circuit Then, the modified ppm3.sch


CS 2204 Spring 2008

Page 94

Today’s Individual Xilinx Lab Work The BCD counter circuit in ppm3.sch

BCD Up Counter


CS 2204 Spring 2008

Page 95


BCD Up Counter


CS 2204 Spring 2008

Page 96

Today’s Individual Xilinx Lab Work15. Perform an integrity test to check for errors

Integrity tests do not catch all the errors That is why after the Integrity tests we have to perform

• Functional simulations• Xilinx IMPLEMENTATIONs• Timing simulations

16. Perform functional simulations on this BCD Up Counter in schematic 3 to verify that it is working

See slide 129 about supplying the periodic clock signal Make sure the circuit is beautified and the schematic

is saved again


CS 2204 Spring 2008

Page 97

Today’s Individual Xilinx Lab Work17. Do a Xilinx IMPLEMENTATION

Make sure there are no errors Make sure the IMPLEMENTATION options are changed so

that a better IMPLEMENTATION is done Read the Implementation Log File to confirm that

The number of warnings 26• These warning are OK, we can continue• Note that there are 26 warnings not 24 as it is the

case with the term project since two wires in Block 4 are not used

• These wires are the wires that connected the CE and CLR inputs of the Xilinx BCD counter to VCC and GND in Block 4, respectively

WARNING:NgdBuild:454 - logical net '$Net00619_' has no loadWARNING:NgdBuild:454 - logical net '$Net00620_' has no load


CS 2204 Spring 2008

Page 98

Today’s Individual Xilinx Lab Work17. Do a Xilinx IMPLEMENTATION

Read the Implementation Log File to see that The FPGA chip utilization is 97%

• The Xilinx IMPLEMENTATION maps the design to 190 to 191 CLBs, hence 96% to 97% utilization, after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass

produce it to test the design one more time to make sure the design is correct Nevertheless, the utilization is high since two gate networks implement a full adder and this implementation is worse than the Xilinx implementation That is why it is better that we use Xilinx components if they are available


CS 2204 Spring 2008

Page 99

Today’s Individual Xilinx Lab Work

17. Do a Xilinx IMPLEMENTATION The Project Manager window looks like this after the

IMPLEMENTATION is completed successfully :

The checkmark forIMPLEMENTATIONcan be delayed a few minutes sometimes

Make sure the options for IMPLEMENTATION are “High Effort” “50” and “5”


CS 2204 Spring 2008

Page 100

Today’s Individual Xilinx Lab Work18. Do you think there is a possibility of a glitch ?

If yes, which output(s) would have the glitch ? Which input combination pairs would generate the

glitch ? Observe the glitch and show it to the TA

19. Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 3 and correct your circuit


CS 2204 Spring 2008

Page 101

Today’s Individual Xilinx Lab Work20. Help your partners complete today’s project

21. Continue reading the Term Project handout Relate each term project (sub)block in the Term

Project handout to the Ppm schematic Study Ppm (sub)blocks by performing simulations

Play the other two versions of the term project to refresh your memory• Ppm human vs. human : ppmhvsh• Ppm machine vs. machine : ppmmvsm

22. Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics


CS 2204 Spring 2008

Page 102

Understand Critical WiresRD : 4 bits

The random digitR1D : 4 bits

Next random digitR2D : 4 bits

The random digit after next random digitP1add, TRD : 4 bits

Altogether they form a random digit manually input to the machine player to test it

In order to input it, one of SW1 – SW4 must be 1

DISP : 16 bits They represent the four position displays

In Hex DISP15-DISP12 : the leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc

TDISP : 16 bitsNext display bits after the current random digit is played

SELTPD : 4 bitsSelects between DISP and TDISP to add the current or next random digit

If it is 0, it selects DISP, otherwise TDISP


CS 2204 Spring 2008

Page 103

Understand Critical WiresTADDDISP : 16 bits

The result of selection between DISP and TDISPNPDISP : 16 bits

TADDDISP digits plus RDNDISP : 16 bits

New DISP bits In Hex

BRWD : 4 bits Basic reward

In Hex The digit played and also minimum points earned

Brwdeqz : 1 bit BRWD is zero when it is 1

PDPRD : 4 bits Display overflow bits after addition

Pdprd : 1 bitThe display overflow bit of the position played


CS 2204 Spring 2008

Page 104

Understand Critical WiresSelplyr : 1 bit

The current player If it is 0, it is the human player, otherwise, it is the

machine player

P1SEL : 4 bits The position played by the human player

P2SEL : 4 bits The position played by the machine player

PSEL : 4 bits Position Select bits of current player

ENCPSEL : 2 bits The number of the position played

EQ : 4 bits The equality of the four displays to the digit played

NSD : 2 bits The number of similar digits, i.e. the adjacency

information of the position played


CS 2204 Spring 2008

Page 105

Understand Critical WiresRWD : 8 bits

The reward points calculated based on adjacencies In Unsigned Binary

P1PT : 8 bits Player 1 points

In Hex

P2PT : 8 bits Player 2 points

In Hex

PT : 8 bits The points of the current player

In Hex

NPT : 8 bits New player points for the current player

In Hex Ptovf : 1 bit

The points overflow if it is 1, the new player points is above (255)10


CS 2204 Spring 2008

Page 106

Understand Critical WiresP1add : 1 bit

Player 1 adds when it is 1

P2add : 1 bit Player 2 adds when it is 1

Add : 1 bit The current player adds when it is 1

P1skip : 1 bit Player 1 skips when it is 1

P2skip : 1 bit Player 2 skips when it is 1

P1played : 1 bit Player 1 played when it is 1

P2played : 1 bit Player 2 played when it is 1


CS 2204 Spring 2008

Page 107

Understand Critical WiresClear : 1 bit

Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so that it can play again

Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers

Shp1rds : 1 bitShows next two digits to Player 1 in state 1

Add : 1 bitShows that the current player has selected to add

Stp1pt : 1 bit Store Player 1 points

Stp2pt : 1 bit Store Player 2 points

Grd : 1 bit Signals to generate a new random digit

The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD

Bpds : 1 bitBlink one or all displays slowly

Bpdf : 1 bit Blocks a display fast after a display overflow


CS 2204 Spring 2008

Page 108

Understand Critical WiresClff : 1 bit

Clears FFs in Block 2 so that the next player can play if there is no overflow

S1 : 1 bit State 1 where when it is 1, the Ppm is in state 1

P2sturn : 1 bit Signals that Player 2 has the turn

It is 1 when the Ppm is in state 4

Sysclk : 1 bit System clock of the operation diagram at 6 Hz to the

digit played P2clk : 1 bit

The clock signal of Player 2 at 48 Hz Rdclk : 1 bit

The random digit counter clock at 192 Hz


CS 2204 Spring 2008

Page 109

Project Manager Actions and Reminders Make sure there is a CS2204 folder Make sure there is an experiment folder for

the current experimentYou can check the folder the current project is in

by selecting File -> Project Info Make sure the FPGA chip and its model are

correct when a new Xilinx project is createdYou can check the FPGA chip and its model by

selecting File -> Project Type… The selections must be as follows

• The chip : Spartan • The model : S10PC84• Speed : 3


CS 2204 Spring 2008

Page 110

Project Manager Actions and Reminders If you copy a project completely and paste it as a

new project, its schematic files cannot be worked on right away

After you open the schematics, they are all Non-Project schematics

Close all the schematics Close the schematics window Open the schematics one by one on the Project

Manager window Double click on the schematic name on the upper left side

for each schematic file


CS 2204 Spring 2008

Page 111

Project Manager Actions and Reminders When you do the first Xilinx

IMPLEMENTATION or after clearing the implementation data, you need to change implementation options before clicking on “Run” in the Implement Design Window

You can change the options by selecting Options… in the same window and then

Increase the Place & Route Level to the Highest Effort on the “Options” window

Click on the Edit Options… button for Implementation: in the Program Options area of the “Options” window

Click on Place and Route on the “Spartan Implementation Options: Default” window

Increase Router Options to 50 and 5 for both Routing Passes and Delay-Based Cleanup Passes


CS 2204 Spring 2008

Page 112

Project Manager Actions and Reminders After a successful IMPLEMENTATION

The schematic files have a check mark next to them The Design Entry button will have a check mark The IMPLEMENTATION button has a check mark (after a

delay of minutes sometimes) The PROGRAMMING button is highlighted

If not, just click in anywhere in the Flow tab area of the Project Manager window, it will be highlighted

If the IMPLEMENTATION is not successful due to errors, the IMPLEMENTATION button will have an “X” mark

The error can be because of wrong chip selection or schematic design errors

Correct them then !


CS 2204 Spring 2008

Page 113

Project Manager Actions and Reminders After a Xilinx IMPLEMENTATION, read the

Implementation Log File for errors, warnings and FPGA chip utilization

You can read the Implementation Log File by selecting Reports -> Implementation Log File

All No driver warnings must be corrected• No Driver means, the wire is not connected to any

component output All Multiple drivers warnings must be corrected

• Multiple Drivers means, a wire is connected to multiple component outputs

Most No Load warnings can be ignored• Because, the software warns that a component output

is not used, because you do not need the output• But, if a component output is needed, and not

connected, then it is an error, the output must be connected to the input of a component


CS 2204 Spring 2008

Page 114

Project Manager Actions and Reminders After performing several Xilinx IMPLEMENTATIONs, clear

the implementation data, by selecting Project -> Clear Implementation Data

Back to back Xilinx IMPLEMENTATIONs use previous implementation data that is unchanged to save time

Over time, this implementation data becomes corrupt and the bit file has errors

• Correct designs do not perform correctly on the FPGA board

Clearing the implementation data changes the implementation options to the default ones

The schematic files will keep their check marks The Design Entry button will keep its check mark But, the IMPLEMENTATION button will have a question mark The PROGRAMMING button will not be highlighted The implementation options must be changed to the required

ones again


CS 2204 Spring 2008

Page 115

Schematic Design Actions, Shortcuts & Reminders Place team info on schematics

You can enter the team info by selecting File -> Table Setup…

Place your name & a partner name on Line1: Place names of the other two partners on Line 2: On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007

Press F2 to enter the Select & Drag Mode Only, in this mode components can be deleted, rotated,

copied and pasted You can press ESC to enter the Select & Drag Mode Press F3 to get component library on screen

VCC is logic 1 GND is logic 0 To quickly locate a component, enter the first few letters

of the component in the bottom area of the SC Symbols window

To locate XOR gates, just enter letter “X” and “O”


CS 2204 Spring 2008

Page 116

Schematic Design Actions, Shortcuts & Reminders Press F4 to draw wires Press F5 to draw buses Press F7 to search for wires and components

To search for wires, select the Signal/Bus mode If the wire does not have a name, the software assigns one

that starts with a “$” symbol and ends with a “_” symbol• Use the whole name to search for a wire

To search for a component, select the Instance mode If a component does not have a name, the software assigns

one that starts with “$I” symbols followed by a number• Use the whole name to search for the component

Press F8 to start simulation quickly Press F10 to refresh the screen


CS 2204 Spring 2008

Page 117

Schematic Design Actions, Shortcuts & Reminders Press ctrl-c to copy a wire or a component selected

When components are copied, their labels are not copied !

You can copy from a schematic that belongs to another project

To open the schematic of another project, click on button in the upper left corner, then select the schematic file which will be in another folder

Press ctrl-v to paste a wire or a component Press ctrl-r/ctrl-l to rotate components right/left

Wires cannot be rotated ! You can see how a Xilinx macro is designed (the

internal structure), do a Hierarchy Push, by selecting Hierarchy -> Hierarchy Push

You can close the macro internal design screen, by selecting Hierarchy -> Hierarchy Pop


CS 2204 Spring 2008

Page 118

Schematic Design Actions, Shortcuts & Reminders Unless otherwise stated, use Xilinx macros instead of

designing them to save time Use buffers to rename wires Do not use unnecessary input/output buffers Do not use unnecessary input/output pads If you copy and paste components, their labels are not

copied and pasted by the software You will need to “source” the schematic file to copy and paste

component labels as explained in the Advanced Xilinx and Digilent Features handout

Xilinx does not have high density ROM memory components

16x1-bit and 32x1-bit They may not be used at all

• If needed, its usage is described on page 9 of the Advanced Xilinx and Digilent Features handout


CS 2204 Spring 2008

Page 119

Schematic Design Actions, Shortcuts & Reminders Drawing buses by using Draw Buses button on

the left side : Ppm buses are type None Individual wires of a bus must have names the same as

the bus name The indices of individual wires start at 0 and are up to the

number of bus wires minus 1• Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1,

NPT0 If a component generates a bus, there is no need to

draw the individual wires of the bus, unless a components needs those individual wires


CS 2204 Spring 2008

Page 120

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Place components of different sub/blocks separate from

each other to recognize them Write Comments, draw lines and rectangles and label

sub/blocks to identify them on the schematic for documentation purposes

• Use the Graphics Toolbox button on the left : Label components appropriately

Wire names follow application and block partitioning naming requirements

• Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs

Component names start with a U• Except if it is a BUF, IBUF, OBUF, IPAD or OPAD

To label a component, right click on the component and select Symbol Properties…

• Give the name in the Reference: section of the Symbol Properties window


CS 2204 Spring 2008

Page 121

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Do not leave components unused Draw short wires and label them with the same name

To label wires double click on the wire and enter the name in the Net Name: area of the pop up window

Draw wires without unnecessary turn Draw wires without tangling Draw wires around components/labels/names Do not short circuit input lines Do not short circuit output lines Do not have labels/attributes/components overlap


CS 2204 Spring 2008

Page 122

Schematic Design Actions, Shortcuts & Reminders Perform integrity tests to catch simple

errorsYou can do an integrity test of the current

schematic sheet, by selecting Options -> Integrity Test for Current Sheet

After the completion, a window may tell you to look at the Project Manager window to read about warnings detected, even if it says the test passed successfully

• Look at the Project Manager window, you will see warnings in blue

• If the last line has the Schematic Contents OK line, there is no need to correct anything


CS 2204 Spring 2008

Page 123

Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors

Press F8 to start simulation quickly You will see the SC Probes window

To select the input wires to be simulated, click on the Stimulator tool button of the SC Probes windows

Then click on the input wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the input wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting input bus wires, click on the bus wires in the increasing index order : ABUS0, ABUS1, ABUS2,…


CS 2204 Spring 2008

Page 124


Press F8 to start simulation quickly You will see the SC Probes window :

To select the output wires to be simulated, click on the Probe tool button of the SC Probes windows :

Then click on the output wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the output wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting output bus wires, click on the bus wires in the increasing index order : OBUS0, OBUS1, OBUS2,…


CS 2204 Spring 2008

Page 125


Press F8 to start simulation quickly You will see the SC Probes window :

To start the simulation, click on the Simulator button of the SC Probes window :

Once you have the simulation window on the screen You will see the input wires listed and then the output

wires on the left side of the Logic Simulator window


CS 2204 Spring 2008

Page 126


Separate the input rows from the output rows by placing a blank row between the input and output wires sets

Click on the top output wire Make selections Signal -> Empty Rows -> Insert

Combine bus bits to reduce the number of rows Click on the top bus wire which has the lowest index

(ABUS0) Press shift and simultaneously click on the highest order

bus wire (ABUS7) to select all the wires of the bus• A turquoise rectangle covers the bus wires

Right click on the turquoise rectangle and make the following selections Bus -> Combine


CS 2204 Spring 2008

Page 127


In order to simulate the circuit, the input wires must be first given new names

Click on the Select Stimulators button : • A keypad window will be shown

Select an input wire by clicking on it (it will be covered by a turquoise rectangle) and then click on any letter key on the keypad, such as “q”

• To the right of the input wire, the new name “q” is shown• To the right of “q”, the current value of the wire is shown

► If it is a single wire, the value is Hi-Z

◊ This has to be changed to have correct simulations

► If it is a bus, the value is shown as capital letter “Z”◊ This has to be changed as well for correct

simulations


CS 2204 Spring 2008

Page 128


To change the values of wires on the simulator window If it is a single wire, the value is Hi-Z :

• Just click on the Hi-Z line to make the value 0 ►The value is shown to the right of name “q” as 0• Click on the 0 value line again to make the value 1 ►The value is shown to the right of name “q” as 1

If it is a bus, the value is shown as capital letter “Z”• Click on Logical States to give a value to the bus :

►The Stimulator State Selection window will be shown• Click on the bus name, such as ABUS• Enter an appropriate Hex value in the Bus State area, such as

“FA” ► Appropriate means the Hex value must fit the width of the

bus : “FA” implies, the bus has at least eight wires

• Click on the Bus button of the Stimulator State Selection window :

►The value assigned is shown to the right of name “q” as “FA”


CS 2204 Spring 2008

Page 129


To change the values of wires on the simulator window To have a clock signal as an input follow the steps below :

• Make sure the input signal is not renamed as “q”, “w” etc.• Click on the input signal to select it• Click on the Select Stimulators button : • Click on Formula… • Double click on C1: under Clocks• Enter the following in the Edit Formula area :• 100ns=H 100ns=L

► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated ► The periodic signal has a period of 200ns or a frequency of 5MHz

• Click Accept• Click Close• You will see the C1 button on the Select Stimulators window

highlighted• Click on C1 so that the input signal is renamed C1• Click on the Simulation Step button several times :• You will see the periodic signal automatically generated and

the output values in response to that


CS 2204 Spring 2008

Page 130


Start simulating the circuit for different input combinations

If the circuit has 4 or less inputs, then simulate the circuit for all input combinations (test vectors)

• 16 or less number of input combinations (test vectors) If the circuit has more than 4 inputs, select a number of

input combinations (test vectors) then simulate the circuit for these test vectors

• Which test vectors to choose is a very important task ! To simulate the circuit, click on the Simulation Step

button several times : Observe the outputs

If they are correct, try another input combination If wrong, return to the schematic and try to figure out why

it is wrong ! If an output value is Hi-Z or Unknown, there is an error,

correct it


CS 2204 Spring 2008

Page 131

Schematic Design Actions, Shortcuts & Reminders Printing schematics

1) Double click on the Printer227 icon on your desktop and wait about a minute to allow it to affect the printing option

2) Zoom into an area of the schematic to print the area

3) Select File -> Print on the schematic window4) Change the option to Current View Only on the Print

window5) Click on Setup on the Print Window6) Change the printer to HP Printer 8150 in Room 2277) Click on Options to select Landscape printing if

necessary8) Click OK as many times as needed to print the page9) Print one copy of each area and then make copies

of the printed schematics for your partners


CS 2204 Spring 2008

Page 132

What to do if the testing on the board gives wrong results even thought the design is correct ?

If the design is absolutely correct, here are the steps to follow in sequence :

1) The FPGA board is turned on ?2) SW9 is in the PROG position ?3) The Bitronics Data Switch selects your PC ?4) The FPGA type and model are correct ?5) The implementation options are changed ?6) There are not too many levels of folders to reach the project

on the PC ?7) Clear the implementation data, close the software, restart

the software and do a new Xilinx IMPLEMENTATION Does it work now ?

8) Save the schematic file worked on in a separate folder Delete the project, recreate the project, copy the schematic

design from the saved schematic file• Does it work ?

Download the zipped project from the course web site, unzip it, copy the schematic design from the saved schematic file• Does it work ?


CS 2204 Spring 2008

Page 133

What to do if the testing on the board gives wrong results even thought the design is correct ?

9) Repeat step 7, by using your partner’s working schematic

10) Login to another PC and try steps 5 - 811) Ask from the TA to help you

a) The TA will login to your original PC and try steps 5 – 8 by using your schematic design and his/her S drive

b) The TA will login to another PC and try steps 5 – 8 by using your schematic design and his/her S drive on the new PC

c) The TA will inform the professor

12) If the project works on the second PC, inform the lab supervisor, Mr. Keni Yip that the original PC has a problem

Documents

CS 2204 Spring 2008 Digital Logic and State Machine Design Lab 8 Experiment 4 - 5