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Digital Circuits II

VHDL for Digital System Design

Code Converters, Multiplexers, and Demultiplexers using FPGA

References:

1) Text Book: Digital Electronics, 9th editon, by William Kleitz, published by

Pearson

2) VHDL for Programmable Logic, 1996, by Kevin Skahill, published by Addison

Wesley

3) Digital Design Essentials, 2002, by Richard Sandige, published by Prentice Hall

4) Fundamentals of Digital Logic with VHDL Design, 2000, by Stephen Brown and

Zvonko Vranesic, published by McGraw Hill

5) VHDL Made Easy, 1997, by David Pellerin and Douglas Taylor, Prentice Hall

Spring 2015

Paul I-Hai Lin, Professor of ECET

Dept. of Computer, Electrical and Information Technology

Indiana University-Purdue University Fort Wayne

Prof. Paul Lin

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Topics of Discussion

VHDL Comparators using IF-THEN-ELSE

Decoders Implemented in the VHDL Language

Code Converters

Multiplexers

De-Multiplexers

FPGA Design Applications Using LPMs

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Figure 8.1 Binary comparator for comparing

two 4-bit binary strings

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Figure 8.2 The 7485 4-bit magnitude

comparator: (a) pin configuration and (b)

logic symbol.

Figure 8.3 Magnitude comparison of two 8-bit binary strings (or binary

words)

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VHDL Comparator Using IF-THEN-ELSE

LIBRARY ieee; -- Figure8-5.vhd

USE ieee.std_logic_1164.ALL;

ENTITY compare_8b IS

PORT(a, b : IN std_logic_vector(7 DOWNTO 0);

agb, aeb, alb : OUT std_logic);

END compare_8b;

ARCHITECTURE arc OF compare_8b IS

SIGNAL result : std_logic_vector(2 DOWNTO 0);

BEGIN

PROCESS (a,b)

BEGIN

IF a < b THEN result <= "001";

ELSIF a = b THEN result <= "010";

ELSIF a > b THEN result <= "100";

ELSE result <= "000";

END IF;

agb <= result(2);

aeb <= result(1);

alb <= result(0);

END PROCESS;

END arc;Prof. Paul Lin 5

Figure 8.6 Flowchart showing the sequential execution

within the PROCESS.

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Figure 8.7 Simulation of the 8-bit comparator of Figure 8-4

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Figure 8.8 A BCD decoder selects the correct decimal-

indicating lamp based the BCD input

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Figure 8.10 Complete circuit for an active-Low output

octal (1-of-8) decoder

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Decoders Implemented in the VHDLFigure 8.18 Octal decoders: VHDL program using Boolean equations; (b) block

symbol file

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Figure 8.18 (Continue) (c) simulation of the decoded

waveforms

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Decoders Implemented in the VHDLFigure 8.19 Octal decoder implemented with vectors and the selected signal

assignment: (a) VHDL listing; (b) block symbol file.

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Decoders Implemented in the VHDLFigure 8.20 Octal decoder with an enable input: (a) VHDL listing; (b) block symbol file

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Decoders Implemented in the VHDLFigure 8.21 Octal decoder: (a) VHDL program using the IF-THEN-ELSE and CASE

statement; (b) block symbol file; (c ) the octal decoder with enable control

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Multiplexers

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Figure 8.44 Functional diagram of a four-line multiplexer.

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Multiplexers

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Figure 8.45 Logic diagram for a four-line multiplexer

Example 8-19: VHDL 4-Line Multiplexer

LIBRARY ieee; -- 4-line multiplexer

USE ieee.std_logic_1164.ALL; -- using the selected signal assignment

ENTITY ex8_19 IS

PORT(d :IN std_logic_vector (3 DOWNTO 0);

s : IN std_logic_vector (1 DOWNTO 0);

y : OUT std_logic);

END ex8_19 ;

ARCHITECTURE arc OF ex8_19 IS

BEGIN

WITH s SELECT

y <= d(3) WHEN "11",

d(2) WHEN "10",

d(1) WHEN "01",

d(0) WHEN "00",

'0' WHEN OTHERS;

END arc;Prof. Paul Lin 18

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Example 8-19: VHDL 4-Line Multiplexer

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De-MultiplexersFigure 8.53 4-line demultiplexer: (a) functional diagram; (b) waveform simulation

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De-MultiplexersFigure 8.56 The 74154 demultiplexer connections to route an input

signal to the S output.

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FPGA Design Applications Using LPMsExample 8-21 LMP Comparator

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FPGA Design Applications Using LPMsExample 8-22 LMP Decoder

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FPGA Design Applications Using LPMsExample 8-23 LMP Multiplexer

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FPGA Design Applications Using LPMsExample 8-23 LMP Multiplexer

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Summary & Conclusion

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