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Digital Circuits II

VHDL for Digital System Design

Flip Flops and Registers

References:

1) Text Book: Digital Electronics, 9th editon, by William Kleitz, published by

Pearson

Spring 2015

Paul I-Hai Lin, Professor of ECET

Dept. of Computer, Electrical and Information Technology

Indiana University-Purdue University Fort Wayne

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Topics of Discussion

RS-Flip Flops

D-Flip Flops (Latch), Altera Block Design and VHDL Code

• Synchronous with Gated and Clock

• Asynchronous Set and Reset

Master Slave J-K Flip Flop

• Edge Triggered

Using Altera’s LPM (Library of Parameterized Modules)

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Figure 10.1 Cross-NOR S-R Flip Flop: (a) Set condition; (b) Reset

condition

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Figure 10.2 Cross-NAND S-R Flip Flop

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Figure 10.3 Symbols for an S-R Flip Flop

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S-R Flip Flop Timing Analysis

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S-R Flip Flop Application: Storage register to remember time of day when a temperature limit switch

goes high

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Gated S-R Flip Flop

Asynchronous – output responds immediately to input

Synchronous – output responds in step with a control input

Function Table and Symbol

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Gated D Flip Flop

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Example 10-6: VHDL Description of a D-Latch

Block design file (Figure 10-17)

VHDL Design File

(Figure 10-18)

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VHDL Description of a D-Latch

Simulation file (Figure 10-19)

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Example 10-9: VHDL Description of a D Flip-Flop

Block design file (Figure 10-25)

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Example 10-9: VHDL Description of a D Flip-Flop

VHDL Code (Figure 10-26 a)

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Example 10-9: VHDL Description of a D Flip-Flop

Flow chart (Figure 10-26 b)

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Example 10-9: VHDL Description of a D Flip-Flop

Simulation file (Figure 10-27)

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Example 10-10: D Flip-Flop with Asynchronous Set and

Reset VHDL code (Figure 10-28)

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Example 10-10: D Flip-Flop with Asynchronous Set and

Reset

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Master-Slave J-K Flip-Flop

J => Set, K => Reset

Toggle mode: J = K = HIGH

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Master-Slave J-K Flip-Flop

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Edge-Triggered J-K Flip-Flop with VHDL Model

Figure 10.37 Symbols for edge-triggered J-K flip-flops: (a)

positive edge triggered; (b) negative edge triggered.

Figure 10.38 Function table for negative edge-triggered J-K flip-

flop

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Example 10.14

Block design file for the J-K flip-flop (Figure 10-41)

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Example 10.14

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VHDL Description of an Edge-Triggered J-K Flip-Flop

Figure 10.42 (b) Flow chart.

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VHDL Description of an Edge-Triggered J-K Flip-Flop

Figure 10.43 Simulation file.

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Example 10-20 Altera’s LPM Flip-Flop

Figure 10.58 The LPM_FF

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Example 10-20 Altera’s LPM Flip-Flop

Figure 10.59 The LPM D F/F simulation file

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Example 10-21 Altera’s LPM Flip-Flop with

Asynchronous Control Figure 10.60 The LPM D F/F block design file

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Example 10-21 Altera’s LPM Flip-Flop with

Asynchronous Control Figure 10.61 The LPM D F/F simulation file

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Summary & Conclusion

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