Digital Audio PLL on TSMC 0.18um Datasheet

PLLXpert Design Datasheet

User Name :- Kieran Flynn

User E-Mail :- [email protected]

Design Title :- Digital Audio PLL

Design Number :- 12364215

Submitted On :- Mon Feb 17 06:05:55 EST 2003

Target Process :- TSMC CL018G, 0.18um G Process

Table of Contents

Design CriteriaPage 2

Block DiagramPage 3

Pin DescriptionPage 4

Electrical PerformancePage 5

Jitter InformationPage 6

Output Waveforms PlotPage 9

GDSII Layout PlotPage 10

DeliverablesPage 11

GuidelinesPage 12

Applications InformationPage 13

Appendix APage 18

Appendix BPage 20

Page 1 of 23

© Copyright 2003 ParthusCeva. All rights reserved. All other trademarks are the property of their respective owners. DISCLAIMER: the information is provided "as is" without any express or impliedwarranty of any kind including warranties of merchantability, non-infringement of intellectual property, or fitness for any particular purpose. In no event shall ParthusCeva or its suppliers be liable for anydamages whatsoever arising out of the use of or inability to use the materials. ParthusCeva and its suppliers further do not warrant the accuracy or completeness of the information, text, graphics or otheritems contained within these materials. ParthusCeva may make changes to these materials, or to the products described therein, at any time without notice.

PLLXpert Clock Synthesis IPDataSheet

Understanding your PLL...

Design Details

Target Process TSMC CL018G, 0.18um G Process

Input Frequency 4.5 MHz

Input Divider 1

PFD Frequency 4.5 MHz

VCO Center Frequency 288.0 MHz

Feedback Divider 64

Buffered VCO Out Disabled

Programmable Dividers Enabled

Clock Deskew Disabled

Number of Outputs 3

Name Frequency Divider Duty Cycle Phase Cycle

Output xClk01 57.6 MHz 5 60.0% 0

Output xClk02 48.0 MHz 6 50.0% 0

Output xClk03 32.0 MHz 9 55.555% 0

Page 2 of 23




Block DiagramThis is a general block diagram which indicates that up to 10 possible output dividers, xClk01 to xClk10, can be used. This

particular PLL design contains 3 output divider(s). The output divider value(s), X, pertinent to this PLL design are indicated

in the pin description on the following page.

Figure 1. PLL Block Diagram

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Pin Descriptions

Signal Name Signal

Type

Description

Input Pins

refClk Input;D Input Clock. Nominal Frequency ; 4.5 MHz

porL Input;D Power on reset. When low the pll is reset, when high the pll is active.

sleepL Input;D Sleep mode. Turns off the PLL when low.

forceBypass Input;D Bypass PLL. When high input clock is fed through to become VCOOut

IPD0 .. IPD7 Input;D(8) Input Programmable Divider(8) is a static bus which must be set up at device power-up,

capability of dividing between 1 and 256, where IPD0 is the lsb.

FBD0 .. FBD7 Input;D(8) Feedback Programmable Divider(8) is a static bus which must be set up at device power-

up, capability of dividing between 1 and 256, where FBD0 is the lsb.

Output Pins

pllLock Output;D Goes high when Phase Detector indicates lock for 32 successive cycles of pfd clock. Will

deassert subsequently if Phase Detector indicates loss of lock. Criterion for in lock/out of

lock is programmed by PLLXpert software to change with input reference clock frequency.

sysResetL Output;D Goes high on third positive edge of the slowest output clock after pllLock is first set following

a porL cycle. (During which clocks are active). Will not deassert if pllLock subsequently

indicates loss of lock.

xClk01 Output;D Output Clock Frequency 57.6 MHz Divider 5 Duty 60.0% Phase advanced by 0 VCO Clock

Cycles

xClk02 Output;D Output Clock Frequency 48.0 MHz Divider 6 Duty 50.0% Phase advanced by 0 VCO Clock

Cycles

xClk03 Output;D Output Clock Frequency 32.0 MHz Divider 9 Duty 55.555% Phase advanced by 0 VCO

Clock Cycles

Power/Ground Pins

pllVdd Power Dedicated Vdd supply

pllGnd Ground Dedicated Ground

Table 1. PLL Pin Descriptions

Page 4 of 23




Electrical Performance

Parameter Name Term Note Typical Minimum Maximum

Input Signals

porL low time [number of refClk cycles] 3

Reference Frequency [MHz] 4.5 3.15 650.005

PFD Frequency [MHz] 4.5 3.15 5.85

Max allowed Jitter at the PFD [ps] Tjpfd 4 11500.0

Output Signals

VCO Frequency [MHz] 288.0 216.0 360.0

Random Jitter sigma (VCOOut) [pS] Rj 3 7.509 11.296

Intrinisic Deterministic Jitter peak-peak [ps] DjI 3 20 40

Deterministic Jitter due to VDD noise peak-peak [ps/mV] DjVdd 3 0.624 1.082

Random Jitter Sigma xClk01 [% of cycle] RjxN 1 0.096



Phase Matching xClkN to xClkN [ps] 5 20

xClkN Duty Cycle Deviation [ps] 1 20

Other parameters

Power Supply [V] 1.80 1.60 2.00

Junction Temperature [°C] 0.0 125

Core Power [mW] 12.3 19.5

Total Area [ sq mm ] 0.273

Loop Bandwidth [kHz] 52.62 218.67

Loop Settling Time [µs] 237

Phase Margin [°] 52.0 53.0

Input Clock Suppression [dB] 41.0 51.1

Table 2. PLL Electrical Performance

Note 1. xClkN refers to any xClk 01, 02, 03 ... 10

Note 2. The duty cycle of any given xClkN in this PLL design is atated in the Table 1 the Pin Description. This parameter

indicates the deviation from the stated duty cycle

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#Note4

#Note3

#Note3

#Note3

#Note1

#Note1

#Note1

#Note5

#Note1

Jitter Information

Figure 2. Jitter Transfer function for the PLL

Note 3 Period Jitter

Total period jitter, TPj, on the VCO clock of the PLL, may be computed from the following equation

TPj = TDj + TRj Equ 1

TDj is the total deterministic jitter and TRj is the total random jitter. Total deterministic jitter, TDj, for the PLL, may be

computed from the following equation

TDj = DjI + TDjVdd + TDjRef Equ 2

DjI, intrinsic deterministic jitter, is stated in Table 2. TDjVdd, the total deterministic jitter due to VDD noise, may be

computed from the following equation

TDjVdd = DjVdd*Vnoise Equ 3

DjVdd, deterministic jitter due to VDD noise, is stated in Table 2.Vnoise is the amplitude of the (pllVdd/pllVddCore) VDD

noise (expressed in mV) present in the system.

TDjRef, total deterministic jitter due to reference clock jitter, may be computed from the following equation

TDjRef = DjRef(f1) + DjRef(f2) + DjRef(f3) + ......... Equ 4

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DjRef(f), deterministic jitter due to a reference clock jitter occurring at a frequency, f, may be computed from the transfer

function shown in Fig 2 and the following equation

DjRef(fmod) = (Tvco/Tref)*Aref*gain(fmod) Equ 5

Aref is the amplitude of the jitter on the reference clock (peak-peak, expressed in ps), and fmod is the rate (frequency) at

which the jitter is occurring. Tref is the period of the reference clock and Tvco is the period of the VCO clock. The gain at

fmod can be estimated from the transfer function and converted from dB to absolute gain before applying in [Equ 5] as

`gain(fmod)'. Total random jitter, TRj, for the PLL must be computed in the context of the reliability of the system being

designed. TRj can be computed from the following equation.

TRj = NumberOfSigma*Rj Equ 6

Rj, the random jitter sigma, is stated in Table 2. Total period jitter, TPj, defines a region where a clock edge is to occur.

The question for the designer is how often can an edge occur outside this defined region? If the answer is 3 in every 1000

edges then the percentage reliability required is at least 99.7%. Using Table 3 the appropriate number of sigma,

NumberOfSigma, is 6. TPj can be computed from the following equation.

TPj = TDj + (6*Rj)

For a reliability of 99.9999998% or 2 in every 1e9 edges then the relevant equation is

TPj = TDj + (12*Rj)

For a commonly used error rate in communications of 1 in every 1e12 edges the requirement for the random component is

14*Rj. Clearly the more reliable the system the greater the number of Rj's included in the equation for TPj. Table 3 shows

Rj versus reliability. (Note Rj is denoted by σ in Table 3

Number of σ's % Area under normal curve

±1σ (2σ) 68.2689

±2σ (4σ) 95.45

±3σ (6σ 99.73

±4σ (8σ) 99.9937

±5σ (10σ) 99.9999437

±6σ (12σ) 99.9999998

±7σ (14σ) 99.9999999

Table 3. Rj(σ) versus percentage reliability

When computing the TPj on an output clock other than the VCO clock, convert the Rjx value for the output clock to an Rj

value using the following equation

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Rj = Rjx/(Fout*100) Equ 7

where Fout is the frequency of the output clock, expressed in Hz. (The resulting Rj will be in units of ps) The TPj can the

be computed using the equations given above.Refer to Appendix B.1 for a sample period jitter calculation.

Note 4 Max allowable jitter at the PFD

The TjPfd specification is used to ensure the correct operation of the lock detect circuitry. However jitter of this order on

the pfd clock may have significant impact on both period and tracking jitter. Note [3] and [5] discuss these effects.

Note 5 Phase skew between the reference clock and the VCO clock

To compute the worst case phase skew, PS, between the reference clock and the VCO clock, the user must complete the

following calculations. (Note: PS is the magnitude of the phase skew. The reference clock may lead or lag the VCO clock

by this amount)

PS = Spo + PSdyn Equ 8

Spo, the static phase offset, is stated in Table 2 and PSdyn is the dynamic phase skew PSdyn may be computed from the

following equation

PSdyn = (DriftI/2) + TDtrRef Equ 9

DriftI is stated in Table 2. TDtrRef is a measure of the PLL's ability to track a determinsitic modulations on the reference

clock. This may be computed from the following equation

TDtrRef = DtrRef(f1) + DtrRef(f2) + DtrRef(f3) + ......... Equ 10

DtrRef(f) is a measure of the PLL's ability to track a modulation on the reference clock occurring at a frequency, f. This

may be computed from the transfer function shown in Fig 2 and the following equation

DtrRef(fmod) = (Aref/2)*(|1-gain(fmod)|) Equ 11

Aref is the amplitude of the modulation on the reference clock (peak-peak, expressed in ps), and fmod is the rate

(frequency) at which the modulation is occurring. The gain at fmod can be estimated from the transfer function and

converted from dB to absolute gain before applying in [Equ 11] as `gain(fmod)'. Refer to Appendix A.2 for a sample phase

skew calculation.

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Waveforms Plot

Figure 3. Waveform Plot

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GDS Layout

This image has been generated from the GDS II layout for your entered design.

Measured from the top left-hand corner of the pll below the horizontal dimension is

606.9 µm and the vertical dimension is 543.1 µm

Figure 4. The PLL GDS

Page 10 of 23




Deliverables

Verilog/VHDL Behavioral Model

Registered Users and Licensees can receive a Verilog/VHDL Behavioral Model and Test Bench for the PLL described in

this datasheet. The Verilog/VHDL model is a high level behavioral model intended to demonstrate the basic functionality of

the PLL under normal operating conditions. To understand the PLL interface run the sample Verilog/VHDL Test Bench

provided and examine both inputs and outputs. This model can be used in conjunction with the digital system to verify

connectivity.

The Verilog/VHDL Model has the following characteristics:

• The Verilog/VHDL Behavioral Model responds to a defined start-up sequence and produces the correct outputs.

• The Verilog/VHDL Model does not support jitter on the reference clock or any kind of frequency and/or phase variation or

slip of the reference clock.

• If the model is operated outside the specified frequency range it will not work correctly. Out of bounds operation is

highlighted in the model by

• Setting the VCOOut to 'X' i.e. do not care.

• pllLock will be cleared.

• xClkN will not run.

• This out-of-bounds condition is a 'hard' cut-off point in the Verilog/VHDL model. The PLL exhibits a soft degradation

characteristic outside the specified design range. Performance is not gauranteed under such conditions - hence the hard

cut-off in the Verilog/VHDL.

• In a PLL with field programmable dividers a Power on Reset is needed subsequent to a change in the divider bus value.

Similarly if the model is driven to an "out of bounds" condition a Power on Reset is required.

• The Verilog/VHDL Model does not include a loop filter. This is due to speed constraints. Consequently there are

limitations to the model. For example when the reference clock is taken away, the output clocks die away immediately. In

silicon, however, the output clocks will decay away slowly due to the time constant of the filter.

• SETTLINGTIME is a defined parameter in the Verilog/VHDL model. An alternative setting for SETTLINGTIME is included

in the Testbench. This setting is commented out, but it shows how the user might alter the parameter. Sometimes this is

done to speed up a silmuation.

Cadence Compatible .Lef File

The .Lef File provided to Registered Users and Licensees is a Cadance Compatible file. It provides abstract information

such as metal layer obstructions, boundary and pin positions for place and route purposes. Information contained in the

Lib file allows a P&R tool to instantiate the PLL into a higher level design.

Synopsys .Lib File

The .Lib file is used for static timing analysis. It is a boundary description of the PLL and contains details of pin

capacitance loading and drive strength. The .Lib file is not a behavioral model. It does not model timing through the PLL

block.

Page 11 of 23




Guidelines

Layout

The GDS II produced by PLLXpert has been tested for compliance with the following DRC and LVS Decks, to which

ParthusCeva have applied the modifications as outlined in Appendix A.

• DRC CalibreDrc_0.18um_logic_salicide_1.8V/3.3V_1P6M_V2.3a

• LVS CalibreLvs_0.18um_logic_salicide_1.8V/3.3V_1P6M_V1.9d

When integrating the PLL GDSII into a higher level design the following basic guidelines should be considered.

• It is recommended that the PLL should be manually located into the higher level assembly and should be placed close to

the edge of the chip and as close as possible to the reference clock. Placing the PLL close to the reference clock reduces

the possibility of any noise or jitter being picked up by the reference clock before it enters the PLL.

• The ParthusCeva PLL uses 4 metals. The LEF file indicates metal blocking up to 6 metal layers. This is done to prevent

unwanted noisy tracks running over the PLL. If less than 6-metals are being used then the upper blocking layers should be

ignored. If more than 6 metals are being used metal blocking should be enabled on these layers also.

• The pllVdd and the pllGnd pins are located on the guard band that encloses the PLL. A dedicated PLL power supply

pllVdd should be connected at this location. The line connections between pllGnd and pllVdd should be constrained to

have a resistance of less than 1�. If possible double bond pllVdd and pllGnd from the pads to the package pins. Avoid IR

drops in the supply.

• The guard band has been designed to provide isolation for the PLL from any adjacent circuitry. This isolation should be

sufficient such that no additional spacing outside the guard band should be required when placing adjacent circuits.

• It is recommended that non-epi material be used.

Routing

If using 2 or more output clocks from the PLL block then care must be taken not to route these clocks too close together

over a long distance otherwise capacitive coupling between metal tracks will cause crosstalk. Recomended separation

distance is at least 1µm. Figure 5 below describes a routing method for the case where all 10 output dividers are used and

its necessary to route the inner 5 output dividers out through the narrow routing channel allocated in the lef file.

Figure 5. Routing Example

Page 12 of 23




Applications

Programmable Dividers

The Programmable Divider option enables eight bit control of the input and feedback dividers. These dividers can be set to

any integer divider ratio from 1 to 256. The dividers can be programmed via an eight bit register. To set a divider ratio of N

the divider bus must be set to N-1. For example to set a divider ratio of 1 the register should be programmed to 00000000

and for a ratio of 256 the register should be programmed to 11111111.

It should be noted that no hard limits for the divider ratios are established in any delivered GDSII. Thus divider ratios are

selectable which may drive the PLL outside of its specified design range. It is the responsibility of the user to ensure that

any controlling program is designed to limit the range of selectable divider ratios to those that maintain PLL operation

within the specified design range

It should be noted that these these dividers should always be configured while the porL input to the PLL is low.If using an

on-chip register to store divider values do not use sysResetL as the reset on this register, use porL

Table 4 contains an illustration of the divider settings for a number of PLL configurations. In this example it is assumed that

a PLL has been designed using the following design criteria.

Input Ref Clock 30 MHz

M ( input divider ratio ) 5

VCO Frequency ( nominal ) 300 MHz

N ( feedback divider ratio) 50

Programmable Dividers Enabled

From the design specifications for the ParthusCeva IP we can identify that the design has the following frequency

capabilities.

VCO Frequency Range ±25% 225 MHz - 375 MHz

PFD Frequency ( nominal ) Input Ref Clock ( nominal ) / ( M ( nominal ) 6 MHz

PFD Frequency Range ±30% 4.2 MHz - 7.8 MHz

Example 1 in Table 4 illustrates a nominal configuration achieved by selecting divider ratios that allow for operation of the

PLL at the center frequency of both the Ref Clock and the VCO.

Example 2 in Table 4 illustrates a configuration that exercises the lower design limit of the VCO frequency range by

selecting a feedback divider ratio of 40.

Example 3 in Table 4 illustrates a configuration that clearly exceeds the lower design limit of the VCO frequency range

when a feedback divider ratio of 30 is selected without making any compensating adjustment to the Reference Clock or

Input Divider Ratio. Whilst it is the case that ParthusCeva PLLs exhibit a soft degradation characteristic outside the

specified design range, performance is not guaranteed under such conditions.

Example 4 in Table 4 illustrates a configuration that takes advantage of the flexible input frequency range using an above

center 35 MHz Ref Clock but maintains the VCO center frequency by selecting a different set of divider ratios to that used

in Example 1.

Page 13 of 23




Example 5 in Table 4 illustrates a configuration that exercises the upper design limit of the VCO frequency range by

selecting a feedback divider ratio of 75.

Example 6 in Table 4 illustrates a configuration that clearly exceeds the upper design limit of the VCO frequency range

when a feedback divider ratio of 90 is selected without making any compensating adjustment to the Reference Clock or

Input Divider Ratio. Whilst it is the case that ParthusCeva PLLs exhibit a soft degradation characteristic outside the

specified design range, performance is not guaranteed under such conditions.

Ex No ErefClk Input ( M )

ratio

Input Register PFD Frequency Feedback

( N ) ratio

Feedback Register VCO

Frerquency

1 30 MHz 5 (4)00000100 6 MHz 50 (49)00110001 300 MHz

2 30 MHz 5 (4)00000100 6 MHz 40 (39)00100111 240 MHz

3 30 MHz 5 (4)00000100 6 MHz 30 (29)00011101 180 MHz

4 35 MHz 7 (6)00000110 5 MHz 60 (59)00111011 300 MHz

5 35 MHz 7 (6)00000110 5 MHz 75 (74)01001010 375 MHz

6 35 MHz 7 (6)00000110 5 MHz 90 (89)01011001 450 MHz

Table 4. Example Feedback divider settings

PLLLock signal

(Note : pfdClk = refClk/InputDivider and fbClk = vcoClk/FeedbackDivider)

The output signal "pllLock" goes high when the phase frequency detector indicates lock for 32 consecutive cycles of the

pfdClk. The phase frequency detector indicates lock when the pfdClk and the fbClk are within 15.0ns of each other.

The "sysResetL" signal goes high on the third positive edge of the slowest clock after "pllLock" is first set. It will not

deassert if "pllLock" subsequently indicates loss of lock. "sysResetL" is only cleared if it gets "porL" or "sleepL".

Deskew Delay

In order to avoid instability there is a maximum deskew delay that can be introduced into the feedback path between

VCOOut and VCODelayed. If a deskew PLL has deskew selected then the value of the Maximum deskew delay Mdd is

stated in table 2

Page 14 of 23




Figure 6. Deskew Delay

1) In this example, the delay through the clkTreeBuffer has been deskewed by placing it in the feedback path. The rising

edge of refClk and the rising edge of VCODelayed will be aligned.

2) In this example, the delay through the on-chip buffer 'b1' has been deskewed by placing a matching buffer 'b2' in the

feedback path. The rising edge of extRefClk and the rising edge of VCOOut will be aligned.

3) In this example, both the on-chip buffer 'b2' and the clkTreeBuffer have been deskewed by placing them in the feedback

path. The rising edge of refClk and the rising edge of the clkToChip will be aligned.

The user should use note [3], Phase skew between the reference clock and the VCO clock, to determine the quality of the

alignment.

Note the pllLock indication does not guarantee that the deskew spec is met. If the user requires an indicator for when the

PLL is within the deskew spec then a counter approximately 1000.00µs long should be built. This counter will begin

counting when pllLock goes high.

When implementing this delay buffer ensure that minimal jitter is added to the VCODelayed signal by having fast transition

times and a clean supply for the buffer.

If the user has selected programmable dividers and wishes to deskew to an output clock other than the VCO clock, then

the user may do so with the following requirements and limitations.

1) The appropriate output clock must tied to VCODelayed via the required delay.

2) The feedback divider bus FBD must be set using the following equation

FBD = (N/X)-1

where N is the required feedback divider ratio and X is the divide ratio of the output divider. A limitation of this equation is

that N must be an integer multiple of X.

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3) The limitation of this scheme is that for a fixed reference clock frequency, the integer multiples of VCO frequency that

are achievable have been reduced by X.

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PLLXpert is a Division of ParthusCeva which specializes in the design and development of Clock Synthesis Technology

and IP.

Generations of ParthusCeva Clock Synthesis blocks similar to the one described in this datasheet have been used by

ParthusCeva in its world leading platform level intellectual property solutions spanning such demanding applications as

• Transceivers for gigabit serial communiations.

• Baseband processors with demanding bit error rate requirements for GPS and mobile wireless communications.

• Fast DSP solutions for graphics and media processing.

Licensees of these platforms include 3Com, Agilent, Cirrus Logic, Fujitsu, HP, Hitachi, Motorola, National Semiconductor,

Nvidia, STMircoelectronics, Texas Instruments, and Sharp Microelectronics

The Clock Synthesis Block design featured in this datasheet is based on a design that has been verified by testing and

simulation using the ParthusCeva generic test chip. An evaluation report on the test chip is available and can be

downloaded by Registered Users from the pllxpert.com website.

The standard clock synthesis blocks available from PLLXpert Online can be licensed on an individual pay as you use basis

or, depending on your anticipated annual demand, can be licensed in sets of 5 or 10. For further details of licensing fees

and conditions please contact your nearest local representative who's details are provided below.

Custom and semi-custom variants of the standard designs can also be supplied and will be quoted on request.

ParthusCeva. (Europe)Building 2,University Technology Park,Curraheen Road,Bishopstown,Cork,Ireland.tel: +353 21 480 1900fax: +353 21 480 1901

ParthusCeva. (USA)2033 Gateway Place,Suite 150,San Jose.CA 95110-1002.tel: +1 408 514 2900fax: +1 408 514

ParthusCeva. (Asia/Pacific)801 Stanhope House,738 King's Road,Hong Kong.tel: + 852 2590 6881fax: + 852 2590 6977

Global e-mail•[email protected]•[email protected]

Page 17 of 23




Appendix A

drc.template

LAYOUT PATH "TOPCELLNAME.gds"

LAYOUT PRIMARY "TOPCELLNAME"

LAYOUT SYSTEM GDSII

DRC SUMMARY REPORT drc_summary HIER

DRC RESULTS DATABASE drc.database ASCII

DRC MAXIMUM VERTEX 199

INCLUDE "../newest_rules.drc"

extract.template

LAYOUT PATH "TOPCELLNAME.gds"


LAYOUT ERROR ON INPUT YES

LAYOUT SYSTEM GDSII

LVS POWER NAME VDD vdd pllVdd pllvdd avdd "DVDD!"

LVS GROUND NAME GND gnd pllGnd pllgnd agnd VSS vss "DGND!"

LVS ISOLATE SHORTS YES BY LAYER

TEXT DEPTH PRIMARY

VIRTUAL CONNECT COLON YES

MASK SVDB DIRECTORY "svdb" QUERY

INCLUDE "../newest_rules.lvs"

compare.template

LAYOUT SYSTEM SPICE

LAYOUT CASE YES

LAYOUT PATH "TOPCELLNAME.ext"


SOURCE SYSTEM SPICE

SOURCE CASE YES

SOURCE PATH "TOPCELLNAME.cdl"

SOURCE PRIMARY "TOPCELLNAME"

MASK SVDB DIRECTORY "svdb" QUERY

Page 18 of 23




LVS REPORT compare.rep

LVS REPORT OPTION A B C D

LVS REPORT MAXIMUM 50

LVS IGNORE PORTS NO

LVS POWER NAME VDD pllvdd avdd "vdd!"

LVS GROUND NAME GND VSS vss pllgnd agnd "gnd!"

LVS RECOGNIZE GATES NONE

LVS COMPARE CASE NAMES TYPES

LVS REDUCE SERIES MOS YES

LVS REDUCE PARALLEL MOS YES

LVS REDUCE PARALLEL RESISTORS YES

LVS REDUCE SERIES RESISTORS YES

LVS REDUCE PARALLEL CAPACITORS YES

LVS REDUCE SERIES CAPACITORS YES

LVS REDUCE PARALLEL DIODES YES

LVS REDUCE PARALLEL BIPOLAR YES

LVS ALL CAPACITOR PINS SWAPPABLE NO

LVS REDUCE SPLIT GATES NO

LVS PROPERTY RESOLUTION MAXIMUM 250

LVS ABORT ON SUPPLY ERROR NO

TRACE PROPERTY MP W W 0

TRACE PROPERTY MP L L 0

TRACE PROPERTY MN W W 0

TRACE PROPERTY MN L L 0

TRACE PROPERTY D A A 0

TRACE PROPERTY R R R 0.5

TRACE PROPERTY C C C 0

Page 19 of 23




Appendix B

Period Jitter

An example calculation of total period jitter. The example PLL is specified in Table B.1. The transfer function for this

example PLL is shown on Figure B.1. The example system, that the PLL resides in, is specified as follows

VDD noise 50mV peak-peak

Reference clock noise 500ps peak-peak jitter occurring at 200kHz

250ps peak-peak jitter occurring at 10MHz

The example application requires a reliability of no more than 1 in every 10000 clock edges occurring outside the defined

jitter region.

Parameter Name Term Note Typical Minimum Maximum

Input Signals

Reference Frequency [MHz] 10

PFD Frequency [MHz] 10

Max allowed Jitter at the PFD [ps] Tjpfd 2 1000

Output Signals

Random Jitter sigma (VCOOut) [ps] [1] Rj 1 5 7

Intrinsic Determinstic Jitter peak-peak [ps] DjI 1 10 20

Deterministic jitter due to VDD noise peak-peak [ps/mV] DjVdd 1 1 1.6

Intrinsic Drift between rerfClk and VCOOut peak-peak [ps] DriftI 3 2000

Static Phase Offset between refClk and VCOOut [ps] Spo 3 200

Random Jitter sigma (xClkN) [% of cycle] RjxN 1 Value

Table B.1 Example PLL Electrical Performance table

Page 20 of 23




Figure A.1. Jitter Transfer function for the example PLL

Period Jitter Calculation

Total deterministic jitter due to VDD noise

Using Equ 3 TDjVdd = 1.6*50 80ps

Total deterministic jitter due to the reference clock noise

From Fig B.1 (p1) Gain at f1(200kHz) = 0dB

gain(f1) = 10(0/20) 1

From Fig B.1 (p3) Gain at f2(10MHz) = -12dB

gain(f2) = 10(-12/20) 0.25

Using Equ 5 DjRef(f1) = (1/10)*500*1 50ps

DjRef(f2) = (1/10)*250*0.25 6.25ps

Using Equ 4 TDjRef = 50ps + 6.25ps 56.25ps

Total deterministic jitter

From Equ 2 TDj = 20ps + 80ps + 56.25ps 156.25ps

Page 21 of 23




Total random jitter

The reliability requirement is that no more than 1 in every 10000 clock edges occur outside the defined jitter

region This equates to a reliability of greater than 99.99%. Using Table 3, the number of sigma required is 8.

From Equ 6 TRj = 8*8ps 64ps

Total period jitter

From Equ 1 TPj = 156.25ps + 64 ps 220.25ps

Phase Skew

The example PLL is specified in table B.1. The transfer function for this example PLL is shown on Fig B.1. The example

system, that the PLL resides in, is specified as follows

Reference clock noise 500ps peak-peak jitter occurring at 10MHz

phase drift of peak-peak amplitude 300ps

occurring at 1MHz

Phase Skew Calculation

Total phase skew due to the reference clock noise

Calculate the gain at each noise component using the transfer curve in Fig B.1

From Fig B.1 (p2) Gain at f1(1MHz) = 1dB

gain(f1) = 10(1/20) 1.122

From Fig B.1 (p3) Gain at f2(10MHz) = -12dB

gain(f2) = 10(-12/20) 0.25

Using Equ 1 DtrRef(f1) = (300ps/2)*(|1-1.122|) 18.3ps

DtrRef(f2) = (500ps/2)*(|1-0.25|) 187.5ps

Using Equ 10 TDtrRef = 18.3ps + 187.5ps 205.8ps

Total phase skew

From Equ 9 Psdyn = (800ps/2) + 205.8ps 605.8ps

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From Equ 8 PS = 200ps + 605.8ps 805.8ps

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Documents

Digital Audio PLL on TSMC 0.18um Datasheet