A Low-Voltage 4th Order Cascade Delta-Sigma Modulator in 0.18um CMOS

2450 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010

A Low-Voltage Fourth-Order Cascade Delta–SigmaModulator in 0.18-�m CMOS

Chien-Hung Kuo, Member, IEEE, Deng-Yao Shi, and Kang-Shuo Chang, Member, IEEE

Abstract—In this paper, a low-voltage fourth-order 2-2 cascadedelta–sigma �� modulator using the proposed double-sam-pling switched-operational-amplifier (SOP)-based integrator ispresented. In the analog part of the �� modulator, most of thepower consumption comes from the SOP used in the integrator.Hence, the requirement of the SOP must effectively be relaxed toreduce the power consumption of the modulator. In each cascadestage, the second-order �� modulator with a cascade-of-inte-grators input feedforward structure is used to reduce the outputswing. The second integrator output of the first stage is directlyconnected to the second stage to simplify circuit design on theanalog part. Furthermore, the double-sampling SOP-based inte-grator is also adopted to reduce the applied clock frequency byhalf. In this paper, systematic means of designing the presentedmodulator and searching the minimum current of the SOP in aspecified supply voltage are also developed. The presented ��modulator is fabricated in a 0.18- m 1P6M CMOS technology.The chip core area without PADs is 1.57 mm�. The modulatorachieves an 84-dB peak signal-to-noise plus distortion ratio andan 88-dB dynamic range in 20-kHz signal bandwidth with a clockfrequency of 2 MHz. The power consumption of the presentedmodulator core is 0.66 mW at a supply voltage of 1 V. The pre-sented modulator can also be operated in a wide range of supplyvoltages from 1.8 V down to 0.9 V without seriously degrading theperformance.

Index Terms—Analog-to-digital converter, delta–sigma modu-lator, double sampling, low voltage, switched operational amplifier(SOP).

I. INTRODUCTION

W ITH the improvement of the modern CMOS tech-nology, smaller scaled devices not only allow more

integrated circuits into a chip but also promote the operationalspeed of digital systems. Although the reduced voltage in theadvanced process can effectively decrease the power consump-tion of digital circuits, a moderate power density still needs tobe maintained while more subcircuits are integrated into a chip.Hence, it brings a great challenge in the design of low-voltagelow-power mixed-signal circuits caused by the disproportionalscaled threshold voltage to the supply.

Manuscript received October 13, 2009; revised January 17, 2010; acceptedFebruary 19, 2010. Date of publication April 29, 2010; date of current versionOctober 01, 2010. This work was supported in part by the National ScienceCouncil, Taiwan, under Grant NSC 98-2220-E-003-004 and in part by a grantof making chips from the National Chip Implementation Center (CIC). Thispaper was recommended by Associate Editor G. Manganaro.

C.-H. Kuo and D.-Y. Shi are with the Department of Applied ElectronicsTechnology, National Taiwan Normal University, Taipei 106, Taiwan (e-mail:[email protected]).

K.-S. Chang is with the Department of Research and Development, ProlificTechnology, Inc., Taipei 115, Taiwan.

Digital Object Identifier 10.1109/TCSI.2010.2046231

Fig. 1. SC integrator with the (a) conventional opamp, (b) SOP, and (c) double-output stage of the SOP.

The operational amplifier (opamp) is an essential com-ponent in switched-capacitor (SC) modulators, but theconventional ones, such as folded-cascode and telescopicopamps, suffer from the overdrive issue on floating switchesin low-voltage circuits [1]–[4]. For example, as shown inFig. 1(a), a floating switch is often needed at the output of SCintegrators to disconnect from the succeeding circuits while thenext integrator is at its integration phase. If the 0.18- m CMOSprocess and body effect are considered, the threshold voltageof devices will be close to 0.5 V. Thus, this floating switch willbe hard to be turned on in a supply voltage of 1 V.

The switched-opamp (SOP) technique provides an ingeniouscircuit skill for realizing low-voltage SC modulators[5]–[8]. As shown in Fig. 1(b), the overdrive problem onfloating switches has been overcome by switching on/off theoutput stage. Moreover, to prevent the output level from uncer-tainty, the output will be pulled high in the switching off phase.

1549-8328/$26.00 © 2010 IEEE

KUO et al.: CASCADE DELTA–SIGMA MODULATOR IN 0.18- m CMOS 2451

Fig. 2. Architecture of the presented fourth-order 2-2 CIFF�� modulator.

In low-voltage SC modulators, the limited signal poweroften requires a large sampling capacitance to obtain the targetsignal-to-noise-plus-distortion ratio (SNDR) [2]. Thus, thisheavy capacitive load would need a wideband of the SOP toprovide enough current to complete signal settling at the inte-gration phase. However, it will increase the power consumptionof the SOP. The other choice is to utilize the double-samplingtechnique to extend the duty cycle for signal settling ratherthan increasing the bandwidth of the SOP [9]–[13]. Conse-quently, the current and the power of the SOP will be reduced.Unfortunately, the output of the SOP is active only on one oftwo nonoverlapped clock phases. Hence, two SOPs would berequired to implement the double-sampling SC integrator [14].In this paper, the double-sampling integrator using two outputstages of the SOP, which has been proposed in [15], will beadopted. As shown in Fig. 1(c), only one of the differentialpaths is depicted for simplicity. Since these two output stagescan alternatively be switched [16], the double-sampling inte-grator can be synthesized by only one SOP. Hence, the appliedclock frequency can also be successfully halved [17]–[19].

This paper presents a double-sampling fourth-order cas-cade-of-integrators input feedforward (CIFF) modulatorusing the proposed SOP-based integrator [20]. In Section II, thedesign considerations of the presented modulator will be dis-cussed and analyzed, including architectures and requirementsof components used in the modulator. Section III illustratesthe implementation of the presented SOP-based fourth-orderdouble-sampling 2-2 cascade modulator. The circuit designof each building block is also described. Experimental resultsof the presented modulator will be shown in Section IV, and aconclusion will be given in Section V.

II. DESIGN CONSIDERATIONS

The architecture of the fourth-order 2-2 CIFF modulatoris shown in Fig. 2. The functions LF and LF are loop filters ofthe first and second stages, respectively. The second-order inte-gration function is chosen for loop filters to ensure the stabilityof the modulator [21]. Single-bit quantization is selected in eachstage due to the inherent linearity of data conversion and lowerpower feature compared with power-hungry dynamic elementmatching circuits. Quantization errors in these two stages aredenoted by and , respectively. Finally, the output will beobtained after the digital cancellation to the quantization error

.

Fig. 3. Linear models of the (a) conventional double-sampling CIFF��mod-ulator and (b) double-sampling CIFF�� modulator with cross-coupled outputpaths (DSCP).

A. Modulator Structure in Each Stage

The structure of the conventional double-sampling second-order CIFF modulator is shown in Fig. 3(a). The inputsignal is sampled by the individual path at different clock phases

and and then sent to its own integration path to performthe data conversion. At the end of the modulator, digital outputstreams of and will be interlaced with each other to obtaindouble number of output data in the applied clock period.

To apply the double-sampling technique to the SOP circuit,two output stages with distinct turn-on phase are utilized to ac-complish double output in a clock cycle [8], [15]. Since theoutput stages of the SOP provide different paths for integration,the linear model of the presented second-order double-samplingCIFF modulator with cross-coupled output paths (DSCP)will be represented, as shown in Fig. 3(b). Two cross-coupledintegrators are demonstrated to explicate the operation of twodifferent output stages. Two output signals of the integrator areswapped over between two sampling paths inside the loop. Thatis, each integrator transmits its output signal to the other sam-pling path for the next integration. If the SOP could provideenough gain, the mismatch error between two output stages canbe neglected, and this structure will be the same as the first one.Fortunately, the gain requirement of the SOP is not too high inthe cascade modulator. Hence, the mismatch issue couldeasily be overcome. Since the DSCP model can precisely de-scribe the SOP-based circuit, we keep the abbreviation DSCPand the structure here to contrast with the circuit implementa-tion of the SOP-based modulator.


Fig. 4. Ideal output power spectrum of the conventional second-order CIFFmodulator and the second-order DSCP CIFF �� modulator.

In the presented DSCP modulator, -domain output sig-nals in the individual path can be expressed as

(1)

(2)

where and are double-sampled inputs, and symbolsand are quantization errors. Thus, the final output can bederived as

(3)

where

(4)

As expected, the signal transfer function (STF) of unity is ob-tained. Most of the signal power will not go through the in-tegrator path, and the output swings of integrators can effec-tively be reduced. Consequently, the requirement of the SOPand the associated power consumption would be relieved, whichis particularly important for the low-voltage circuit design. Theoutput power spectra of the ideal conventional CIFF modulatorwithout double sampling and the CIFF DSCP modulatorare drawn in Fig. 4. It clearly shows that the quantization noiseof the DSCP modulator is effectively decreased in the interestband.

B. Modulator Architecture

The overall block diagram of the presented fourth-orderDSCP 2-2 cascade modulator is shown in Fig. 5. Twoanalog outputs and from the second integrator ofthe first stage are directly connected to the input of the nextstage for further noise shaping. It should be noted that a functionof the first stage quantization error is delivered to the secondstage for signal swing reduction and easy implementation, but

it complicates the digital cancellation logics, including and. Nevertheless, it is worthy to replace the inaccuracy analog

circuits with the robust digital ones. The associated functionsof digital filters are

(5)

(6)

where

(7)

(8)

(9)

(10)

Thus, the final output of the modulator can be obtained as

(11)

For the nominal coefficients given in Fig. 3(b), the functionin (11) will be equal to the denominator in (3); thus, a

double-sampling fourth-order noise-shaping technique of thesecond-stage quantization errors will be obtained. Similarly, aunity gain of the STF can also be derived from (5). To avoidthe saturation at integrator outputs and to ensure that outputs ofall integrators have approximately the same power level, signalscaling is performed, and the resulting coefficients are

, ,, and .

When the sinusoidal input signal power is 3 dB, the signalswings at outputs of integrators are shown in Fig. 6. In this simu-lation, positive and negative quantization levels are 1 and 1,respectively, and the clock frequency is 2 MHz. It is evident thatall signal swings are beneath 40% of the full scale.

C. DR

The dynamic range (DR) of the modulator can be ex-pressed as the ratio of the maximum signal power andthe sampling thermal noise [22], i.e.,

DROSR

(12)

where denotes the maximum amplitude of the sinu-soidal signal, OSR stands for the oversampling ratio, rep-resents the input sampling capacitance, indicates the Boltz-mann’s constant, and is the absolute temperature. If the signalamplitude is reduced by half due to low-voltage SC circuits, thesampling capacitance must be quadrupled to keep a constant DRof the modulator. Thus, the resulting large capacitances not onlyresult in large area but also increase the loading of the SOP. Inother words, the tradeoff between performance and power willbe intensified in low-voltage modulators. The same contentionagainst the power consumption is also hold with the increase ofOSR to the DR of the modulator. In this paper, the total power


Fig. 5. Overall block diagram of the presented fourth-order DSCP 2-2 CIFF �� modulator.

Fig. 6. Integrator output swings of the presented DSCP 2-2 CIFF ��

modulator.

consumption of the modulator must be confined to be smallerthan 900 W, so that the input sampling capacitance of 4 pF ischosen at an OSR of 100.

Since the thermal noise caused by capacitors of succeedingintegrators will be noise shaped by preceding stages, capaci-

tance values at the input of integrators would follow the criterion[6]

OSR(13)

where denotes the number of preceding integrators before thepresent one, and is the nominal gain of the th integrator.Thus, capacitances at the input of integrators after the first onecan substantially be scaled down. Nevertheless, no capacitancesmaller than 0.5 pF is chosen for the integrators after the secondone to prevent parasitics from degrading the accuracy of themodulator.

D. Jitter

Although the SC modulator is less susceptible to theclock jitter compared with the continuous-time one, the jittermodulated by the signal frequency might corrupt the signal ac-curacy as the input frequency goes high. Assume that the clockjitter has a Gaussian random distribution with the standard de-viation , and the total root-mean-square jitter power can beexpressed as [23], [24]

POSR

(14)

where is the input frequency. Fig. 7 shows the SNDR versussimultaneous effects of the signal frequency and the clock jitter.


Fig. 7. SNDR of the presented �� modulator versus the input frequency andclock jitter.

From simulation results, the presented modulator could toleratea clock jitter of 500 ps without significantly degrading the per-formance in the signal band when the standard deviation ischanging from 0 to 0.2% of the sampling period.

E. Minimum Current and Gain Requirements of the SOP

The settling behavior of the integrator is one of important in-spections in high-resolution modulators. The accuracy ofsignal settling at the final value of the integration phase dependson SOP parameters such as finite dc gain, phase margin, slewrate (SR), and unity-gain bandwidth (UGB). In other words, in-adequate parameters would result in signal distortion, and unac-ceptable harmonics would be generated. Overdesign is usuallyrequired to achieve good signal settling, but excess power mightbe consumed due to the lack of a proper design approach. Oneof our objectives is to find out the minimum required current ofthe SOP for a specified signal resolution.

When a small signal is applied to the integrator, the output ofthe integrator will linearly settle to its final value during the inte-gration phase. On the other hand, when a large swing is sampled,signal integration will force the SOP to operate in the slewingmode. In addition, a large current will start charging the loaduntil the differential input of the SOP becomes close to eachother. Then, the SOP enters the linear mode to settle the signalfor the remaining value. As depicted in Fig. 8, the transitionfrom slewing to linear settling in signal integration is graphi-cally illustrated. The time spent on the slewing and linear modesare denoted by and , and the overall time for signal inte-gration will be close to half of the sampling clock period ,i.e.,

(15)

In a finite sampling clock period, a small SR will prolong theslewing time and shorten the linear settling time for signalintegration.

If the output stage of the SOP has an enough driving current,then the SR can be described by the following equation:

SR (16)

Fig. 8. Signal settling at the output of the opamp in the integration phase.

where and represent the tail current and the compen-sating capacitance of the SOP, respectively. Since the outputstage of the SOP must be switched, the output signal will swingbetween the supply rail and the signal level. Thus, the worst caseof the slewing range would be approximately close to half of thesupply voltage.

On the other hand, to reach an -bit resolution in the linearsettling operation, the maximum time constant can be de-rived with a view to minimize the bandwidth and power con-sumption of the SOP [25], i.e.,

(17)

where is the feedback factor of the integrator. The maximumtime constant also indicates the minimum required bandwidthand tail current for a specified resolution in the linear settlingmode. Therefore, the minimum required UGB of the SOP forsignal integration can also be expressed as

(18)

where is the overdrive of the SOP input differential pair.It can be seen that the tail current is inversely proportional tothe time constant. The lesser the given tail current, the more therequired linear settling time, which shortens the slewing time ina limited integration period as (15). According to (15), (17), and(18), the minimum required tail current for the linear settlingmode can be redefined in terms of the slewing time and otherparameters. Thus

(19)

From (16) and (19), the required tail current for two operationalmodes can be plotted against the slewing time, as shown inFig. 9. The cross-point indicates the minimum tail currentthat simultaneously meets both requirements of signal slewingand linear settling in the integration period. For example, as-sume that the supply voltage is 1 V, the input overdrive is 0.2V, the clock frequency is 2 MHz, and the compensating capac-itance of the first SOP is 0.95 pF. Then, the minimum requiredtail current will be 21.608 A, and the slewing time is 22 ns,which approximates to 8.796% of the integration period. More


Fig. 9. Required tail current of the first SOP against the slewing time in slewingand linear modes.

Fig. 10. SNDR of the presented modulator versus the finite gain of the SOP, inwhich four SOPs are simulated in order.

specifically, the minimum required tail current and the slewingtime for signal integration can be deduced as

(20)

(21)

Through (16), (18), (20), and (21), we found that the SR andUGB are uncorrelated with . That is, in a specified resolution,the minimum SR and UGB will be a function of supply voltage,feedback factor, overdrive, and sampling frequency.

At the end of the integration period, the accuracy of the finalsettled value will depend on the finite gain of the SOP, as indi-cated in Fig. 8. The performance of the presented modulatoragainst the dc gain of the SOP is evaluated with a 3-dB sinu-soidal input at an OSR of 100. Fig. 10 shows the SNDR versusthe SOP gain. The simulations are performed according to theorder of the first SOP to the fourth one. Once the required gainof the SOP is determined, we will set this gain value to the cur-rent SOP and then evaluate the next one. To prevent the finitegain of the SOP from significantly degrading the performanceof the modulator, the minimum gain requirements of the SOPare 70, 70, 55, and 45 dB in sequence.

Fig. 11. (a) Nonideal integrator linear model. (b) Resulting SNDR of the pre-sented modulator versus the coefficient error in different dc gains of the SOP.

Fig. 12. SNDR of the presented modulator versus the input power.

F. Mismatches

To estimate the effect of mismatch among all paths in thepresented modulator, coefficients of integrators are assumed tohave a linear error in a range of 1% of the nominal value,uniformly distributed random errors, and with 1% of thelinear error, and opamp finite gain errors and . The linearmodel of the integrator with these nonideal effects is shown inFig. 11(a). The resulting integrator function can be expressed as

for (22)


Fig. 13. Schematic of the (a) first stage and (b) second stage of the fourth-order DSCP 2-2 CIFF�� modulator with the proposed SOP-based integrator.

where

(23)

(24)

Here, and denote the nominal and actual forward gains ofthe integrator, respectively. The feedback coefficients standfor the mismatch errors between two output stages. As shown inFig. 5, eight feedforward path coefficients are also consideredin the simulation, i.e.,

(25)

where are the nominal coefficients in feedforward paths, andis a uniformly distributed random error. Fig. 11(c) shows the

SNDR of the presented modulator against various coefficient er-rors. Each curve is determined by different gains of the SOP, in

which each point is obtained by averaging 20 simulation runswith random errors. Here, the presented modulator can tolerate0.1% variation of coefficient errors with SNDR degradation nomore than 2 dB. Toward the end of curves, SNDR values ob-tained from different gains become closer to each other, in whichthe coefficient mismatch dominates the performance of the mod-ulator. When the mismatch variation of coefficients reaches 1%,the maximum SNDR degradation will approximate to 6 dB.Thus, a careful layout should be paid attention to prevent theexcess mismatch among the signal paths from corrupting theperformance.

G. Verification

Since nonideal factors of the comparator will be noise shapedby preceding integrators, requirements of the comparator offsetand hysteresis could easily be reached. The presented fourth-


order DSCP 2-2 cascade modulator is simulated with allsynthesized parameters and nonidealities, including samplingcapacitance, clock jitter, finite gain of the SOP, coefficient error,as well as offset and hysteresis of the comparator.

Fig. 12 shows the SNDR versus the input power in threecases. The first case is the ideal modulator without signalscaling. It exhibits higher SNDR values but presents a loweroverloading level at 11 dB of the input power. The secondcase is the ideal modulator after signal scaling. The resultingpeak SNDR is shifted to the right, and the input power differ-ence between peak SNDR and zero will be approximately thesame as the ideal case. The last case is the nonideal one aftersignal scaling. The SNDR curve shows a reasonable perfor-mance, which is mainly limited by the thermal noise of the 4-pFsampling capacitance. In addition, the peak SNDR is shiftedcloser to the full scale of input power since overload harmonicsare hidden by the increasing quantization noise floor. Whenthe input power is 1 dB, the peak SNDR and the DR can befound as 95 and 97 dB, respectively, at an OSR of 100.

III. SC IMPLEMENTATION

The first-stage schematic of the presented SOP-based fourth-order DSCP cascade modulator and corresponding clocksare shown in Fig. 13(a), where only a single-ended equivalentcircuit is depicted for clearness. At the input of the modulator,the signal and DAC feedbacks share the same capacitor to re-duce the thermal noise and the output load of the SOP. To alignwith the integration phase, DAC feedback control bits q1 andqb1 are the functions of the advanced clock and comparatoroutputs and . Similar logics are arranged for the con-trol bits q2 and qb2. The SOP with double output stages is de-signed and combined with the double-sampling technique to de-crease the required clock rate and the power consumption of theSOP. Since two output stages of the SOP are turned on at twodistinct clock phases, the output signal will alternatively be in-tegrated to the other output stage of the same SOP.

In the second integrator, the input bias of the SOP is set atground level, so that the dc level-shift circuits are added to keepcharge conservation in signal integration, as shown in the dashedblock. Prior to quantization, the summation function is imple-mented by using simple SC circuits without additional SOP[26]. This is because only the polarity of the differential signalneeds to be distinguished in single-bit quantization.

As shown in Fig. 13(b), the schematic of the second stage issimilar to that of the first stage, except for input SC circuits, inwhich individual sampling and feedback capacitors are appliedto the input of this stage. The reason is that the floating switchcannot be used in sampling paths to separate the first stage fromDAC feedbacks. The output of the second integrator of the firststage is directly connected to the input of the second stage tosimplify circuit implementation.

The capacitances used after the first integrator can be scaleddown due to the noise suppression inside the loop, which ishelpful to the power reduction of the SOP. All the capacitancesused in the presented modulator are listed in Table I.

TABLE ICAPACITANCES OF THE PRESENTED CASCADE ��MODULATOR

Fig. 14. SOP with two output stages.

A. SOP

The two-stage SOP has shown the feasibility on its rela-tively large signal swing under low-voltage applications [17].The schematic of the double-output SOP is the same as [18].Fig. 14 demonstrates the sketch of the SOP, in which onlythe single-ended circuit is depicted for simplicity. The PMOSinput is biased at ground to provide enough overdrive, and theoutput common-mode level is set to to obtain a regularsignal swing. In the input stage, parts of current-source loadsare controlled by the common-mode feedback signal forbetter signal settling behavior. In the output stage, two SOPoutputs are alternatively switched on/off to cooperate with thedouble-sampling paths. Moreover, to obtain the required SR,the bias current of the output stage is determined by the tail cur-rent and the ratio of output load and compensating capacitance.The performance of this SOP is summarized in Table II.


TABLE IIPERFORMANCE SUMMARY OF THE FIRST SOP

Fig. 15. Clocked comparator and SR-latch.

As the supply voltage descends, the output swing of theSOP must be limited in a certain range to maintain all devicesworking on the saturation region. In other words, a low-voltageSOP will suffer from the nonlinear amplification when a largesignal is presented. Thus, a higher dc gain of the SOP is oftenrequired to solve this problem. In this paper, a 76-dB dc gainfor the SOP is designed to suppress the nonlinear distortion.

B. Clock Phases and Switches

The nonoverlapped clocks and are essential elementsfor normal operations of the SC modulator. The advancedclocks and are applied to the switches near input ter-minals of the SOP to diminish the clock feedthrough effect.Dummy switches are also utilized here for the same reason. Asshown in Fig. 13(a), the turn-on edge of the advanced clocks

and are aligned with the clocks and , respectively.This is done to avoid overlapping with each other due to theprocess variation. Most switches are realized by either PMOSswitches to the supply or NMOS grounding for the sake of ac-quiring enough drive. The bootstrapped input switches [27] areused to convey high swing sinusoidal waves to the input of the

modulator for measuring purposes.

C. Comparator

As shown in Fig. 15, the single-bit quantizer is realized bythe fully differential clocked comparator with an SR-latch [4].The input bias of the NMOS differential pair is set at toobtain enough overdrive in low-voltage circumstances. WhenClk is low, and are high, and complementary outputsQ and Qb will hold their former states by the following SR-latch.Meanwhile, since the comparator is in rest mode, the tail current

Fig. 16. Die microphotograph of the presented SOP-based fourth-order DSCP2-2 CIFF �� modulator.

TABLE IIIPERFORMANCE SUMMARY OF THE PRESENTED SOP-BASED

DSCP 2-2 CASCADE �� MODULATOR

of M4 will be switched off to save power. When Clk is high, thedifferential signals and will start slewing, and newcomplementary outputs will be latched by the positive feedback.

IV. EXPERIMENTAL RESULTS

The presented SOP-based fourth-order DSCP-CIFFmodulator was fabricated in a 0.18- m 1P6M CMOS process.The microphotograph is shown in Fig. 16, and the core area,excluding PADs, is 1.57 mm . The presented modulator ismeasured under a 1-V supply voltage. The positive and negativereferences are 0.75 and 0.25 V, respectively. When a 6-dBsinusoidal signal wave with a 5.62-kHz frequency is suppliedto the modulator under a sampling clock rate of 2 MHz, thepower spectrum of the first stage is then derived from the FFTof the measured 65 536-point digital output stream, as shown inFig. 17(a). The odd-order harmonic tones, which are caused bythe single-bit quantization [21], are apparent at the output of thefirst stage. As expected, the harmonics caused by the first stagecan effectively be suppressed after digital cancellation filters,and the power spectrum of the final digital output is shown inFig. 17(b). The presented modulator after signal scalingpresents the movement of the quantization noise toward theinterest band. Nevertheless, the resulting SNDR degradation isless than 0.5 dB since the thermal noise dominates the noisefloor in the interest band.


TABLE IVPERFORMANCE COMPARISON OF 1-V AND SUB-1-V �� MODULATORS

total power including buffers and I/Os without digital filtering, : A-weighted audio band,: no linear cap., : metal cap., � � �: continuous-time RC

Fig. 17. Measured output spectrum of the (a) first stage and (b) final output ofthe presented fourth-order DSCP CIFF �� modulator.

The SNDR versus the input power is plotted in Fig. 18. Themeasured peak SNR and SNDR of the presented 1-V modu-lator in 20-kHz signal bandwidth are 87 and 84 dB, respec-tively. The measured DR is 88 dB at an OSR of 100. The totalpower consumptions of the modulator, including and excludingthe output buffers, are 0.86 and 0.66 mW, respectively. The sum-marized performances of the presented modulator are listedin Table III.

Fig. 18. Experimental dynamic range of the presented modulator.

Fig. 19. Measured SNDR versus the input power.

To test the flexibility of the presented modulator withchanges in the supply voltage, the performance is measuredunder various supply values. The measured SNDR values arerecorded in Fig. 19. There is no significant degradation on theperformance of the presented modulator within a wide range ofsupply voltages from 1.8 to 0.9 V.


Table IV shows the performance of the presented modulatorwith recently published 1-V or sub-1-V modulators forcomparison. The figure-of-merit (FOM) is defined as

FOMin decibels BW

Power(26)

The listed modulators with different approaches are noted underTable IV. Chae et al. [4] show the lowest power due to theuse of inverters in the modulator instead of opamps. Comparingwith other opamp-based modulators, the proposed DSCP-CIFFmodulator exhibits the best peak SNDR and a comparable FOM.

V. CONCLUSION

This paper has described a fourth-order DSCP-CIFF 2-2 cas-cade modulator with the proposed double-sampling SOP-based integrator. The systematic means of designing the mod-ulator has been offered. Under a specified supply voltage, theminimum current of the SOP for the target resolution has beeninvestigated and derived. Furthermore, we have also noticedthat the minimum required SR and UGB can be evaluated bysupply voltage, overdrive, feedback factor, and operating fre-quency, which is helpful to the design of the modulator. Thedouble-sampling SOP-based integrator has also been validatedfrom the measurement results of a 1-V fourth-order CIFFmodulator. Experimental results have also verified the flexibilityof the presented modulator, which can be operated under awide range of supply voltages.

REFERENCES

[1] G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Hamashita, K.Takasuka, G. Temes, and U. K. Moon, “0.6-V 82-dB delta–sigma audioADC using switched- �� integrators,” IEEE J. Solid-State Circuits,vol. 40, no. 12, pp. 2398–2407, Dec. 2005.

[2] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-PowerSigma–Delta Modulator. Norwell, MA: Kluwer, 1999.

[3] M. Keskin, U. Moon, and G. C. Temes, “A 1-V 10-MHz clock rate13-bit CMOS�� modulator using unity-gain-reset opamps,” IEEE J.Solid-State Circuits, vol. 37, no. 7, pp. 817–824, Jul. 2002.

[4] Y. Chae, I. Lee, and G. Han, “A 0.7V 36�W 85dB-DR audio��mod-ulator using class-C inverter,” in Proc. ISSCC, Feb. 2008, pp. 490–491.

[5] M. Steyaert, J. Crols, and S. Gogaert, “Switched-opamp, a techniquefor realizing full CMOS switched-capacitor filters at very low volt-ages,” in Proc. ESSCIRC, 1993, pp. 178–181.

[6] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W. Sansen,“A 900-mV low-power��A/D converter with 77-dB dynamic range,”IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1887–1897, Dec. 1998.

[7] J. Sauerbrey, T. Tille, D. S. Landsiedel, and R. Thewes, “A 0.7-VMOSFET-only switches-opamp �� modulator in standard digitalCMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.1662–1669, Dec. 2002.

[8] V. S. L. Cheung, H. C. Luong, M. Chan, and W. H. Ki, “A 1-V3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetoothreceivers,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 805–816,May 2003.

[9] R. Khoini-Poorfard and D. A. Johns, “Time-interleaved oversamplingconvertors,” Electron. Lett., vol. 29, no. 19, pp. 1673–1674, Sep. 16,1993.

[10] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi,and G. C. Temes, “A noise-coupled time-interleaved delta–sigma ADCwith 4.2 MHz bandwidth, �98 dB THD, and 79 dB SNDR,” IEEE J.Solid-State Circuits, vol. 43, no. 12, pp. 2601–2612, Dec. 2008.

[11] P. Rombouts, J. Raman, and L. Weyten, “An approach to tackle quan-tization noise folding in double-sampling sigma–delta modulationA/D converters,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 50, no. 4, pp. 157–163, Apr. 2003.

[12] S. Pamarti, “A theoretical study of the quantization noise in splitdelta–sigma ADCs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.55, no. 5, pp. 1267–1278, Jan. 2008.

[13] J. McNeill, M. C. W. Coln, and B. J. Larivee, “Split-ADC: Architec-ture for deterministic digital background calibration of a 16-bit 1-MS/sADC,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437–2445,Dec. 2005.

[14] V. S. L. Cheung, H. C. Luong, and W. H. Ki, “A 1-V 10.7-MHzswitched-opamp bandpass �� modulator using double-samplingfinite-gain-compensation technique,” IEEE J. Solid-State Circuits, vol.37, no. 10, pp. 1215–1225, Oct. 2002.

[15] C. H. Kuo and S. I. Liu, “A 1-V 10.7-MHz fourth-order bandpass��modulators using two switched opamps,” IEEE J. Solid-State Circuits,vol. 39, no. 11, pp. 2041–2045, Nov. 2004.

[16] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V�� modulatorwith 80 dB SNDR and 83 dB DR using a single-phase technique,” inProc. ISSCC, Feb. 2006, pp. 74–75.

[17] V. S. L. Cheung, H. C. Luong, and W. H. Ki, “A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter,” IEEE J. Solid-StateCircuits, vol. 36, no. 1, pp. 14–22, Jan. 2001.

[18] C. H. Kuo, S. C. Chen, and K. S. Chang, “A 91 dB SOP-based low-voltage low-distortion fourth-order 2-2 cascaded delta–sigma modu-lator,” in Proc. IASTED Int. Circuits, Signals Syst., Nov. 2006, pp.199–204.

[19] P. J. Hurst and W. J. Mclntyre, “Double sampling in switched-capacitordelta–sigma A/D converters,” in Proc. IEEE Int. Symp. Circuits Syst.,1990, pp. 902–905.

[20] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta–sigma ADC topology,” Electron. Lett., vol. 37, no. 12,pp. 737–738, Jun. 2001.

[21] R. Schreier and G. C. Temes, Understanding Delta–Sigma Data Con-verters. New York: Wiley, 2004.

[22] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-�W 88-dB audiosigma–delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits,vol. 39, no. 11, pp. 1809–1818, Nov. 2004.

[23] S. Norsworthy, R. Schreier, and G. Temes, Delta–Sigma Data Con-verters: Theory, Design, and Simulation. New York: IEEE Press,1996.

[24] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto,and F. Maloberti, “Modeling sigma–delta modulator non-idealitiesin Simulink,” in Proc. IEEE Int. Symp. Circuits Syst., May 1999, pp.384–387.

[25] R. del Rio, J. M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R.Dominguez-Castro, F. Medeiro, and A. Rodriguez-Vázquez, “Highlylinear 2.5-V CMOS��modulator for ADSL�,” IEEE Trans. CircuitsSyst. I, Reg. Papers, vol. 51, no. 1, pp. 47–62, Jan. 2004.

[26] T. Christen, T. Burger, and Q. Huang, “A 0.13 �m CMOSEDGE/UMTS/ WLAN tri-mode �� ADC with �92 dB THD,”in Proc. ISSCC, Feb. 2007, pp. 240–241.

[27] M. Dessouky and A. Kaiser, “A 1 V 1 mW digital-audio modulatorwith 88 dB dynamic range using local switch bootstrapping,” in Proc.IEEE CICC, 2000, pp. 13–16.

[28] K. P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR25-kHz continuous-time delta–sigma modulator with a return-to-openDAC,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 496–507, Mar.2007.

[29] J. Ron, S. Byun, Y. Choi, H. Roh, Y. G. Kim, and J. K. Kwon, “A 0.9-V60- �W 1-bit fourth-order delta–sigma modulator with 83-dB dynamicrange,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361–370, Feb.2008.

[30] J. Wang, T. Matsuoka, and K. Taniguchi, “A 0.5 V feedforwarddelta–sigma modulator with inverter-based integrator,” in Proc. ESS-CIRC, 2009, pp. 328–331.


Chien-Hung Kuo (M’07) was born in Taipei,Taiwan, in 1965. He received the M.S. and Ph.D.degrees in electrical engineering from the NationalTaiwan University, Taipei, in 1992 and 2003,respectively.

From 1992 to 2003, he was a Lecturer withthe Technology and Science Institute of NorthernTaiwan, Taipei. In 2003, he joined the Department ofElectrical Engineering, Tamkang University, Taipei,where he was an Assistant Professor. Since 2007, hehas been with the Department of Applied Electronics

Technology, National Taiwan Normal University. His current research interestsare in mixed-signal integrated circuits and low-power analog-to-digital dataconverters.

Deng-Yao Shi was born in Changhua, Taiwan,in 1984. He received the B.S. degree in electricalengineering from the National Formosa University,Yunlin, Taiwan, in 2008. He is currently workingtoward the M.S. degree with the Department ofApplied Electronics Technology, National TaiwanNormal University, Taipei, Taiwan.

His current research interests include low-powerdelta–sigma ADCs and mixed-signal circuit design.

Kang-Shuo Chang (M’10) was born in Yilan,Taiwan, in 1982. He received the M.S. degree inelectrical engineering from Tamkang University,Taipei, Taiwan, in 2006.

Since 2006, he has been with the Departmentof Research and Development, Prolific Tech-nology, Inc., Taipei. His research interests includemixed-signal CMOS circuits and low-power ADCs.

Documents

A Low-Voltage 4th Order Cascade Delta-Sigma Modulator in 0.18um CMOS